supleed2/ELEC50010-IAC-CW
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126 commits 2 branches 0 tags 9.2 MiB
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74 commits

Author SHA1 Message Date
Ibrahim 888bb7c822 Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main 2020-12-02 14:05:59 +00:00
Ibrahim b81c2c0952 Minor sytax corrections 2020-12-02 14:03:16 +00:00
yhp19 d1d64ae747 changed control for aluop and naming 2020-12-02 21:55:17 +08:00
Ibrahim 2a6d87c7b8 Minor sytax corrections 2020-12-02 13:35:47 +00:00
Ibrahim 56dfe9e1e8 Minor sytax corrections 2020-12-02 13:35:00 +00:00
Aadi Desai bd9ae64dc2 Update hardvard.v to match ALU 2020-12-02 13:27:37 +00:00
Ibrahim c4cae70ffc Added ALUZero Output + corrected other syntax errors 2020-12-02 13:12:48 +00:00
Ibrahim 89abb5c1ed Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main 2020-12-02 12:52:37 +00:00
Ibrahim 57d15539a2 Done expect for j type, LWL/R & MLT 2020-12-02 12:51:53 +00:00
yhp19 63b017d552 added control comments 2020-12-02 15:43:30 +08:00
Aadi Desai 27cccc28b8 Added partial loads to regfile 
Partial reads are handled within the ALU
 2020-12-02 01:04:57 +00:00
Aadi Desai 3433337eba Added Regfile 
Missing partial/misaligned loads
 2020-12-01 23:04:43 +00:00
yhp19 4edcb07e1f added control 2020-12-01 15:30:57 +08:00
Aadi Desai 5a72698fec Update mips_cpu_harvard.v 
Add registerv0 testbench line
 2020-11-30 15:36:25 +00:00
Ibrahim ba192442e4 adding immediate back 2020-11-30 14:15:36 +00:00
Ibrahim e4841407e6 ALU - start - questions need addressing 2020-11-30 14:07:33 +00:00
Ibrahim 954a5b47aa
Added shamt to the deconstruction of the instruction 2020-11-30 13:50:04 +00:00
jc4419 02f3f1cbba
Program Counter - Untested 2020-11-30 16:08:58 +04:00
jl7719 841081c152 Update mips_cpu_memory.v 
Change as per constraint
 2020-11-29 17:44:08 +09:00
jl7719 7c9fc23f7e Update mips_cpu_data_memory.v to mips_cpu_memory.v 2020-11-29 17:06:18 +09:00
Aadi Desai 3b183075aa Update mips_cpu_harvard.v 
Added andlink functionality?
 2020-11-29 01:16:33 +00:00
Aadi Desai b5766a15ba Update mips_cpu_harvard.v 
Initial version, connection names to be matched to individual modules
 2020-11-29 01:04:08 +00:00
jl7719 d90b7d3971 Add data memory module 2020-11-27 15:41:14 +09:00
jl7719 e6e4f17afe Add initial coursework deliverables 2020-11-24 14:20:29 +09:00