3 commits

Author	SHA1	Message	Date
Aadi Desai	20880f6ab2	Complete avalon bus memory ... Read and write logic (including partial writes using byte enables) complete. Address is always word aligned, as handled within bus wrapper.	2020-12-16 19:20:48 +00:00
Aadi Desai	f5fea77ea7	General structure of bus memory ... Read and Write logic to be added	2020-12-16 08:42:26 -08:00
Aadi Desai	67682ecfde	Create basic bus memory block ... I/O, parameters and initial setup block included	2020-12-16 14:07:43 +00:00