supleed2/ELEC50010-IAC-CW
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Author SHA1 Message Date
ibzmo 62c7ffc32b updated ref 2020-12-20 10:32:11 +00:00
ibzmo f8dbdeaccd minor correction 2020-12-20 10:31:18 +00:00
jl7719 3dce72e26c Add more testcase for srav, srlv 2020-12-20 09:23:22 +00:00
jl7719 d3dcd92a44 Fix sllv, srlv, srav to shift by A[4:0] 2020-12-20 09:07:35 +00:00
yhp19 1458a6c619 testcase fix 3 2020-12-20 16:29:24 +08:00
yhp19 861e7899fe testcase fix 2 2020-12-20 16:03:43 +08:00
yhp19 86dcf34d6e testcase error fix 2020-12-20 15:55:15 +08:00
yhp19 81f720d03f last extra testcases 2020-12-20 15:30:20 +08:00
jl7719 7a09c7e9f7 Add sb testcase 2020-12-19 16:05:44 +00:00
jl7719 85e23d824c Add more testcases for mthi, mtlo, mult, multu 2020-12-19 15:34:35 +00:00
jl7719 0d731c74b2 Add testcases for or and ori 2020-12-19 13:13:56 +00:00
theexecutor13 7850cb65d6 fixing testcase errors 2020-12-19 11:16:39 +00:00
yhp19 3836be459f Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main 2020-12-19 19:04:39 +08:00
yhp19 cbc305b139 load instr testcase 2020-12-19 19:04:29 +08:00
jl7719 8d100e8693 Update regfile and harvard to enable register reset 2020-12-19 10:55:41 +00:00
jl7719 cecf5537b0 Fix some errors 
j-2.ref.txt fixed and removed square bracket from regfile
 2020-12-19 10:41:05 +00:00
Aadi Desai 49b7fdbe07
Update Harvard for new regfile input 2020-12-19 10:27:17 +00:00
Aadi Desai a598321539
Use base+offset[1:0] for partial loads instead of base[1:0] 2020-12-19 10:22:44 +00:00
yhp19 6797fc5a32 added some jump testcases 2020-12-19 15:24:34 +08:00
theexecutor13 3110fb19ea fixed branch instr testcase 2020-12-19 06:32:51 +00:00
yhp19 ce776e28ce added more branch instructions testcases 2020-12-19 14:15:44 +08:00
jl7719 9aa405120f Fix divu testcases and add divu-5 testcase 
Updated the edgecase ref file
 2020-12-19 05:37:54 +00:00
ibzmo 88eadf4f27 reference to with these instructions 2020-12-18 23:15:04 +00:00
ibzmo 044e972176 sll, sllv & store and set instructions still to go 2020-12-18 23:13:47 +00:00
theexecutor13 ea21975708 fixing testcases 2020-12-18 15:04:46 +00:00
yhp19 9e7a5caf82 weird cases added 2020-12-18 23:10:15 +08:00
yhp19 3e5729e642 beq testcases 2020-12-18 22:08:55 +08:00
jl7719 a59e73f746 Fix test script not being able to find src dir 
Bus fixed in previous commit
 2020-12-18 12:51:53 +00:00
jl7719 a31d41512b Rename all instruction mem init files to .instr.txt 2020-12-18 12:42:58 +00:00
jl7719 dd4f6346be Add exec folder and executable.txt back for the test to work 2020-12-18 10:51:30 +00:00
jl7719 b114d87cf3 Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main 
Merge
 2020-12-18 10:41:44 +00:00
jl7719 a4a28db189 Add stderr.txt files and diff.txt files for debugging 2020-12-18 10:41:01 +00:00
theexecutor13 bcc05cd061 Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main 2020-12-18 10:07:54 +00:00
theexecutor13 3f8393a404 add some testcases 2020-12-18 10:07:42 +00:00
jl7719 4f97fb41d8 Rename mips_cpu_memory.v to mips_cpu_harvard_memory.v 2020-12-18 09:55:41 +00:00
jl7719 f3779e1cc3 Fix div-5 testcase minor error 2020-12-18 09:24:58 +00:00
jl7719 2a7b9c2c49 Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main 2020-12-18 09:22:27 +00:00
jl7719 47a452cd6d Fix div input testcases 3,4,5 2020-12-18 09:20:00 +00:00
ibzmo 339e2b6b58 updated ref 2020-12-18 09:15:58 +00:00
Ibrahim 579dc5e008 fixed one test case 2020-12-18 09:10:46 +00:00
Ibrahim c13ed23d90 ref file for these test cases - will add complete ref file for all edge cases soon 2020-12-18 08:51:53 +00:00
Ibrahim 48e0cdfbb6 added edge cases these don't pass - please check 2020-12-18 08:48:51 +00:00
Aadi Desai 099540f6ec
Merge pull request #2 from supleed2/bus_wrapper 
Merge Bus Version and updated testcases to Main
 2020-12-17 18:25:17 +00:00
Aadi Desai 1be11d6c19 Add second store halfword testcase 
Checks that only half the word is written using load word after store halfword
 2020-12-17 10:00:18 -08:00
Aadi Desai 5c29ec2be1 Shorten testbench limit, remove custom bus script 2020-12-17 09:44:31 -08:00
Aadi Desai e513096ed8 Add missing opcodes to CtrlMemRead = 0 2020-12-17 09:43:47 -08:00
Aadi Desai 6687cb8e17 Bring read signal low with clk during read cycle 2020-12-17 09:43:04 -08:00
Aadi Desai c8344184b2 Fix sb, sh testcases 
Tried to write to instr mem + typo
 2020-12-17 09:41:55 -08:00
Aadi Desai ad394c7d7d Adding missing opcodes to CtrlMemRead 2020-12-17 09:02:58 -08:00
Aadi Desai cb29efd034 Merge branch 'main' into bus_wrapper 2020-12-17 16:46:01 +00:00