11 commits

Author	SHA1	Message	Date
Aadi Desai	6687cb8e17	Bring read signal low with clk during read cycle	2020-12-17 09:43:04 -08:00
Aadi Desai	1ae5d78b4d	Added dummy clk_enable to harvard instance, added clock kickstart after reset	2020-12-17 07:58:33 -08:00
Aadi Desai	33bb4c7538	Constant selects not working in always_ff in current iverilog	2020-12-16 14:21:26 -08:00
Aadi Desai	5e62dd82d8	Add bus vcd to gitignore, fix missing case in bus	2020-12-16 14:08:28 -08:00
Aadi Desai	da0c9aba01	Fix {} for bit duplication, remove module name from endmodule	2020-12-16 13:38:09 -08:00
Aadi Desai	1123477690	Mask address during partial writes	2020-12-13 00:15:15 +00:00
Aadi Desai	50b9dba651	Added partial writes ... SH and SB were not accounted for in previous version, partial reads are handled within regfile	2020-12-12 16:49:02 +00:00
Aadi Desai	af7645b5b0	Completed wrapper, to be tested	2020-12-11 19:45:00 +00:00
Aadi Desai	714b74ec83	Update mips_cpu_bus.v ... Added fetch/execute states. All instructions not using data memory should function	2020-12-11 19:13:11 +00:00
Aadi Desai	7997076be7	Basic Wrapper, Logic to be added	2020-12-11 10:56:34 +00:00
jl7719	e6e4f17afe	Add initial coursework deliverables	2020-11-24 14:20:29 +09:00