mirror of
https://github.com/supleed2/ELEC50010-IAC-CW.git
synced 2024-09-19 19:46:17 +00:00
Aadi Desai
714b74ec83
Added fetch/execute states. All instructions not using data memory should function
120 lines
3.6 KiB
Verilog
120 lines
3.6 KiB
Verilog
module mips_cpu_bus(
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/* Standard signals */
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input logic clk,
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input logic reset,
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output logic active,
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output logic[31:0] register_v0,
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/* Avalon memory mapped bus controller (master) */
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output logic[31:0] address,
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output logic write,
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output logic read,
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input logic waitrequest,
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output logic[31:0] writedata,
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output logic[3:0] byteenable,
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input logic[31:0] readdata
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);
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logic[1:0] state; // current state of cpu within cycle
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logic[1:0] n_state; // state to be set at next clk edge
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logic[31:0] instr_reg; // instruction register / single-word cache for current instruction
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logic clk_internal; // modulated clock to be passed to harvard cpu
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logic[31:0] harvard_instr_address; // instr addr from pc
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logic harvard_read; // harvard cpu read flag
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logic harvard_write; // harvard cpu write flag
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initial begin
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clk_internal = 1'b0;
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n_state = 2'b00;
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state = 2'b00;
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instr_reg = 32'h00000000;
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address = 32'h00000000;
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write = 1'b0;
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read = 1'b0;
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writedata = 32'h00000000;
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byteenable = 4'b0000;
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end
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always_ff @(posedge clk) begin // CLK Rising Edge
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if (waitrequest) begin
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end else begin
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case (n_state)
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2'b00: begin // fetch
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clk_internal <= 1'b1;
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state <= 2'b00;
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end
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2'b01: begin // execute
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state <= 2'b10;
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instr_reg <= readdata;
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end
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2'b10: begin // read
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end
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2'b11: begin // write
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end
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endcase // state
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end
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end
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always_ff @(negedge clk) begin // CLK Falling Edge
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case (state)
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2'b00: // nothing happens on fetch negedge
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2'b01: begin // execute negedge
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if (!harvard_read && !harvard_write) begin // instruction complete, trigger writeback
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clk_internal <= 1'b0;
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end // otherwise do nothing
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end
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endcase
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end
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always_comb begin
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if (reset) begin
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clk_internal = 1'b0;
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n_state = 2'b00;
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state = 2'b00;
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instr_reg = 32'h00000000;
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address = 32'h00000000;
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write = 1'b0;
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read = 1'b0;
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writedata = 32'h00000000;
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byteenable = 4'b0000;
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end else begin
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case (state)
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2'b00: begin
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address = harvard_instr_address;
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read = 1'b1;
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byteenable = 4'b1111;
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n_state = 2'b01;
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end
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2'b01: begin
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address = 32'h00000000;
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read = 1'b0;
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byteenable = 4'b0000;
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if (harvard_read) begin
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n_state = 2'b10; // next state is read
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end else if (harvard_write) begin
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n_state = 2'b11; // next state is write
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end else begin
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n_state 2'b00; // next state is fetch
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end
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end
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endcase // state
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end
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end
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mips_cpu_harvard mips_cpu_harvard( // Harvard CPU within wrapper
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.clk(clk_internal), // modulated clock input to allow waiting for valid data from memory, input
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.reset(reset), // CPU reset, input
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.active(active), // Is CPU active, output
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.register_v0(register_v0), // $2 / $v0 debug bus, output
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.clk_enable(1'b0), // unused clock enable, input
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.instr_address(harvard_instr_address), // instr addr from pc, output
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.instr_readdata(instr_reg), // cached instruction passed into harvard cpu, input
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.data_address(######), // output
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.data_write(harvard_write), // harvard write flag, output
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.data_read(harvard_read), // harvard read flag, output
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.data_writedata(######), // output
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.data_readdata(######) // input
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);
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endmodule : mips_cpu_bus
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