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48 lines
1.4 KiB
Verilog
48 lines
1.4 KiB
Verilog
module mips_cpu_bus(
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/* Standard signals */
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input logic clk,
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input logic reset,
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output logic active,
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output logic[31:0] register_v0,
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/* Avalon memory mapped bus controller (master) */
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output logic[31:0] address,
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output logic write,
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output logic read,
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input logic waitrequest,
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output logic[31:0] writedata,
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output logic[3:0] byteenable,
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input logic[31:0] readdata
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);
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logic[31:0] instr_reg; // instruction register / single-word cache for current instruction
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logic clk_internal; // modulated clock to be passed to harvard cpu
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always_ff @(posedge clk) begin // how/when to pass through negedge?
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if (waitrequest) begin //if waitrequest is high, do nothing
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end else begin
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//update outputs?
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end
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end
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always_comb begin
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end
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mips_cpu_harvard mips_cpu_harvard( // Harvard CPU within wrapper
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.clk(clk_internal), // modulated clock input to allow waiting for valid data from memory, input
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.reset(reset), // CPU reset, input
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.active(active), // Is CPU active, output
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.register_v0(register_v0), // $2 / $v0 debug bus, output
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.clk_enable(1'b0), // unused clock enable, input
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.instr_address(######), // output
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.instr_readdata(instr_reg), // cached instruction passed into harvard cpu, input
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.data_address(######), // output
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.data_write(######), // output
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.data_read(######), // output
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.data_writedata(######), // output
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.data_readdata(######) // input
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);
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endmodule : mips_cpu_bus
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