jl7719
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0d731c74b2
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Add testcases for or and ori
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2020-12-19 13:13:56 +00:00 |
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theexecutor13
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7850cb65d6
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fixing testcase errors
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2020-12-19 11:16:39 +00:00 |
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yhp19
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3836be459f
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Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main
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2020-12-19 19:04:39 +08:00 |
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yhp19
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cbc305b139
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load instr testcase
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2020-12-19 19:04:29 +08:00 |
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jl7719
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8d100e8693
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Update regfile and harvard to enable register reset
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2020-12-19 10:55:41 +00:00 |
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jl7719
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cecf5537b0
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Fix some errors
j-2.ref.txt fixed and removed square bracket from regfile
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2020-12-19 10:41:05 +00:00 |
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Aadi Desai
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49b7fdbe07
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Update Harvard for new regfile input
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2020-12-19 10:27:17 +00:00 |
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Aadi Desai
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a598321539
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Use base+offset[1:0] for partial loads instead of base[1:0]
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2020-12-19 10:22:44 +00:00 |
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yhp19
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6797fc5a32
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added some jump testcases
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2020-12-19 15:24:34 +08:00 |
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theexecutor13
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3110fb19ea
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fixed branch instr testcase
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2020-12-19 06:32:51 +00:00 |
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yhp19
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ce776e28ce
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added more branch instructions testcases
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2020-12-19 14:15:44 +08:00 |
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jl7719
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9aa405120f
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Fix divu testcases and add divu-5 testcase
Updated the edgecase ref file
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2020-12-19 05:37:54 +00:00 |
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ibzmo
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88eadf4f27
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reference to with these instructions
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2020-12-18 23:15:04 +00:00 |
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ibzmo
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044e972176
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sll, sllv & store and set instructions still to go
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2020-12-18 23:13:47 +00:00 |
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theexecutor13
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ea21975708
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fixing testcases
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2020-12-18 15:04:46 +00:00 |
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yhp19
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9e7a5caf82
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weird cases added
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2020-12-18 23:10:15 +08:00 |
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yhp19
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3e5729e642
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beq testcases
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2020-12-18 22:08:55 +08:00 |
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jl7719
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a59e73f746
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Fix test script not being able to find src dir
Bus fixed in previous commit
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2020-12-18 12:51:53 +00:00 |
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jl7719
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a31d41512b
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Rename all instruction mem init files to .instr.txt
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2020-12-18 12:42:58 +00:00 |
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jl7719
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dd4f6346be
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Add exec folder and executable.txt back for the test to work
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2020-12-18 10:51:30 +00:00 |
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jl7719
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b114d87cf3
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Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main
Merge
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2020-12-18 10:41:44 +00:00 |
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jl7719
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a4a28db189
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Add stderr.txt files and diff.txt files for debugging
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2020-12-18 10:41:01 +00:00 |
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theexecutor13
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bcc05cd061
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Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main
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2020-12-18 10:07:54 +00:00 |
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theexecutor13
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3f8393a404
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add some testcases
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2020-12-18 10:07:42 +00:00 |
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jl7719
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4f97fb41d8
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Rename mips_cpu_memory.v to mips_cpu_harvard_memory.v
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2020-12-18 09:55:41 +00:00 |
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jl7719
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f3779e1cc3
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Fix div-5 testcase minor error
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2020-12-18 09:24:58 +00:00 |
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jl7719
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2a7b9c2c49
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Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main
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2020-12-18 09:22:27 +00:00 |
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jl7719
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47a452cd6d
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Fix div input testcases 3,4,5
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2020-12-18 09:20:00 +00:00 |
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ibzmo
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339e2b6b58
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updated ref
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2020-12-18 09:15:58 +00:00 |
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Ibrahim
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579dc5e008
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fixed one test case
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2020-12-18 09:10:46 +00:00 |
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Ibrahim
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c13ed23d90
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ref file for these test cases - will add complete ref file for all edge cases soon
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2020-12-18 08:51:53 +00:00 |
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Ibrahim
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48e0cdfbb6
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added edge cases these don't pass - please check
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2020-12-18 08:48:51 +00:00 |
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Aadi Desai
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099540f6ec
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Merge pull request #2 from supleed2/bus_wrapper
Merge Bus Version and updated testcases to Main
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2020-12-17 18:25:17 +00:00 |
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Aadi Desai
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1be11d6c19
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Add second store halfword testcase
Checks that only half the word is written using load word after store halfword
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2020-12-17 10:00:18 -08:00 |
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Aadi Desai
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5c29ec2be1
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Shorten testbench limit, remove custom bus script
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2020-12-17 09:44:31 -08:00 |
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Aadi Desai
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e513096ed8
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Add missing opcodes to CtrlMemRead = 0
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2020-12-17 09:43:47 -08:00 |
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Aadi Desai
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6687cb8e17
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Bring read signal low with clk during read cycle
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2020-12-17 09:43:04 -08:00 |
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Aadi Desai
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c8344184b2
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Fix sb, sh testcases
Tried to write to instr mem + typo
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2020-12-17 09:41:55 -08:00 |
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Aadi Desai
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ad394c7d7d
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Adding missing opcodes to CtrlMemRead
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2020-12-17 09:02:58 -08:00 |
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Aadi Desai
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cb29efd034
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Merge branch 'main' into bus_wrapper
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2020-12-17 16:46:01 +00:00 |
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Aadi Desai
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2be1978a36
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Add initial value to npc, add JR to CtrlMemRead
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2020-12-17 08:43:58 -08:00 |
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Aadi Desai
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1ae5d78b4d
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Added dummy clk_enable to harvard instance, added clock kickstart after reset
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2020-12-17 07:58:33 -08:00 |
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Aadi Desai
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74681e8890
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Stall bus memory when reset is high
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2020-12-17 07:34:32 -08:00 |
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jl7719
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cfebb403ba
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Delete from source files and the testbench
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2020-12-17 15:02:59 +00:00 |
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jl7719
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2d9cca262d
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Fix display appearing at the end of log file
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2020-12-17 14:51:08 +00:00 |
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Aadi Desai
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e89087c127
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Bus Memory typo in bus script
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2020-12-17 06:34:42 -08:00 |
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theexecutor13
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6c400f3567
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uploading log.txt weirdness testcase
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2020-12-17 14:31:33 +00:00 |
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Aadi Desai
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2eccc5148e
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Move bus memory from rtl to testbench folder
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2020-12-17 13:58:07 +00:00 |
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Aadi Desai
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af29f22651
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Merge branch 'main' into bus_wrapper
Changes to be duplicated for bus version
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2020-12-17 13:54:26 +00:00 |
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theexecutor13
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0bdbb63f49
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Update reference.txt
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2020-12-17 21:37:17 +08:00 |
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