supleed2/ELEC40006-P1-CW
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10 commits

Author SHA1 Message Date
Kacper 719c9ede2b Added decoder logic for STR and LDR 2020-06-10 14:40:58 +01:00
Kacper 2f6cbeae56 Debugging complete! 
The CPU works now except for the multiply commands. Pipelining is next! Woooo!
 2020-06-08 23:07:52 +01:00
Kacper 24b293e24b Recompiled certain files 2020-06-08 12:10:14 +01:00
Kacper 3d9ea175cd Working on debugging 
The multiplier uses a 2 port ROM. For some reason, I cannot generate one on my machine and so I cannot change the exusting LUT ROM to remove the register outputs. If someone else can do it (Ben), that would be great.
 2020-06-07 23:23:13 +01:00
Kacper b527d5e77d Debugging CPU 2020-06-07 20:51:33 +01:00
Kacper 9a1a1da664 Complete CPU v2 (not tested) 2020-06-07 16:12:05 +01:00
Kacper 685f69a7cf Almost ready CPU 
Changed the MUX blocks into Verilog just cuz they look neater and are probably more optimised in the end. Added the LIFO stack. Working on decoder logic.
 2020-06-07 15:08:34 +01:00
Kacper 1c0032fa95 Fixed decoder and SM 2020-06-02 20:09:22 +01:00
Kacper e1acb56b66 Finished decoder 2020-05-27 18:53:03 +01:00
Kacper 5ed70dabb0 Working on datapath 2020-05-27 11:10:13 +01:00