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32 lines
684 B
Verilog
32 lines
684 B
Verilog
module DECODE
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(
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input [15:0] instr,
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input FETCH,
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input EXEC,
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input COND_result,
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output R0_count,
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output R1_en,
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output R2_en,
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output R3_en,
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output R4_en,
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output R5_en,
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output R6_en,
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output R7_en,
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output [2:0] s1,
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output [2:0] s2,
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output [2:0] s3,
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output s4,
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output RAMd_wren,
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output RAMd_en,
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output RAMi_en
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);
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wire msb, ls, [reg_ls, addr, op, Rd, Rs1, Rs2;
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assign msb = instr[15]; //MSB of the instruction word
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assign ls = instr[14]; //LOAD or STORE bit
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assign reg_ls = instr
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wire LOAD, STORE, UJMP, JMP, AND, OR, XOR, NOT, NND, NOR, XNR, MOV, ADD, ADC, ADO, SUB, SBC, SBO, MUL, MLA, MLS, MRT, LSL, LSR, ASR, ROR, RRC, NOP, STP;
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assign LOAD =
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endmodule
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