Commit graph

6 commits

Author SHA1 Message Date
Aadi Desai 4688a56452 Modified Test Program to add LDR and STR
Also fixed logic within decoder for LDR and STR
2020-06-10 15:51:51 +01:00
Aadi Desai d046242bc1 Final State before Pipelining
Debug Complete, data and instruction mifs + ram files. Test program checked
2020-06-09 22:45:20 +01:00
Kacper 2f6cbeae56 Debugging complete!
The CPU works now except for the multiply commands. Pipelining is next! Woooo!
2020-06-08 23:07:52 +01:00
Kacper 3d9ea175cd Working on debugging
The multiplier uses a 2 port ROM. For some reason, I cannot generate one on my machine and so I cannot change the exusting LUT ROM to remove the register outputs. If someone else can do it (Ben), that would be great.
2020-06-07 23:23:13 +01:00
Kacper b527d5e77d Debugging CPU 2020-06-07 20:51:33 +01:00
Kacper e1acb56b66 Finished decoder 2020-05-27 18:53:03 +01:00