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Aadi Desai 2022-06-27 15:36:05 +00:00 committed by GitHub
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321
ALU_top.bdf
View file

@ -117,7 +117,7 @@ refer to the applicable agreement for further details.
) )
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@ -149,7 +149,7 @@ refer to the applicable agreement for further details.
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@ -165,7 +165,7 @@ refer to the applicable agreement for further details.
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@ -181,55 +181,7 @@ refer to the applicable agreement for further details.
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@ -245,7 +197,7 @@ refer to the applicable agreement for further details.
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@ -261,7 +213,7 @@ refer to the applicable agreement for further details.
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@ -276,7 +228,7 @@ refer to the applicable agreement for further details.
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@ -312,7 +264,7 @@ refer to the applicable agreement for further details.
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25
ALU_top.bsf
View file

@ -110,30 +110,9 @@ refer to the applicable agreement for further details.
(port (port
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1379
CPUProject.bdf
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File diff suppressed because it is too large Load diff

1
CPUProject.qsf
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@ -64,6 +64,7 @@ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name VERILOG_FILE max_min.v set_global_assignment -name VERILOG_FILE max_min.v
set_global_assignment -name SDC_FILE CPUProject.sdc
set_global_assignment -name VERILOG_FILE LIFOstack.v set_global_assignment -name VERILOG_FILE LIFOstack.v
set_global_assignment -name VERILOG_FILE alu.v set_global_assignment -name VERILOG_FILE alu.v
set_global_assignment -name MIF_FILE LUTSquares.mif set_global_assignment -name MIF_FILE LUTSquares.mif

4
CPUProject.sdc Normal file
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@ -0,0 +1,4 @@
#This file must have the same name as your project
#Make input CLK a clock and set frequency to 100MHz (10ns period)
create_clock -name {CLK} -period 10.0 [get_ports {CLK}]

4
CPUProject.sdc.bak Normal file
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@ -0,0 +1,4 @@
#This file must have the same name as your project
#Make input CLK a clock and set frequency to 250MHz (4ns period)
create_clock -name {CLK} -period 4.0 [get_ports {CLK}]

21
LIFOstack.bsf
View file

@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 2018 Intel Corporation. All rights reserved. Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic and other software and tools, and any partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
(including device programming or simulation files), and any (including device programming or simulation files), and any
associated documentation or information are expressly subject associated documentation or information are expressly subject
@ -16,7 +16,8 @@ the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details. refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/ */
(header "symbol" (version "1.1")) (header "symbol" (version "1.1"))
(symbol (symbol
@ -65,20 +66,6 @@ refer to the applicable agreement for further details.
(text "Dout[15..0]" (rect 121 27 163 39)(font "Arial" )) (text "Dout[15..0]" (rect 121 27 163 39)(font "Arial" ))
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) )

6
LIFOstack.v
View file

@ -1,4 +1,4 @@
module LIFOstack (Din, clk, en, rst, rw, Dout, empty, full); module LIFOstack (Din, clk, en, rst, rw, Dout);
input [15:0] Din; // Data being fed to stack input [15:0] Din; // Data being fed to stack
input clk; // clock signal input input clk; // clock signal input
@ -7,8 +7,8 @@ input rst; // reset pin to clear and reinitialise stack (active high)
input rw; // 0: read, 1: write input rw; // 0: read, 1: write
output reg [15:0] Dout; // Data being pulled from stack output reg [15:0] Dout; // Data being pulled from stack
output reg empty; // goes high to indicate SP is at 0 reg empty; // goes high to indicate SP is at 0
output reg full; // goes high to indicate SP is at (slots) reg full; // goes high to indicate SP is at (slots)
reg [5:0] SP; // Points to slot to save next value to reg [5:0] SP; // Points to slot to save next value to
integer i; integer i;

18
alu.bsf
View file

@ -110,23 +110,9 @@ refer to the applicable agreement for further details.
(port (port
(pt 224 96) (pt 224 96)
(output) (output)
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(text "carry" (rect 181 91 203 103)(font "Arial" ))
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6
alu.v
View file

@ -1,4 +1,4 @@
module alu (enable, Rs1, Rs2, Rd, instr, mulresult, exec2, stackout, mul1, mul2, Rout, jump, carry, jumpflags, memaddr); module alu (enable, Rs1, Rs2, Rd, instr, mulresult, exec2, stackout, mul1, mul2, Rout, jump, memaddr);
input enable; // active LOW, disables the ALU during load/store operations so that undefined behaviour does not occur input enable; // active LOW, disables the ALU during load/store operations so that undefined behaviour does not occur
input signed [15:0] Rs1; // input source register 1 input signed [15:0] Rs1; // input source register 1
@ -13,8 +13,7 @@ output reg signed [15:0] mul1; // first number to be multiplied
output reg signed [15:0] mul2; // second number to be multiplied output reg signed [15:0] mul2; // second number to be multiplied
output signed [15:0] Rout; // value to be saved to destination register output signed [15:0] Rout; // value to be saved to destination register
output jump; // tells decoder whether Jump condition is true output jump; // tells decoder whether Jump condition is true
output reg carry; // Internal carry register that is updated during appropriate opcodes, also provides output for debugging reg carry; // Internal carry register that is updated during appropriate opcodes, also provides output for debugging
output [7:0] jumpflags;
output reg [10:0] memaddr; // address to load data from / store data to RAMd output reg [10:0] memaddr; // address to load data from / store data to RAMd
wire [5:0]opcode = instr[14:9]; //opcode of current instruction wire [5:0]opcode = instr[14:9]; //opcode of current instruction
@ -33,7 +32,6 @@ assign JC5 = (Rs1 >= Rs2);
assign JC6 = (Rs1 <= Rs2); assign JC6 = (Rs1 <= Rs2);
assign JC7 = (Rs1 != Rs2); assign JC7 = (Rs1 != Rs2);
assign JC8 = (Rs1 < 0); assign JC8 = (Rs1 < 0);
assign jumpflags = {JC1, JC2, JC3, JC4, JC5, JC6, JC7, JC8};
always @(opcode, mulresult) always @(opcode, mulresult)
begin begin

7
max_min.bsf
View file

@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 2018 Intel Corporation. All rights reserved. Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic and other software and tools, and any partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
(including device programming or simulation files), and any (including device programming or simulation files), and any
associated documentation or information are expressly subject associated documentation or information are expressly subject
@ -16,7 +16,8 @@ the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details. refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/ */
(header "symbol" (version "1.1")) (header "symbol" (version "1.1"))
(symbol (symbol

114
mul16.bdf
View file

@ -144,7 +144,7 @@ refer to the applicable agreement for further details.
(pt 160 144) (pt 160 144)
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@ -152,7 +152,7 @@ refer to the applicable agreement for further details.
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@ -160,7 +160,7 @@ refer to the applicable agreement for further details.
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@ -285,7 +285,7 @@ refer to the applicable agreement for further details.
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(text "overflow" (rect 99 113 150 127)(font "Arial" (font_size 8))) (text "overflow" (rect 99 113 150 127)(font "Arial" (font_size 8)))
(text "overflow" (rect 97 113 140 127)(font "Arial" (font_size 8))) (text "overflow" (rect 97 113 148 127)(font "Arial" (font_size 8)))
(line (pt 145 128)(pt 160 128)) (line (pt 145 128)(pt 160 128))
(unused) (unused)
) )
@ -301,7 +301,7 @@ refer to the applicable agreement for further details.
(pt 160 96) (pt 160 96)
(output) (output)
(text "result[LPM_WIDTH-1..0]" (rect 109 81 242 95)(font "Arial" (font_size 8))) (text "result[LPM_WIDTH-1..0]" (rect 109 81 242 95)(font "Arial" (font_size 8)))
(text "result[]" (rect 108 81 140 95)(font "Arial" (font_size 8))) (text "result[]" (rect 108 81 146 95)(font "Arial" (font_size 8)))
(line (pt 145 96)(pt 160 96)(line_width 3)) (line (pt 145 96)(pt 160 96)(line_width 3))
) )
(parameter (parameter
@ -426,7 +426,7 @@ refer to the applicable agreement for further details.
(pt 160 144) (pt 160 144)
(output) (output)
(text "cout" (rect 120 129 144 143)(font "Arial" (font_size 8))) (text "cout" (rect 120 129 144 143)(font "Arial" (font_size 8)))
(text "cout" (rect 120 129 140 143)(font "Arial" (font_size 8))) (text "cout" (rect 120 129 144 143)(font "Arial" (font_size 8)))
(line (pt 145 144)(pt 160 144)) (line (pt 145 144)(pt 160 144))
(unused) (unused)
) )
@ -434,7 +434,7 @@ refer to the applicable agreement for further details.
(pt 160 128) (pt 160 128)
(output) (output)
(text "overflow" (rect 99 113 150 127)(font "Arial" (font_size 8))) (text "overflow" (rect 99 113 150 127)(font "Arial" (font_size 8)))
(text "overflow" (rect 97 113 140 127)(font "Arial" (font_size 8))) (text "overflow" (rect 97 113 148 127)(font "Arial" (font_size 8)))
(line (pt 145 128)(pt 160 128)) (line (pt 145 128)(pt 160 128))
(unused) (unused)
) )
@ -442,7 +442,7 @@ refer to the applicable agreement for further details.
(pt 160 96) (pt 160 96)
(output) (output)
(text "result[LPM_WIDTH-1..0]" (rect 109 81 242 95)(font "Arial" (font_size 8))) (text "result[LPM_WIDTH-1..0]" (rect 109 81 242 95)(font "Arial" (font_size 8)))
(text "result[]" (rect 108 81 140 95)(font "Arial" (font_size 8))) (text "result[]" (rect 108 81 146 95)(font "Arial" (font_size 8)))
(line (pt 145 96)(pt 160 96)(line_width 3)) (line (pt 145 96)(pt 160 96)(line_width 3))
) )
(parameter (parameter
@ -523,6 +523,42 @@ refer to the applicable agreement for further details.
(line (pt 8 8)(pt 24 8)) (line (pt 8 8)(pt 24 8))
) )
) )
(symbol
(rect 648 56 848 152)
(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
(text "MUL1" (rect 8 75 36 92)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
(text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "NUM1[7..0]" (rect 0 0 68 19)(font "Intel Clear" (font_size 8)))
(text "NUM1[7..0]" (rect 21 43 89 62)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "NUM2[7..0]" (rect 0 0 68 19)(font "Intel Clear" (font_size 8)))
(text "NUM2[7..0]" (rect 21 59 89 78)(font "Intel Clear" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 200 32)
(output)
(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
(text "PROD[15..0]" (rect 105 27 179 46)(font "Intel Clear" (font_size 8)))
(line (pt 200 32)(pt 184 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 184 80))
)
)
(symbol (symbol
(rect 648 176 848 272) (rect 648 176 848 272)
(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8))) (text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
@ -631,42 +667,6 @@ refer to the applicable agreement for further details.
(rectangle (rect 16 16 184 80)) (rectangle (rect 16 16 184 80))
) )
) )
(symbol
(rect 648 56 848 152)
(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
(text "MUL1" (rect 8 75 36 92)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
(text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "NUM1[7..0]" (rect 0 0 68 19)(font "Intel Clear" (font_size 8)))
(text "NUM1[7..0]" (rect 21 43 89 62)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "NUM2[7..0]" (rect 0 0 68 19)(font "Intel Clear" (font_size 8)))
(text "NUM2[7..0]" (rect 21 59 89 78)(font "Intel Clear" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 200 32)
(output)
(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
(text "PROD[15..0]" (rect 105 27 179 46)(font "Intel Clear" (font_size 8)))
(line (pt 200 32)(pt 184 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 184 80))
)
)
(connector (connector
(text "B[15..8]" (rect 570 104 606 121)(font "Intel Clear" )) (text "B[15..8]" (rect 570 104 606 121)(font "Intel Clear" ))
(pt 648 120) (pt 648 120)
@ -864,6 +864,30 @@ refer to the applicable agreement for further details.
(pt 216 216) (pt 216 216)
(pt 520 216) (pt 520 216)
) )
(connector
(text "P1[15..0]" (rect 858 72 900 89)(font "Intel Clear" ))
(pt 848 88)
(pt 912 88)
(bus)
)
(connector
(text "P2[15..0]" (rect 858 192 900 209)(font "Intel Clear" ))
(pt 848 208)
(pt 896 208)
(bus)
)
(connector
(text "P3[15..0]" (rect 858 304 900 321)(font "Intel Clear" ))
(pt 848 320)
(pt 904 320)
(bus)
)
(connector
(text "P4[15..0]" (rect 858 408 900 425)(font "Intel Clear" ))
(pt 848 424)
(pt 888 424)
(bus)
)
(junction (pt 520 208)) (junction (pt 520 208))
(junction (pt 520 216)) (junction (pt 520 216))
(junction (pt 520 320)) (junction (pt 520 320))

47
mul8.bdf
View file

@ -39,7 +39,7 @@ refer to the applicable agreement for further details.
(input) (input)
(rect -752 216 -584 232) (rect -752 216 -584 232)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "NUM1[7..0]" (rect 5 0 61 12)(font "Arial" )) (text "NUM1[7..0]" (rect 5 0 62 12)(font "Arial" ))
(pt 168 8) (pt 168 8)
(drawing (drawing
(line (pt 84 12)(pt 109 12)) (line (pt 84 12)(pt 109 12))
@ -55,7 +55,7 @@ refer to the applicable agreement for further details.
(input) (input)
(rect -752 232 -584 248) (rect -752 232 -584 248)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "NUM2[7..0]" (rect 5 0 58 17)(font "Intel Clear" )) (text "NUM2[7..0]" (rect 5 0 59 17)(font "Intel Clear" ))
(pt 168 8) (pt 168 8)
(drawing (drawing
(line (pt 84 12)(pt 109 12)) (line (pt 84 12)(pt 109 12))
@ -718,7 +718,7 @@ refer to the applicable agreement for further details.
(symbol (symbol
(rect -544 192 -360 272) (rect -544 192 -360 272)
(text "max_min" (rect 5 0 49 12)(font "Arial" )) (text "max_min" (rect 5 0 49 12)(font "Arial" ))
(text "maxmin" (rect 8 64 46 76)(font "Arial" )) (text "maxmin" (rect 8 64 45 81)(font "Intel Clear" ))
(port (port
(pt 0 32) (pt 0 32)
(input) (input)
@ -737,14 +737,14 @@ refer to the applicable agreement for further details.
(pt 184 32) (pt 184 32)
(output) (output)
(text "maximum[7..0]" (rect 0 0 74 12)(font "Arial" )) (text "maximum[7..0]" (rect 0 0 74 12)(font "Arial" ))
(text "maximum[7..0]" (rect 101 27 163 39)(font "Arial" )) (text "maximum[7..0]" (rect 101 27 175 39)(font "Arial" ))
(line (pt 184 32)(pt 168 32)(line_width 3)) (line (pt 184 32)(pt 168 32)(line_width 3))
) )
(port (port
(pt 184 48) (pt 184 48)
(output) (output)
(text "minimum[7..0]" (rect 0 0 70 12)(font "Arial" )) (text "minimum[7..0]" (rect 0 0 70 12)(font "Arial" ))
(text "minimum[7..0]" (rect 104 43 163 55)(font "Arial" )) (text "minimum[7..0]" (rect 104 43 174 55)(font "Arial" ))
(line (pt 184 48)(pt 168 48)(line_width 3)) (line (pt 184 48)(pt 168 48)(line_width 3))
) )
(drawing (drawing
@ -925,6 +925,17 @@ refer to the applicable agreement for further details.
(pt -200 160) (pt -200 160)
(bus) (bus)
) )
(connector
(pt -360 240)
(pt -360 304)
(bus)
)
(connector
(text "B[7..0]" (rect -270 288 -240 305)(font "Intel Clear" ))
(pt -360 304)
(pt -160 304)
(bus)
)
(connector (connector
(pt -544 224) (pt -544 224)
(pt -584 224) (pt -584 224)
@ -967,31 +978,5 @@ refer to the applicable agreement for further details.
(pt 1024 152) (pt 1024 152)
(bus) (bus)
) )
(connector
(pt -360 240)
(pt -344 240)
(bus)
)
(connector
(pt -344 240)
(pt -344 304)
(bus)
)
(connector
(text "B[7..0]" (rect -270 288 -240 305)(font "Intel Clear" ))
(pt -160 304)
(pt -344 304)
(bus)
)
(connector
(pt -160 40)
(pt -160 304)
(bus)
)
(connector
(pt -160 304)
(pt -160 432)
(bus)
)
(junction (pt -200 160)) (junction (pt -200 160))
(junction (pt -160 304)) (junction (pt -160 304))