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47 lines
1.6 KiB
Verilog
47 lines
1.6 KiB
Verilog
module LIFOstack (Din, clk, en, rst, rw, Dout);
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input [15:0] Din; // Data being fed to stack
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input clk; // clock signal input
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input en; // disable stack when not in use
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input rst; // reset pin to clear and reinitialise stack (active high)
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input rw; // 0: read, 1: write
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output reg [15:0] Dout; // Data being pulled from stack
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reg empty; // goes high to indicate SP is at 0
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reg full; // goes high to indicate SP is at (slots)
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reg [5:0] SP; // Points to slot to save next value to
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integer i;
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reg [15:0] mem [31:0];
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always @ (posedge clk) begin
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if (!en); // if not enabled, ignore this cycle
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else begin
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if (rst) begin // if rst is high, clear memory and reset pointers/outputs
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Dout = 16'h0000;
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SP = 6'b000000;
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empty = 1'b1;
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for (i = 0; i < 32; i = i + 1) begin
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mem[i] = 16'h0000;
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end
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end
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else begin
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if (!full && rw) begin // Write when NOT full & Writing
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mem[SP] = Din; // Store data into current slot
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SP = SP + 1'b1; // Increment stack pointer to next empty slot
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full = (SP == 6'b100000) ? 1 : 0; // Stack is full if SP is (slots)
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empty = 1'b0; // Stack is never empty after a push
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end
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else if (!empty && !rw) begin // Read when NOT empty & reading
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SP = SP - 1'b1; // Decrement stack pointer to last filled slot
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Dout = mem[SP]; // Output data from last filled slot
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mem[SP] = 16'h0000; // Clear slot after setting output
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full = 1'b0; // Stack is never full after a pop
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empty = (SP == 6'b000000) ? 1 : 0; // Stack is empty if SP is 0
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end
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end
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end
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end
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endmodule
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