From 6c1f7fc59b62db001ea52fe923060b6eedac4d10 Mon Sep 17 00:00:00 2001
From: supleed2 <21363892+supleed2@users.noreply.github.com>
Date: Thu, 11 Jun 2020 16:23:16 +0100
Subject: [PATCH 1/4] Remove debug lines from ALU to improve performance

---
 alu.v | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/alu.v b/alu.v
index 85c49f1..f9205c8 100644
--- a/alu.v
+++ b/alu.v
@@ -1,4 +1,4 @@
-module alu (enable, Rs1, Rs2, Rd, opcode, mulresult, exec2, stackout, memdatain, mul1, mul2, Rout, jump, carry, jumpflags, memaddr);
+module alu (enable, Rs1, Rs2, Rd, opcode, mulresult, exec2, stackout, mul1, mul2, Rout, jump, memaddr);
 
 input enable; // active LOW, disables the ALU during load/store operations so that undefined behaviour does not occur
 input signed [15:0] Rs1; // input source register 1
@@ -8,14 +8,12 @@ input [5:0] opcode; // opcode is fed in from instruction using wires outside ALU
 input signed [31:0] mulresult; // 32-bit result from multiplier
 input exec2; // Input from state machine to indicate when to take in result from multiplication
 input [15:0] stackout; // input from stack to be fed back to registers
-input signed [15:0] memdatain; // input data from RAMd
 
 output reg signed [15:0] mul1; // first number to be multiplied
 output reg signed [15:0] mul2; // second number to be multiplied
 output signed [15:0] Rout; // value to be saved to destination register
 output jump; // tells decoder whether Jump condition is true
-output reg carry; // Internal carry register that is updated during appropriate opcodes, also provides output for debugging
-output [7:0] jumpflags;
+reg carry; // Internal carry register that is updated during appropriate opcodes
 output reg [10:0] memaddr; // address to load data from / store data to RAMd
 
 reg signed [16:0] alusum; // extra bit to hold carry from operations other than Multiply
@@ -33,7 +31,6 @@ assign JC5 = (Rs1 >= Rs2);
 assign JC6 = (Rs1 <= Rs2);
 assign JC7 = (Rs1 != Rs2);
 assign JC8 = (Rs1 < 0);
-assign jumpflags = {JC1, JC2, JC3, JC4, JC5, JC6, JC7, JC8};
 
 always @(opcode, mulresult)
 	begin
@@ -170,9 +167,6 @@ always @(opcode, mulresult)
 						if(!exec2) begin
 								memaddr = Rs1[10:0];
 							end
-						else begin
-								alusum = {1'b0, memdatain};
-							end
 					end
 				6'b101011: begin // STR Indirect Store (Mem[Rd] = Rs1)
 						memaddr = Rd[10:0];

From 87f3d0e9191b4543716ad0284a13556ce9a9279b Mon Sep 17 00:00:00 2001
From: supleed2 <21363892+supleed2@users.noreply.github.com>
Date: Thu, 11 Jun 2020 17:28:00 +0100
Subject: [PATCH 2/4] CPU set up for testing and analysis

---
 ALU_top.bdf        |  291 ++++-------
 ALU_top.bsf        |   36 +-
 CPUProject.bdf     | 1178 +++++---------------------------------------
 CPUProject.qsf     |    2 +
 CPUProject.qws     |  Bin 0 -> 673 bytes
 CPUProject.sdc     |    4 +
 CPUProject.sdc.bak |    4 +
 LIFOstack.bsf      |   21 +-
 LIFOstack.v        |    6 +-
 alu.bsf            |   57 +--
 10 files changed, 266 insertions(+), 1333 deletions(-)
 create mode 100644 CPUProject.qws
 create mode 100644 CPUProject.sdc
 create mode 100644 CPUProject.sdc.bak

diff --git a/ALU_top.bdf b/ALU_top.bdf
index 0a5ed61..785f265 100644
--- a/ALU_top.bdf
+++ b/ALU_top.bdf
@@ -118,7 +118,7 @@ https://fpgasoftware.intel.com/eula.
 )
 (pin
 	(input)
-	(rect 344 480 520 496)
+	(rect 352 448 528 464)
 	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
 	(text "CLK" (rect 9 0 30 12)(font "Arial" ))
 	(pt 176 8)
@@ -148,25 +148,9 @@ https://fpgasoftware.intel.com/eula.
 	)
 	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
 )
-(pin
-	(input)
-	(rect 344 368 528 384)
-	(text "INPUT" (rect 141 0 169 10)(font "Arial" (font_size 6)))
-	(text "memdatain[15..0]" (rect 5 0 89 17)(font "Intel Clear" ))
-	(pt 184 8)
-	(drawing
-		(line (pt 100 12)(pt 125 12))
-		(line (pt 100 4)(pt 125 4))
-		(line (pt 129 8)(pt 184 8))
-		(line (pt 100 12)(pt 100 4))
-		(line (pt 125 4)(pt 129 8))
-		(line (pt 125 12)(pt 129 8))
-	)
-	(text "VCC" (rect 144 7 164 17)(font "Arial" (font_size 6)))
-)
 (pin
 	(output)
-	(rect 800 272 976 288)
+	(rect 792 272 968 288)
 	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
 	(text "Rout[15..0]" (rect 90 0 145 12)(font "Arial" ))
 	(pt 0 8)
@@ -182,7 +166,7 @@ https://fpgasoftware.intel.com/eula.
 )
 (pin
 	(output)
-	(rect 800 288 976 304)
+	(rect 792 288 968 304)
 	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
 	(text "COND" (rect 90 0 123 12)(font "Arial" ))
 	(pt 0 8)
@@ -198,55 +182,7 @@ https://fpgasoftware.intel.com/eula.
 )
 (pin
 	(output)
-	(rect 800 304 976 320)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "CARRY" (rect 90 0 130 12)(font "Arial" ))
-	(pt 0 8)
-	(drawing
-		(line (pt 0 8)(pt 52 8))
-		(line (pt 52 4)(pt 78 4))
-		(line (pt 52 12)(pt 78 12))
-		(line (pt 52 12)(pt 52 4))
-		(line (pt 78 4)(pt 82 8))
-		(line (pt 82 8)(pt 78 12))
-		(line (pt 78 12)(pt 82 8))
-	)
-)
-(pin
-	(output)
-	(rect 768 480 944 496)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "MUL_res[31..0]" (rect 90 0 165 12)(font "Arial" ))
-	(pt 0 8)
-	(drawing
-		(line (pt 0 8)(pt 52 8))
-		(line (pt 52 4)(pt 78 4))
-		(line (pt 52 12)(pt 78 12))
-		(line (pt 52 12)(pt 52 4))
-		(line (pt 78 4)(pt 82 8))
-		(line (pt 82 8)(pt 78 12))
-		(line (pt 78 12)(pt 82 8))
-	)
-)
-(pin
-	(output)
-	(rect 800 320 976 336)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "jumpflags[7..0]" (rect 90 0 164 12)(font "Arial" ))
-	(pt 0 8)
-	(drawing
-		(line (pt 0 8)(pt 52 8))
-		(line (pt 52 4)(pt 78 4))
-		(line (pt 52 12)(pt 78 12))
-		(line (pt 52 12)(pt 52 4))
-		(line (pt 78 4)(pt 82 8))
-		(line (pt 82 8)(pt 78 12))
-		(line (pt 78 12)(pt 82 8))
-	)
-)
-(pin
-	(output)
-	(rect 800 240 976 256)
+	(rect 792 240 968 256)
 	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
 	(text "mul1[15..0]" (rect 90 0 145 12)(font "Arial" ))
 	(pt 0 8)
@@ -262,7 +198,7 @@ https://fpgasoftware.intel.com/eula.
 )
 (pin
 	(output)
-	(rect 800 256 976 272)
+	(rect 792 256 968 272)
 	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
 	(text "mul2[15..0]" (rect 90 0 145 12)(font "Arial" ))
 	(pt 0 8)
@@ -278,9 +214,9 @@ https://fpgasoftware.intel.com/eula.
 )
 (pin
 	(output)
-	(rect 800 336 976 352)
+	(rect 792 304 968 320)
 	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "memaddr[10..0]" (rect 90 0 165 17)(font "Intel Clear" ))
+	(text "memaddr[10..0]" (rect 90 0 167 12)(font "Arial" ))
 	(pt 0 8)
 	(drawing
 		(line (pt 0 8)(pt 52 8))
@@ -293,7 +229,7 @@ https://fpgasoftware.intel.com/eula.
 	)
 )
 (symbol
-	(rect 544 456 744 552)
+	(rect 552 424 752 520)
 	(text "mul16" (rect 5 0 43 19)(font "Intel Clear" (font_size 8)))
 	(text "MULTIPLIER" (rect 8 75 67 92)(font "Intel Clear" ))
 	(port
@@ -329,9 +265,9 @@ https://fpgasoftware.intel.com/eula.
 	)
 )
 (symbol
-	(rect 544 216 776 424)
+	(rect 544 216 768 392)
 	(text "alu" (rect 5 0 19 12)(font "Arial" ))
-	(text "ALU_in" (rect 8 192 43 204)(font "Arial" ))
+	(text "ALU_in" (rect 8 160 43 172)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
@@ -389,63 +325,42 @@ https://fpgasoftware.intel.com/eula.
 		(line (pt 0 144)(pt 16 144)(line_width 3))
 	)
 	(port
-		(pt 0 160)
-		(input)
-		(text "memdatain[15..0]" (rect 0 0 86 12)(font "Arial" ))
-		(text "memdatain[15..0]" (rect 21 155 107 167)(font "Arial" ))
-		(line (pt 0 160)(pt 16 160)(line_width 3))
-	)
-	(port
-		(pt 232 32)
+		(pt 224 32)
 		(output)
 		(text "mul1[15..0]" (rect 0 0 55 12)(font "Arial" ))
-		(text "mul1[15..0]" (rect 165 27 211 39)(font "Arial" ))
-		(line (pt 232 32)(pt 216 32)(line_width 3))
+		(text "mul1[15..0]" (rect 157 27 203 39)(font "Arial" ))
+		(line (pt 224 32)(pt 208 32)(line_width 3))
 	)
 	(port
-		(pt 232 48)
+		(pt 224 48)
 		(output)
 		(text "mul2[15..0]" (rect 0 0 55 12)(font "Arial" ))
-		(text "mul2[15..0]" (rect 165 43 211 55)(font "Arial" ))
-		(line (pt 232 48)(pt 216 48)(line_width 3))
+		(text "mul2[15..0]" (rect 157 43 203 55)(font "Arial" ))
+		(line (pt 224 48)(pt 208 48)(line_width 3))
 	)
 	(port
-		(pt 232 64)
+		(pt 224 64)
 		(output)
 		(text "Rout[15..0]" (rect 0 0 55 12)(font "Arial" ))
-		(text "Rout[15..0]" (rect 165 59 211 71)(font "Arial" ))
-		(line (pt 232 64)(pt 216 64)(line_width 3))
+		(text "Rout[15..0]" (rect 157 59 203 71)(font "Arial" ))
+		(line (pt 224 64)(pt 208 64)(line_width 3))
 	)
 	(port
-		(pt 232 80)
+		(pt 224 80)
 		(output)
 		(text "jump" (rect 0 0 23 12)(font "Arial" ))
-		(text "jump" (rect 192 75 211 87)(font "Arial" ))
-		(line (pt 232 80)(pt 216 80))
+		(text "jump" (rect 184 75 203 87)(font "Arial" ))
+		(line (pt 224 80)(pt 208 80))
 	)
 	(port
-		(pt 232 96)
-		(output)
-		(text "carry" (rect 0 0 25 12)(font "Arial" ))
-		(text "carry" (rect 190 91 211 103)(font "Arial" ))
-		(line (pt 232 96)(pt 216 96))
-	)
-	(port
-		(pt 232 112)
-		(output)
-		(text "jumpflags[7..0]" (rect 0 0 74 12)(font "Arial" ))
-		(text "jumpflags[7..0]" (rect 149 107 211 119)(font "Arial" ))
-		(line (pt 232 112)(pt 216 112)(line_width 3))
-	)
-	(port
-		(pt 232 128)
+		(pt 224 96)
 		(output)
 		(text "memaddr[10..0]" (rect 0 0 77 12)(font "Arial" ))
-		(text "memaddr[10..0]" (rect 146 123 211 135)(font "Arial" ))
-		(line (pt 232 128)(pt 216 128)(line_width 3))
+		(text "memaddr[10..0]" (rect 138 91 203 103)(font "Arial" ))
+		(line (pt 224 96)(pt 208 96)(line_width 3))
 	)
 	(drawing
-		(rectangle (rect 16 16 216 192))
+		(rectangle (rect 16 16 208 160))
 	)
 )
 (connector
@@ -482,47 +397,17 @@ https://fpgasoftware.intel.com/eula.
 	(bus)
 )
 (connector
-	(pt 752 432)
-	(pt 752 488)
+	(pt 768 280)
+	(pt 792 280)
 	(bus)
 )
 (connector
-	(pt 544 504)
-	(pt 536 504)
-	(bus)
+	(pt 768 296)
+	(pt 792 296)
 )
 (connector
-	(pt 544 520)
-	(pt 528 520)
-	(bus)
-)
-(connector
-	(pt 528 440)
-	(pt 528 520)
-	(bus)
-)
-(connector
-	(pt 536 448)
-	(pt 536 504)
-	(bus)
-)
-(connector
-	(pt 752 432)
-	(pt 536 432)
-	(bus)
-)
-(connector
-	(pt 544 488)
-	(pt 520 488)
-)
-(connector
-	(pt 528 440)
-	(pt 784 440)
-	(bus)
-)
-(connector
-	(pt 536 328)
-	(pt 536 432)
+	(pt 768 312)
+	(pt 792 312)
 	(bus)
 )
 (connector
@@ -531,78 +416,88 @@ https://fpgasoftware.intel.com/eula.
 	(bus)
 )
 (connector
-	(pt 744 488)
-	(pt 752 488)
+	(pt 776 264)
+	(pt 776 408)
 	(bus)
 )
 (connector
-	(pt 752 488)
-	(pt 768 488)
+	(pt 784 248)
+	(pt 784 416)
 	(bus)
 )
 (connector
-	(pt 784 264)
-	(pt 784 440)
+	(pt 536 328)
+	(pt 536 400)
 	(bus)
 )
 (connector
-	(pt 536 448)
-	(pt 792 448)
-	(bus)
-)
-(connector
-	(pt 792 248)
-	(pt 792 448)
-	(bus)
-)
-(connector
-	(pt 776 280)
-	(pt 800 280)
-	(bus)
-)
-(connector
-	(pt 776 296)
-	(pt 800 296)
-)
-(connector
-	(pt 776 312)
-	(pt 800 312)
-)
-(connector
-	(pt 776 328)
-	(pt 800 328)
-	(bus)
-)
-(connector
-	(pt 776 248)
-	(pt 792 248)
-	(bus)
-)
-(connector
-	(pt 792 248)
-	(pt 800 248)
+	(pt 768 264)
+	(pt 776 264)
 	(bus)
 )
 (connector
 	(pt 776 264)
-	(pt 784 264)
+	(pt 792 264)
 	(bus)
 )
 (connector
-	(pt 784 264)
-	(pt 800 264)
+	(pt 768 248)
+	(pt 784 248)
 	(bus)
 )
 (connector
-	(pt 776 344)
-	(pt 800 344)
+	(pt 784 248)
+	(pt 792 248)
 	(bus)
 )
 (connector
-	(pt 544 376)
-	(pt 528 376)
+	(pt 536 400)
+	(pt 760 400)
 	(bus)
 )
-(junction (pt 752 488))
-(junction (pt 784 264))
-(junction (pt 792 248))
+(connector
+	(pt 760 456)
+	(pt 752 456)
+	(bus)
+)
+(connector
+	(pt 760 400)
+	(pt 760 456)
+	(bus)
+)
+(connector
+	(pt 784 416)
+	(pt 544 416)
+	(bus)
+)
+(connector
+	(pt 544 416)
+	(pt 544 472)
+	(bus)
+)
+(connector
+	(pt 552 472)
+	(pt 544 472)
+	(bus)
+)
+(connector
+	(pt 776 408)
+	(pt 536 408)
+	(bus)
+)
+(connector
+	(pt 536 408)
+	(pt 536 488)
+	(bus)
+)
+(connector
+	(pt 552 488)
+	(pt 536 488)
+	(bus)
+)
+(connector
+	(pt 552 456)
+	(pt 528 456)
+)
+(junction (pt 776 264))
+(junction (pt 784 248))
diff --git a/ALU_top.bsf b/ALU_top.bsf
index 63e7bf5..dac5b6c 100644
--- a/ALU_top.bsf
+++ b/ALU_top.bsf
@@ -76,16 +76,9 @@ https://fpgasoftware.intel.com/eula.
 	(port
 		(pt 0 144)
 		(input)
-		(text "memdatain[15..0]" (rect 0 0 107 19)(font "Intel Clear" (font_size 8)))
-		(text "memdatain[15..0]" (rect 21 139 128 158)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 144)(pt 16 144)(line_width 3))
-	)
-	(port
-		(pt 0 160)
-		(input)
 		(text "CLK" (rect 0 0 23 19)(font "Intel Clear" (font_size 8)))
-		(text "CLK" (rect 21 155 44 174)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 160)(pt 16 160))
+		(text "CLK" (rect 21 139 44 158)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 144)(pt 16 144))
 	)
 	(port
 		(pt 256 32)
@@ -118,30 +111,9 @@ https://fpgasoftware.intel.com/eula.
 	(port
 		(pt 256 96)
 		(output)
-		(text "CARRY" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
-		(text "CARRY" (rect 194 91 235 110)(font "Intel Clear" (font_size 8)))
-		(line (pt 256 96)(pt 240 96))
-	)
-	(port
-		(pt 256 112)
-		(output)
-		(text "jumpflags[7..0]" (rect 0 0 89 19)(font "Intel Clear" (font_size 8)))
-		(text "jumpflags[7..0]" (rect 146 107 235 126)(font "Intel Clear" (font_size 8)))
-		(line (pt 256 112)(pt 240 112)(line_width 3))
-	)
-	(port
-		(pt 256 128)
-		(output)
 		(text "memaddr[10..0]" (rect 0 0 97 19)(font "Intel Clear" (font_size 8)))
-		(text "memaddr[10..0]" (rect 138 123 235 142)(font "Intel Clear" (font_size 8)))
-		(line (pt 256 128)(pt 240 128)(line_width 3))
-	)
-	(port
-		(pt 256 144)
-		(output)
-		(text "MUL_res[31..0]" (rect 0 0 90 19)(font "Intel Clear" (font_size 8)))
-		(text "MUL_res[31..0]" (rect 145 139 235 158)(font "Intel Clear" (font_size 8)))
-		(line (pt 256 144)(pt 240 144)(line_width 3))
+		(text "memaddr[10..0]" (rect 138 91 235 110)(font "Intel Clear" (font_size 8)))
+		(line (pt 256 96)(pt 240 96)(line_width 3))
 	)
 	(drawing
 		(rectangle (rect 16 16 240 176))
diff --git a/CPUProject.bdf b/CPUProject.bdf
index e24c8aa..9cdc317 100644
--- a/CPUProject.bdf
+++ b/CPUProject.bdf
@@ -57,71 +57,7 @@ https://fpgasoftware.intel.com/eula.
 )
 (pin
 	(output)
-	(rect 1232 528 1408 544)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "ALU_carry" (rect 90 0 143 12)(font "Arial" ))
-	(pt 0 8)
-	(drawing
-		(line (pt 0 8)(pt 52 8))
-		(line (pt 52 4)(pt 78 4))
-		(line (pt 52 12)(pt 78 12))
-		(line (pt 52 12)(pt 52 4))
-		(line (pt 78 4)(pt 82 8))
-		(line (pt 82 8)(pt 78 12))
-		(line (pt 78 12)(pt 82 8))
-	)
-)
-(pin
-	(output)
-	(rect 1232 560 1408 576)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "Rs1[15..0]" (rect 90 0 141 12)(font "Arial" ))
-	(pt 0 8)
-	(drawing
-		(line (pt 0 8)(pt 52 8))
-		(line (pt 52 4)(pt 78 4))
-		(line (pt 52 12)(pt 78 12))
-		(line (pt 52 12)(pt 52 4))
-		(line (pt 78 4)(pt 82 8))
-		(line (pt 82 8)(pt 78 12))
-		(line (pt 78 12)(pt 82 8))
-	)
-)
-(pin
-	(output)
-	(rect 1232 576 1408 592)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "Rs2[15..0]" (rect 90 0 141 12)(font "Arial" ))
-	(pt 0 8)
-	(drawing
-		(line (pt 0 8)(pt 52 8))
-		(line (pt 52 4)(pt 78 4))
-		(line (pt 52 12)(pt 78 12))
-		(line (pt 52 12)(pt 52 4))
-		(line (pt 78 4)(pt 82 8))
-		(line (pt 82 8)(pt 78 12))
-		(line (pt 78 12)(pt 82 8))
-	)
-)
-(pin
-	(output)
-	(rect 1232 544 1408 560)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "Rd[15..0]" (rect 90 0 136 12)(font "Arial" ))
-	(pt 0 8)
-	(drawing
-		(line (pt 0 8)(pt 52 8))
-		(line (pt 52 4)(pt 78 4))
-		(line (pt 52 12)(pt 78 12))
-		(line (pt 52 12)(pt 52 4))
-		(line (pt 78 4)(pt 82 8))
-		(line (pt 82 8)(pt 78 12))
-		(line (pt 78 12)(pt 82 8))
-	)
-)
-(pin
-	(output)
-	(rect 1232 592 1408 608)
+	(rect 1192 624 1368 640)
 	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
 	(text "instr[15..0]" (rect 90 0 143 12)(font "Arial" ))
 	(pt 0 8)
@@ -137,71 +73,7 @@ https://fpgasoftware.intel.com/eula.
 )
 (pin
 	(output)
-	(rect 1232 608 1408 624)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "FETCH" (rect 90 0 126 12)(font "Arial" ))
-	(pt 0 8)
-	(drawing
-		(line (pt 0 8)(pt 52 8))
-		(line (pt 52 4)(pt 78 4))
-		(line (pt 52 12)(pt 78 12))
-		(line (pt 52 12)(pt 52 4))
-		(line (pt 78 4)(pt 82 8))
-		(line (pt 82 8)(pt 78 12))
-		(line (pt 78 12)(pt 82 8))
-	)
-)
-(pin
-	(output)
-	(rect 1232 624 1408 640)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "EXEC1" (rect 90 0 124 12)(font "Arial" ))
-	(pt 0 8)
-	(drawing
-		(line (pt 0 8)(pt 52 8))
-		(line (pt 52 4)(pt 78 4))
-		(line (pt 52 12)(pt 78 12))
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-	(output)
-	(rect 1432 176 1608 192)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "s5" (rect 90 0 101 12)(font "Arial" ))
-	(pt 0 8)
-	(drawing
-		(line (pt 0 8)(pt 52 8))
-		(line (pt 52 4)(pt 78 4))
-		(line (pt 52 12)(pt 78 12))
-		(line (pt 52 12)(pt 52 4))
-		(line (pt 78 4)(pt 82 8))
-		(line (pt 82 8)(pt 78 12))
-		(line (pt 78 12)(pt 82 8))
-	)
-)
-(pin
-	(output)
-	(rect 1512 288 1688 304)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "RAMd_out[15..0]" (rect 90 0 172 12)(font "Arial" ))
-	(pt 0 8)
-	(drawing
-		(line (pt 0 8)(pt 52 8))
-		(line (pt 52 4)(pt 78 4))
-		(line (pt 52 12)(pt 78 12))
-		(line (pt 52 12)(pt 52 4))
-		(line (pt 78 4)(pt 82 8))
-		(line (pt 82 8)(pt 78 12))
-		(line (pt 78 12)(pt 82 8))
-	)
-)
-(pin
-	(output)
-	(rect 1512 256 1688 272)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "RAMdAddr[10..0]" (rect 90 0 173 12)(font "Arial" ))
-	(pt 0 8)
-	(drawing
-		(line (pt 0 8)(pt 52 8))
-		(line (pt 52 4)(pt 78 4))
-		(line (pt 52 12)(pt 78 12))
-		(line (pt 52 12)(pt 52 4))
-		(line (pt 78 4)(pt 82 8))
-		(line (pt 82 8)(pt 78 12))
-		(line (pt 78 12)(pt 82 8))
-	)
-)
 (symbol
 	(rect 632 144 816 352)
 	(text "mux_8x16" (rect 5 0 55 12)(font "Arial" ))
@@ -1346,7 +674,7 @@ https://fpgasoftware.intel.com/eula.
 	)
 )
 (symbol
-	(rect 896 584 1080 728)
+	(rect 928 512 1112 656)
 	(text "LIFOstack" (rect 5 0 56 12)(font "Arial" ))
 	(text "STACK" (rect 8 128 43 140)(font "Arial" ))
 	(port
@@ -1391,20 +719,6 @@ https://fpgasoftware.intel.com/eula.
 		(text "Dout[15..0]" (rect 117 27 163 39)(font "Arial" ))
 		(line (pt 184 32)(pt 168 32)(line_width 3))
 	)
-	(port
-		(pt 184 48)
-		(output)
-		(text "empty" (rect 0 0 31 12)(font "Arial" ))
-		(text "empty" (rect 137 43 163 55)(font "Arial" ))
-		(line (pt 184 48)(pt 168 48))
-	)
-	(port
-		(pt 184 64)
-		(output)
-		(text "full" (rect 0 0 15 12)(font "Arial" ))
-		(text "full" (rect 151 59 163 71)(font "Arial" ))
-		(line (pt 184 64)(pt 168 64))
-	)
 	(drawing
 		(rectangle (rect 16 16 168 128))
 	)
@@ -1465,16 +779,9 @@ https://fpgasoftware.intel.com/eula.
 	(port
 		(pt 0 144)
 		(input)
-		(text "memdatain[15..0]" (rect 0 0 107 19)(font "Intel Clear" (font_size 8)))
-		(text "memdatain[15..0]" (rect 21 139 128 158)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 144)(pt 16 144)(line_width 3))
-	)
-	(port
-		(pt 0 160)
-		(input)
 		(text "CLK" (rect 0 0 23 19)(font "Intel Clear" (font_size 8)))
-		(text "CLK" (rect 21 155 44 174)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 160)(pt 16 160))
+		(text "CLK" (rect 21 139 44 158)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 144)(pt 16 144))
 	)
 	(port
 		(pt 256 32)
@@ -1507,30 +814,9 @@ https://fpgasoftware.intel.com/eula.
 	(port
 		(pt 256 96)
 		(output)
-		(text "CARRY" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
-		(text "CARRY" (rect 194 91 235 110)(font "Intel Clear" (font_size 8)))
-		(line (pt 256 96)(pt 240 96))
-	)
-	(port
-		(pt 256 112)
-		(output)
-		(text "jumpflags[7..0]" (rect 0 0 89 19)(font "Intel Clear" (font_size 8)))
-		(text "jumpflags[7..0]" (rect 146 107 235 126)(font "Intel Clear" (font_size 8)))
-		(line (pt 256 112)(pt 240 112)(line_width 3))
-	)
-	(port
-		(pt 256 128)
-		(output)
 		(text "memaddr[10..0]" (rect 0 0 97 19)(font "Intel Clear" (font_size 8)))
-		(text "memaddr[10..0]" (rect 138 123 235 142)(font "Intel Clear" (font_size 8)))
-		(line (pt 256 128)(pt 240 128)(line_width 3))
-	)
-	(port
-		(pt 256 144)
-		(output)
-		(text "MUL_res[31..0]" (rect 0 0 90 19)(font "Intel Clear" (font_size 8)))
-		(text "MUL_res[31..0]" (rect 145 139 235 158)(font "Intel Clear" (font_size 8)))
-		(line (pt 256 144)(pt 240 144)(line_width 3))
+		(text "memaddr[10..0]" (rect 138 91 235 110)(font "Intel Clear" (font_size 8)))
+		(line (pt 256 96)(pt 240 96)(line_width 3))
 	)
 	(drawing
 		(rectangle (rect 16 16 240 176))
@@ -2137,16 +1423,6 @@ https://fpgasoftware.intel.com/eula.
 	(pt 136 416)
 	(bus)
 )
-(connector
-	(pt 136 416)
-	(pt 136 448)
-	(bus)
-)
-(connector
-	(pt 136 448)
-	(pt 136 792)
-	(bus)
-)
 (connector
 	(pt 136 224)
 	(pt 136 256)
@@ -2381,11 +1657,6 @@ https://fpgasoftware.intel.com/eula.
 	(pt 592 592)
 	(bus)
 )
-(connector
-	(pt 136 792)
-	(pt 1416 792)
-	(bus)
-)
 (connector
 	(text "Rs1[15..0]" (rect 818 160 865 177)(font "Intel Clear" ))
 	(pt 816 176)
@@ -2434,113 +1705,6 @@ https://fpgasoftware.intel.com/eula.
 	(pt 576 304)
 	(bus)
 )
-(connector
-	(pt 1416 496)
-	(pt 1224 496)
-	(bus)
-)
-(connector
-	(pt 1232 520)
-	(pt 1224 520)
-	(bus)
-)
-(connector
-	(pt 1224 520)
-	(pt 1224 496)
-	(bus)
-)
-(connector
-	(text "EXEC1" (rect 1186 616 1217 633)(font "Intel Clear" ))
-	(pt 1176 632)
-	(pt 1232 632)
-)
-(connector
-	(text "EXEC2" (rect 1186 632 1217 649)(font "Intel Clear" ))
-	(pt 1176 648)
-	(pt 1232 648)
-)
-(connector
-	(text "CARRY" (rect 1186 520 1221 537)(font "Intel Clear" ))
-	(pt 1176 536)
-	(pt 1232 536)
-)
-(connector
-	(text "Rd[15..0]" (rect 1186 536 1228 553)(font "Intel Clear" ))
-	(pt 1176 552)
-	(pt 1232 552)
-	(bus)
-)
-(connector
-	(text "Rs1[15..0]" (rect 1186 552 1233 569)(font "Intel Clear" ))
-	(pt 1176 568)
-	(pt 1232 568)
-	(bus)
-)
-(connector
-	(text "Rs2[15..0]" (rect 1186 568 1233 585)(font "Intel Clear" ))
-	(pt 1176 584)
-	(pt 1232 584)
-	(bus)
-)
-(connector
-	(text "instr[15..0]" (rect 1184 584 1233 601)(font "Intel Clear" ))
-	(pt 1176 600)
-	(pt 1232 600)
-	(bus)
-)
-(connector
-	(text "FETCH" (rect 1186 600 1217 617)(font "Intel Clear" ))
-	(pt 1176 616)
-	(pt 1232 616)
-)
-(connector
-	(text "PC[15..0]" (rect 1186 648 1229 665)(font "Intel Clear" ))
-	(pt 1232 664)
-	(pt 1176 664)
-	(bus)
-)
-(connector
-	(text "R1[15..0]" (rect 1186 664 1228 681)(font "Intel Clear" ))
-	(pt 1232 680)
-	(pt 1176 680)
-	(bus)
-)
-(connector
-	(text "R2[15..0]" (rect 1186 680 1228 697)(font "Intel Clear" ))
-	(pt 1232 696)
-	(pt 1176 696)
-	(bus)
-)
-(connector
-	(text "R3[15..0]" (rect 1186 696 1228 713)(font "Intel Clear" ))
-	(pt 1232 712)
-	(pt 1176 712)
-	(bus)
-)
-(connector
-	(text "R4[15..0]" (rect 1186 712 1228 729)(font "Intel Clear" ))
-	(pt 1232 728)
-	(pt 1176 728)
-	(bus)
-)
-(connector
-	(text "R5[15..0]" (rect 1186 728 1228 745)(font "Intel Clear" ))
-	(pt 1232 744)
-	(pt 1176 744)
-	(bus)
-)
-(connector
-	(text "R6[15..0]" (rect 1186 744 1228 761)(font "Intel Clear" ))
-	(pt 1232 760)
-	(pt 1176 760)
-	(bus)
-)
-(connector
-	(text "R7[15..0]" (rect 1186 760 1228 777)(font "Intel Clear" ))
-	(pt 1232 776)
-	(pt 1176 776)
-	(bus)
-)
 (connector
 	(text "CLK" (rect 354 712 374 729)(font "Intel Clear" ))
 	(pt 344 728)
@@ -2556,38 +1720,6 @@ https://fpgasoftware.intel.com/eula.
 	(pt 560 120)
 	(pt 600 120)
 )
-(connector
-	(text "ALU_out[15..0]" (rect 1448 264 1518 281)(font "Intel Clear" ))
-	(pt 1440 280)
-	(pt 1512 280)
-	(bus)
-)
-(connector
-	(text "stack_out[15..0]" (rect 1450 296 1525 313)(font "Intel Clear" ))
-	(pt 1512 312)
-	(pt 1440 312)
-	(bus)
-)
-(connector
-	(text "COND" (rect 1450 312 1479 329)(font "Intel Clear" ))
-	(pt 1512 328)
-	(pt 1440 328)
-)
-(connector
-	(pt 1416 320)
-	(pt 1368 320)
-	(bus)
-)
-(connector
-	(pt 1416 320)
-	(pt 1416 496)
-	(bus)
-)
-(connector
-	(pt 1416 496)
-	(pt 1416 792)
-	(bus)
-)
 (connector
 	(text "s4" (rect 1296 373 1313 383)(font "Intel Clear" )(vertical))
 	(pt 1312 360)
@@ -2598,12 +1730,6 @@ https://fpgasoftware.intel.com/eula.
 	(pt 344 712)
 	(pt 400 712)
 )
-(connector
-	(text "MUL_res[31..0]" (rect 1450 328 1521 345)(font "Intel Clear" ))
-	(pt 1512 344)
-	(pt 1440 344)
-	(bus)
-)
 (connector
 	(pt 464 192)
 	(pt 464 400)
@@ -2660,29 +1786,11 @@ https://fpgasoftware.intel.com/eula.
 	(pt 272 88)
 	(pt 304 88)
 )
-(connector
-	(text "jumpflags[7..0]" (rect 1448 344 1518 361)(font "Intel Clear" ))
-	(pt 1512 360)
-	(pt 1440 360)
-	(bus)
-)
 (connector
 	(pt 1256 336)
 	(pt 1248 336)
 	(bus)
 )
-(connector
-	(text "mul1[15..0]" (rect 1448 360 1502 377)(font "Intel Clear" ))
-	(pt 1512 376)
-	(pt 1440 376)
-	(bus)
-)
-(connector
-	(text "mul2[15..0]" (rect 1448 376 1502 393)(font "Intel Clear" ))
-	(pt 1512 392)
-	(pt 1440 392)
-	(bus)
-)
 (connector
 	(pt 856 592)
 	(pt 856 400)
@@ -2747,17 +1855,6 @@ https://fpgasoftware.intel.com/eula.
 	(pt 1248 384)
 	(bus)
 )
-(connector
-	(text "jumpflags[7..0]" (rect 1184 416 1254 433)(font "Intel Clear" ))
-	(pt 1184 432)
-	(pt 1232 432)
-	(bus)
-)
-(connector
-	(text "CARRY" (rect 1186 400 1221 417)(font "Intel Clear" ))
-	(pt 1184 416)
-	(pt 1232 416)
-)
 (connector
 	(text "COND" (rect 1194 384 1223 401)(font "Intel Clear" ))
 	(pt 1184 400)
@@ -2775,23 +1872,6 @@ https://fpgasoftware.intel.com/eula.
 	(pt 1232 352)
 	(bus)
 )
-(connector
-	(text "MUL_res[31..0]" (rect 1184 448 1255 465)(font "Intel Clear" ))
-	(pt 1184 464)
-	(pt 1232 464)
-	(bus)
-)
-(connector
-	(text "CLK" (rect 882 464 902 481)(font "Intel Clear" ))
-	(pt 928 480)
-	(pt 872 480)
-)
-(connector
-	(text "RAMd_out[15..0]" (rect 870 448 950 465)(font "Intel Clear" ))
-	(pt 928 464)
-	(pt 872 464)
-	(bus)
-)
 (connector
 	(text "instr[10..0]" (rect 904 40 953 57)(font "Intel Clear" ))
 	(pt 872 56)
@@ -2810,12 +1890,6 @@ https://fpgasoftware.intel.com/eula.
 	(pt 872 88)
 	(bus)
 )
-(connector
-	(text "memaddr[10..0]" (rect 1192 432 1267 449)(font "Intel Clear" ))
-	(pt 1184 448)
-	(pt 1232 448)
-	(bus)
-)
 (connector
 	(pt 1080 72)
 	(pt 1088 72)
@@ -2836,12 +1910,6 @@ https://fpgasoftware.intel.com/eula.
 	(pt 872 152)
 	(bus)
 )
-(connector
-	(text "memaddr[10..0]" (rect 1448 392 1523 409)(font "Intel Clear" ))
-	(pt 1512 408)
-	(pt 1440 408)
-	(bus)
-)
 (connector
 	(text "s5" (rect 1008 117 1025 127)(font "Intel Clear" )(vertical))
 	(pt 1024 112)
@@ -2858,83 +1926,6 @@ https://fpgasoftware.intel.com/eula.
 	(pt 1160 304)
 	(bus)
 )
-(connector
-	(text "Rs1[15..0]" (rect 850 600 897 617)(font "Intel Clear" ))
-	(pt 840 616)
-	(pt 896 616)
-	(bus)
-)
-(connector
-	(text "CLK" (rect 850 616 870 633)(font "Intel Clear" ))
-	(pt 840 632)
-	(pt 896 632)
-)
-(connector
-	(text "stack_en" (rect 850 632 892 649)(font "Intel Clear" ))
-	(pt 840 648)
-	(pt 896 648)
-)
-(connector
-	(text "stack_rst" (rect 850 648 892 665)(font "Intel Clear" ))
-	(pt 840 664)
-	(pt 896 664)
-)
-(connector
-	(text "stack_rw" (rect 850 664 892 681)(font "Intel Clear" ))
-	(pt 840 680)
-	(pt 896 680)
-)
-(connector
-	(text "stack_out[15..0]" (rect 1082 600 1157 617)(font "Intel Clear" ))
-	(pt 1080 616)
-	(pt 1144 616)
-	(bus)
-)
-(connector
-	(text "stack_empty" (rect 1082 616 1143 633)(font "Intel Clear" ))
-	(pt 1080 632)
-	(pt 1144 632)
-)
-(connector
-	(text "stack_full" (rect 1082 632 1129 649)(font "Intel Clear" ))
-	(pt 1080 648)
-	(pt 1144 648)
-)
-(connector
-	(text "stack_empty" (rect 1450 408 1511 425)(font "Intel Clear" ))
-	(pt 1512 424)
-	(pt 1440 424)
-)
-(connector
-	(text "stack_full" (rect 1450 424 1497 441)(font "Intel Clear" ))
-	(pt 1512 440)
-	(pt 1440 440)
-)
-(connector
-	(pt 1512 296)
-	(pt 1416 296)
-	(bus)
-)
-(connector
-	(pt 1416 296)
-	(pt 1416 256)
-	(bus)
-)
-(connector
-	(pt 1416 256)
-	(pt 1160 256)
-	(bus)
-)
-(connector
-	(pt 1160 192)
-	(pt 1160 256)
-	(bus)
-)
-(connector
-	(pt 1160 256)
-	(pt 1160 304)
-	(bus)
-)
 (connector
 	(pt 872 -152)
 	(pt 872 24)
@@ -3034,11 +2025,6 @@ https://fpgasoftware.intel.com/eula.
 	(pt 1432 24)
 	(bus)
 )
-(connector
-	(text "RAMd_wren" (rect 1394 40 1453 57)(font "Intel Clear" ))
-	(pt 1384 56)
-	(pt 1448 56)
-)
 (connector
 	(text "RAMd_en" (rect 1394 56 1441 73)(font "Intel Clear" ))
 	(pt 1384 72)
@@ -3084,36 +2070,143 @@ https://fpgasoftware.intel.com/eula.
 	(pt 1384 184)
 	(pt 1432 184)
 )
-(connector
-	(pt 1168 152)
-	(pt 1168 248)
-	(bus)
-)
 (connector
 	(pt 872 152)
 	(pt 1088 152)
 	(bus)
 )
 (connector
-	(pt 1088 152)
-	(pt 1168 152)
+	(text "RAMd_wren" (rect 1386 40 1445 57)(font "Intel Clear" ))
+	(pt 1384 56)
+	(pt 1432 56)
+)
+(connector
+	(text "memaddr[10..0]" (rect 1192 400 1267 417)(font "Intel Clear" ))
+	(pt 1184 416)
+	(pt 1232 416)
 	(bus)
 )
 (connector
-	(pt 1168 248)
-	(pt 1440 248)
+	(text "CLK" (rect 882 448 902 465)(font "Intel Clear" ))
+	(pt 928 464)
+	(pt 872 464)
+)
+(connector
+	(pt 1160 192)
+	(pt 1160 304)
 	(bus)
 )
 (connector
-	(pt 1440 248)
-	(pt 1440 264)
+	(pt 136 776)
+	(pt 1376 776)
 	(bus)
 )
 (connector
-	(pt 1440 264)
-	(pt 1512 264)
+	(pt 1368 320)
+	(pt 1376 320)
 	(bus)
 )
+(connector
+	(pt 1376 320)
+	(pt 1376 776)
+	(bus)
+)
+(connector
+	(pt 136 416)
+	(pt 136 448)
+	(bus)
+)
+(connector
+	(pt 136 448)
+	(pt 136 776)
+	(bus)
+)
+(connector
+	(text "PC[15..0]" (rect 1146 632 1189 649)(font "Intel Clear" ))
+	(pt 1192 648)
+	(pt 1136 648)
+	(bus)
+)
+(connector
+	(text "R1[15..0]" (rect 1146 648 1188 665)(font "Intel Clear" ))
+	(pt 1192 664)
+	(pt 1136 664)
+	(bus)
+)
+(connector
+	(text "R2[15..0]" (rect 1146 664 1188 681)(font "Intel Clear" ))
+	(pt 1192 680)
+	(pt 1136 680)
+	(bus)
+)
+(connector
+	(text "R3[15..0]" (rect 1146 680 1188 697)(font "Intel Clear" ))
+	(pt 1192 696)
+	(pt 1136 696)
+	(bus)
+)
+(connector
+	(text "R4[15..0]" (rect 1146 696 1188 713)(font "Intel Clear" ))
+	(pt 1192 712)
+	(pt 1136 712)
+	(bus)
+)
+(connector
+	(text "R5[15..0]" (rect 1146 712 1188 729)(font "Intel Clear" ))
+	(pt 1192 728)
+	(pt 1136 728)
+	(bus)
+)
+(connector
+	(text "R6[15..0]" (rect 1146 728 1188 745)(font "Intel Clear" ))
+	(pt 1192 744)
+	(pt 1136 744)
+	(bus)
+)
+(connector
+	(text "R7[15..0]" (rect 1146 744 1188 761)(font "Intel Clear" ))
+	(pt 1192 760)
+	(pt 1136 760)
+	(bus)
+)
+(connector
+	(text "instr[15..0]" (rect 1144 616 1193 633)(font "Intel Clear" ))
+	(pt 1136 632)
+	(pt 1192 632)
+	(bus)
+)
+(connector
+	(text "stack_out[15..0]" (rect 1114 528 1189 545)(font "Intel Clear" ))
+	(pt 1112 544)
+	(pt 1168 544)
+	(bus)
+)
+(connector
+	(text "Rs1[15..0]" (rect 874 528 921 545)(font "Intel Clear" ))
+	(pt 928 544)
+	(pt 872 544)
+	(bus)
+)
+(connector
+	(text "CLK" (rect 874 544 894 561)(font "Intel Clear" ))
+	(pt 928 560)
+	(pt 872 560)
+)
+(connector
+	(text "stack_en" (rect 874 560 916 577)(font "Intel Clear" ))
+	(pt 928 576)
+	(pt 872 576)
+)
+(connector
+	(text "stack_rst" (rect 874 576 916 593)(font "Intel Clear" ))
+	(pt 928 592)
+	(pt 872 592)
+)
+(connector
+	(text "stack_rw" (rect 874 592 916 609)(font "Intel Clear" ))
+	(pt 928 608)
+	(pt 872 608)
+)
 (junction (pt 856 192))
 (junction (pt 136 320))
 (junction (pt 136 352))
@@ -3138,8 +2231,5 @@ https://fpgasoftware.intel.com/eula.
 (junction (pt 544 480))
 (junction (pt 560 496))
 (junction (pt 576 512))
-(junction (pt 1416 496))
 (junction (pt 536 192))
 (junction (pt 872 24))
-(junction (pt 1160 256))
-(junction (pt 1088 152))
diff --git a/CPUProject.qsf b/CPUProject.qsf
index f6d4eb8..0e69956 100644
--- a/CPUProject.qsf
+++ b/CPUProject.qsf
@@ -62,6 +62,7 @@ set_global_assignment -name POWER_USE_PVA ON
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name SDC_FILE CPUProject.sdc
 set_global_assignment -name VERILOG_FILE LIFOstack.v
 set_global_assignment -name VERILOG_FILE alu.v
 set_global_assignment -name MIF_FILE LUTSquares.mif
@@ -84,4 +85,5 @@ set_global_assignment -name VERILOG_FILE mux_3x16.v
 set_global_assignment -name VERILOG_FILE ADD_1.v
 set_global_assignment -name VERILOG_FILE SM_pipelined.v
 set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
+set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/CPUProject.qws b/CPUProject.qws
new file mode 100644
index 0000000000000000000000000000000000000000..d4099da20b1bda1e89b73250ae070e8477b55336
GIT binary patch
literal 673
zcmbV|F-rqM5QX36EUvV)NMRuogoGp@YA1?TDMVr|xyzl#L@%5X3$fKdVq@*k5W&{}
zqQ-BQz2=Yz?($}LX5P-c+1-Z9Ro6rVU2CRO-6~h1G2WC|q7+g9>e|<lPCx<Uf_MVI
zrC38{p3~Evwup4JLw=ihS4|MJQ*Ish5HzXWCU4m`y9)-eGwi0TnCkwoo+c`I#>|1f
z%t+Cr6h3iT@`x<>=^YN$z`A<q$<V*5J>785nCS|y&zbWZF-i)fYR<CLuVo$bG-V8<
zBpUxla?*Iv(6L53)A@foS>X_@IZ@NaQk}Yr)D>o%FbyJke1PPUo3k)^)w!aQKr(!(
sR5BU%XoHHm|E)`EF8DiZQSH$RKHgtlA(u51J<#s0bZPr-zz=Hr0mb@o)c^nh

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HcmV?d00001

diff --git a/CPUProject.sdc b/CPUProject.sdc
new file mode 100644
index 0000000..c0fad97
--- /dev/null
+++ b/CPUProject.sdc
@@ -0,0 +1,4 @@
+#This file must have the same name as your project
+
+#Make input CLK a clock and set frequency to 100MHz (10ns period)
+create_clock -name {CLK} -period 10.0 [get_ports {CLK}]
diff --git a/CPUProject.sdc.bak b/CPUProject.sdc.bak
new file mode 100644
index 0000000..fdc6662
--- /dev/null
+++ b/CPUProject.sdc.bak
@@ -0,0 +1,4 @@
+#This file must have the same name as your project
+
+#Make input CLK a clock and set frequency to 250MHz (4ns period)
+create_clock -name {CLK} -period 4.0 [get_ports {CLK}]
diff --git a/LIFOstack.bsf b/LIFOstack.bsf
index 967974d..1633c8a 100644
--- a/LIFOstack.bsf
+++ b/LIFOstack.bsf
@@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 2018  Intel Corporation. All rights reserved.
+Copyright (C) 2019  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
 (including device programming or simulation files), and any 
 associated documentation or information are expressly subject 
@@ -16,7 +16,8 @@ the Intel FPGA IP License Agreement, or other applicable license
 agreement, including, without limitation, that your use is for
 the sole purpose of programming logic devices manufactured by
 Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details.
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
 */
 (header "symbol" (version "1.1"))
 (symbol
@@ -65,20 +66,6 @@ refer to the applicable agreement for further details.
 		(text "Dout[15..0]" (rect 121 27 163 39)(font "Arial" ))
 		(line (pt 184 32)(pt 168 32)(line_width 3))
 	)
-	(port
-		(pt 184 48)
-		(output)
-		(text "empty" (rect 0 0 25 12)(font "Arial" ))
-		(text "empty" (rect 138 43 163 55)(font "Arial" ))
-		(line (pt 184 48)(pt 168 48)(line_width 1))
-	)
-	(port
-		(pt 184 64)
-		(output)
-		(text "full" (rect 0 0 10 12)(font "Arial" ))
-		(text "full" (rect 153 59 163 71)(font "Arial" ))
-		(line (pt 184 64)(pt 168 64)(line_width 1))
-	)
 	(drawing
 		(rectangle (rect 16 16 168 128)(line_width 1))
 	)
diff --git a/LIFOstack.v b/LIFOstack.v
index b476bc4..a7669ad 100644
--- a/LIFOstack.v
+++ b/LIFOstack.v
@@ -1,4 +1,4 @@
-module LIFOstack (Din, clk, en, rst, rw, Dout, empty, full);
+module LIFOstack (Din, clk, en, rst, rw, Dout);
 
 input [15:0] Din; // Data being fed to stack
 input clk; // clock signal input
@@ -7,8 +7,8 @@ input rst; // reset pin to clear and reinitialise stack (active high)
 input rw; // 0: read, 1: write
 
 output reg [15:0] Dout; // Data being pulled from stack
-output reg empty; // goes high to indicate SP is at 0
-output reg full; // goes high to indicate SP is at (slots)
+reg empty; // goes high to indicate SP is at 0
+reg full; // goes high to indicate SP is at (slots)
 
 reg [5:0] SP; // Points to slot to save next value to
 integer i;
diff --git a/alu.bsf b/alu.bsf
index 169c1a7..010863f 100644
--- a/alu.bsf
+++ b/alu.bsf
@@ -21,9 +21,9 @@ https://fpgasoftware.intel.com/eula.
 */
 (header "symbol" (version "1.1"))
 (symbol
-	(rect 16 16 248 224)
+	(rect 16 16 240 192)
 	(text "alu" (rect 5 0 15 12)(font "Arial" ))
-	(text "inst" (rect 8 192 20 204)(font "Arial" ))
+	(text "inst" (rect 8 160 20 172)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
@@ -81,62 +81,41 @@ https://fpgasoftware.intel.com/eula.
 		(line (pt 0 144)(pt 16 144)(line_width 3))
 	)
 	(port
-		(pt 0 160)
-		(input)
-		(text "memdatain[15..0]" (rect 0 0 67 12)(font "Arial" ))
-		(text "memdatain[15..0]" (rect 21 155 88 167)(font "Arial" ))
-		(line (pt 0 160)(pt 16 160)(line_width 3))
-	)
-	(port
-		(pt 232 32)
+		(pt 224 32)
 		(output)
 		(text "mul1[15..0]" (rect 0 0 41 12)(font "Arial" ))
-		(text "mul1[15..0]" (rect 170 27 211 39)(font "Arial" ))
-		(line (pt 232 32)(pt 216 32)(line_width 3))
+		(text "mul1[15..0]" (rect 162 27 203 39)(font "Arial" ))
+		(line (pt 224 32)(pt 208 32)(line_width 3))
 	)
 	(port
-		(pt 232 48)
+		(pt 224 48)
 		(output)
 		(text "mul2[15..0]" (rect 0 0 42 12)(font "Arial" ))
-		(text "mul2[15..0]" (rect 169 43 211 55)(font "Arial" ))
-		(line (pt 232 48)(pt 216 48)(line_width 3))
+		(text "mul2[15..0]" (rect 161 43 203 55)(font "Arial" ))
+		(line (pt 224 48)(pt 208 48)(line_width 3))
 	)
 	(port
-		(pt 232 64)
+		(pt 224 64)
 		(output)
 		(text "Rout[15..0]" (rect 0 0 43 12)(font "Arial" ))
-		(text "Rout[15..0]" (rect 168 59 211 71)(font "Arial" ))
-		(line (pt 232 64)(pt 216 64)(line_width 3))
+		(text "Rout[15..0]" (rect 160 59 203 71)(font "Arial" ))
+		(line (pt 224 64)(pt 208 64)(line_width 3))
 	)
 	(port
-		(pt 232 80)
+		(pt 224 80)
 		(output)
 		(text "jump" (rect 0 0 18 12)(font "Arial" ))
-		(text "jump" (rect 193 75 211 87)(font "Arial" ))
-		(line (pt 232 80)(pt 216 80)(line_width 1))
+		(text "jump" (rect 185 75 203 87)(font "Arial" ))
+		(line (pt 224 80)(pt 208 80)(line_width 1))
 	)
 	(port
-		(pt 232 96)
-		(output)
-		(text "carry" (rect 0 0 22 12)(font "Arial" ))
-		(text "carry" (rect 189 91 211 103)(font "Arial" ))
-		(line (pt 232 96)(pt 216 96)(line_width 1))
-	)
-	(port
-		(pt 232 112)
-		(output)
-		(text "jumpflags[7..0]" (rect 0 0 57 12)(font "Arial" ))
-		(text "jumpflags[7..0]" (rect 154 107 211 119)(font "Arial" ))
-		(line (pt 232 112)(pt 216 112)(line_width 3))
-	)
-	(port
-		(pt 232 128)
+		(pt 224 96)
 		(output)
 		(text "memaddr[10..0]" (rect 0 0 62 12)(font "Arial" ))
-		(text "memaddr[10..0]" (rect 149 123 211 135)(font "Arial" ))
-		(line (pt 232 128)(pt 216 128)(line_width 3))
+		(text "memaddr[10..0]" (rect 141 91 203 103)(font "Arial" ))
+		(line (pt 224 96)(pt 208 96)(line_width 3))
 	)
 	(drawing
-		(rectangle (rect 16 16 216 192)(line_width 1))
+		(rectangle (rect 16 16 208 160)(line_width 1))
 	)
 )

From aff07036e0896d8b0155fe5e8775b5542bfb9bc7 Mon Sep 17 00:00:00 2001
From: Benjamin <bramhorst27@gmail.com>
Date: Sat, 13 Jun 2020 01:41:24 +0100
Subject: [PATCH 3/4] Fixed multiplier bug

---
 abs.bdf                | 769 -----------------------------------------
 abs.bsf                |  44 ---
 min.bsf => max_min.bsf |  36 +-
 max_min.v              |  11 +
 max_min.v.bak          |  11 +
 min.v                  |   7 -
 min.v.bak              |  12 -
 mul16.bdf              | 354 +++++++++----------
 mul8.bdf               | 299 ++++++++--------
 mul8.bsf               |  18 +-
 10 files changed, 364 insertions(+), 1197 deletions(-)
 delete mode 100644 abs.bdf
 delete mode 100644 abs.bsf
 rename min.bsf => max_min.bsf (66%)
 create mode 100644 max_min.v
 create mode 100644 max_min.v.bak
 delete mode 100644 min.v
 delete mode 100644 min.v.bak

diff --git a/abs.bdf b/abs.bdf
deleted file mode 100644
index ab619c9..0000000
--- a/abs.bdf
+++ /dev/null
@@ -1,769 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2019  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and any partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-(header "graphic" (version "1.4"))
-(pin
-	(input)
-	(rect 64 168 232 184)
-	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
-	(text "N[7..0]" (rect 5 0 40 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 84 12)(pt 109 12))
-		(line (pt 84 4)(pt 109 4))
-		(line (pt 113 8)(pt 168 8))
-		(line (pt 84 12)(pt 84 4))
-		(line (pt 109 4)(pt 113 8))
-		(line (pt 109 12)(pt 113 8))
-	)
-	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
-)
-(pin
-	(output)
-	(rect 1152 224 1328 240)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "ABS[7..0]" (rect 90 0 137 12)(font "Arial" ))
-	(pt 0 8)
-	(drawing
-		(line (pt 0 8)(pt 52 8))
-		(line (pt 52 4)(pt 78 4))
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-		(line (pt 52 12)(pt 52 4))
-		(line (pt 78 4)(pt 82 8))
-		(line (pt 82 8)(pt 78 12))
-		(line (pt 78 12)(pt 82 8))
-	)
-)
-(symbol
-	(rect 408 160 472 208)
-	(text "XOR" (rect 1 0 21 10)(font "Arial" (font_size 6)))
-	(text "C2" (rect 3 37 15 54)(font "Intel Clear" ))
-	(port
-		(pt 0 16)
-		(input)
-		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
-		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
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-		(line (pt 0 32)(pt 11 32))
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-		(pt 64 24)
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-		(input)
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-	(drawing
-		(line (pt 14 13)(pt 25 13))
-		(line (pt 14 36)(pt 25 36))
-		(arc (pt 7 29)(pt 7 19)(rect -14 8 19 41))
-		(arc (pt 49 24)(pt 25 13)(rect -6 13 57 76))
-		(arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36))
-		(arc (pt 8 36)(pt 8 12)(rect -21 7 14 42))
-	)
-)
-(symbol
-	(rect 120 288 152 304)
-	(text "VCC" (rect 7 0 27 10)(font "Arial" (font_size 6)))
-	(text "inst" (rect 3 5 20 17)(font "Arial" )(invisible))
-	(port
-		(pt 16 16)
-		(output)
-		(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
-		(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
-		(line (pt 16 16)(pt 16 8))
-	)
-	(drawing
-		(line (pt 8 8)(pt 24 8))
-	)
-)
-(symbol
-	(rect 168 280 200 312)
-	(text "GND" (rect 8 16 29 26)(font "Arial" (font_size 6)))
-	(text "inst5" (rect 3 21 25 38)(font "Intel Clear" )(invisible))
-	(port
-		(pt 16 0)
-		(output)
-		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
-		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
-		(line (pt 16 8)(pt 16 0))
-	)
-	(drawing
-		(line (pt 8 8)(pt 16 16))
-		(line (pt 16 16)(pt 24 8))
-		(line (pt 8 8)(pt 24 8))
-	)
-)
-(symbol
-	(rect 968 136 1128 304)
-	(text "LPM_ADD_SUB" (rect 37 0 149 16)(font "Arial" (font_size 10)))
-	(text "FA_ABS" (rect 3 156 41 173)(font "Intel Clear" ))
-	(port
-		(pt 0 144)
-		(input)
-		(text "aclr" (rect 20 130 41 144)(font "Arial" (font_size 8)))
-		(text "aclr" (rect 20 130 41 144)(font "Arial" (font_size 8)))
-		(line (pt 0 144)(pt 15 144))
-		(unused)
-	)
-	(port
-		(pt 0 32)
-		(input)
-		(text "add_sub" (rect 20 17 69 31)(font "Arial" (font_size 8)))
-		(text "add_sub" (rect 20 17 69 31)(font "Arial" (font_size 8)))
-		(line (pt 0 32)(pt 15 32))
-	)
-	(port
-		(pt 0 48)
-		(input)
-		(text "cin" (rect 20 34 36 48)(font "Arial" (font_size 8)))
-		(text "cin" (rect 20 34 36 48)(font "Arial" (font_size 8)))
-		(line (pt 0 48)(pt 15 48))
-		(unused)
-	)
-	(port
-		(pt 0 104)
-		(input)
-		(text "clken" (rect 20 90 49 104)(font "Arial" (font_size 8)))
-		(text "clken" (rect 20 90 49 104)(font "Arial" (font_size 8)))
-		(line (pt 0 104)(pt 56 104))
-		(unused)
-	)
-	(port
-		(pt 0 88)
-		(input)
-		(text "clock" (rect 20 74 49 88)(font "Arial" (font_size 8)))
-		(text "clock" (rect 20 74 49 88)(font "Arial" (font_size 8)))
-		(line (pt 0 88)(pt 56 88))
-		(unused)
-	)
-	(port
-		(pt 0 72)
-		(input)
-		(text "dataa[LPM_WIDTH-1..0]" (rect 20 57 153 71)(font "Arial" (font_size 8)))
-		(text "dataa[]" (rect 20 57 58 71)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 15 72)(line_width 3))
-	)
-	(port
-		(pt 0 120)
-		(input)
-		(text "datab[LPM_WIDTH-1..0]" (rect 20 105 153 119)(font "Arial" (font_size 8)))
-		(text "datab[]" (rect 20 105 58 119)(font "Arial" (font_size 8)))
-		(line (pt 0 120)(pt 15 120)(line_width 3))
-	)
-	(port
-		(pt 160 144)
-		(output)
-		(text "cout" (rect 120 129 144 143)(font "Arial" (font_size 8)))
-		(text "cout" (rect 120 129 144 143)(font "Arial" (font_size 8)))
-		(line (pt 145 144)(pt 160 144))
-		(unused)
-	)
-	(port
-		(pt 160 128)
-		(output)
-		(text "overflow" (rect 99 113 150 127)(font "Arial" (font_size 8)))
-		(text "overflow" (rect 97 113 148 127)(font "Arial" (font_size 8)))
-		(line (pt 145 128)(pt 160 128))
-		(unused)
-	)
-	(port
-		(pt 160 96)
-		(output)
-		(text "result[LPM_WIDTH-1..0]" (rect 109 81 242 95)(font "Arial" (font_size 8)))
-		(text "result[]" (rect 108 81 146 95)(font "Arial" (font_size 8)))
-		(line (pt 145 96)(pt 160 96)(line_width 3))
-	)
-	(parameter
-		"LPM_WIDTH"
-		"8"
-		"Width of I/O, any integer > 0"
-		" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64" 
-		(type "PARAMETER_UNSIGNED_DEC")	)
-	(drawing
-		(line (pt 16 48)(pt 72 48))
-		(line (pt 16 152)(pt 144 152))
-		(line (pt 16 16)(pt 144 16))
-		(line (pt 16 72)(pt 56 72)(line_width 3))
-		(line (pt 16 120)(pt 56 120)(line_width 3))
-		(line (pt 104 96)(pt 144 96)(line_width 3))
-		(line (pt 88 128)(pt 144 128))
-		(line (pt 16 32)(pt 88 32))
-		(line (pt 80 144)(pt 144 144))
-		(line (pt 16 144)(pt 72 144))
-		(line (pt 104 112)(pt 104 80))
-		(line (pt 88 128)(pt 88 120))
-		(line (pt 16 152)(pt 16 16))
-		(line (pt 144 152)(pt 144 16))
-		(line (pt 56 136)(pt 56 56))
-		(line (pt 72 64)(pt 72 48))
-		(line (pt 88 72)(pt 88 32))
-		(line (pt 80 144)(pt 80 124))
-		(line (pt 72 144)(pt 72 128))
-		(line (pt 56 56)(pt 104 80))
-		(line (pt 56 136)(pt 104 112))
-	)
-	(annotation_block (parameter)(rect 960 96 1154 134))
-)
-(symbol
-	(rect 784 120 896 208)
-	(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
-	(text "ADD1" (rect 3 77 36 91)(font "Arial" (font_size 8)))
-	(port
-		(pt 0 64)
-		(input)
-		(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
-		(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
-		(line (pt 0 64)(pt 44 64)(line_width 3))
-	)
-	(port
-		(pt 56 88)
-		(input)
-		(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
-		(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
-		(line (pt 56 88)(pt 56 72))
-	)
-	(port
-		(pt 0 32)
-		(input)
-		(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
-		(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
-		(line (pt 0 32)(pt 44 32)(line_width 3))
-	)
-	(port
-		(pt 112 48)
-		(output)
-		(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
-		(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
-		(line (pt 68 48)(pt 112 48)(line_width 3))
-	)
-	(parameter
-		"WIDTH"
-		"8"
-		"Width of I/O, any integer > 0"
-		" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64" 
-		(type "PARAMETER_UNSIGNED_DEC")	)
-	(drawing
-		(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
-		(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
-		(line (pt 68 64)(pt 68 32))
-		(line (pt 44 80)(pt 44 16))
-		(line (pt 44 16)(pt 68 32))
-		(line (pt 44 80)(pt 68 64))
-	)
-	(annotation_block (parameter)(rect 720 80 902 118))
-)
-(connector
-	(pt 232 176)
-	(pt 312 176)
-	(bus)
-)
-(connector
-	(text "N[0]" (rect 362 32 382 49)(font "Intel Clear" ))
-	(pt 384 48)
-	(pt 408 48)
-)
-(connector
-	(text "N[7]" (rect 362 56 382 73)(font "Intel Clear" ))
-	(pt 384 64)
-	(pt 408 64)
-)
-(connector
-	(text "N[1]" (rect 368 96 388 113)(font "Intel Clear" ))
-	(pt 390 112)
-	(pt 408 112)
-)
-(connector
-	(text "N[7]" (rect 368 112 388 129)(font "Intel Clear" ))
-	(pt 390 128)
-	(pt 408 128)
-)
-(connector
-	(text "N[7]" (rect 368 176 388 193)(font "Intel Clear" ))
-	(pt 390 192)
-	(pt 408 192)
-)
-(connector
-	(text "N[7]" (rect 368 240 388 257)(font "Intel Clear" ))
-	(pt 390 256)
-	(pt 408 256)
-)
-(connector
-	(text "N[2]" (rect 368 160 388 177)(font "Intel Clear" ))
-	(pt 390 176)
-	(pt 408 176)
-)
-(connector
-	(text "N[3]" (rect 368 224 388 241)(font "Intel Clear" ))
-	(pt 390 240)
-	(pt 408 240)
-)
-(connector
-	(text "N[4]" (rect 368 288 388 305)(font "Intel Clear" ))
-	(pt 390 304)
-	(pt 408 304)
-)
-(connector
-	(text "N[7]" (rect 368 304 388 321)(font "Intel Clear" ))
-	(pt 390 320)
-	(pt 408 320)
-)
-(connector
-	(text "N[5]" (rect 368 352 388 369)(font "Intel Clear" ))
-	(pt 390 368)
-	(pt 408 368)
-)
-(connector
-	(text "N[7]" (rect 368 368 388 385)(font "Intel Clear" ))
-	(pt 390 384)
-	(pt 408 384)
-)
-(connector
-	(text "N[7]" (rect 368 432 388 449)(font "Intel Clear" ))
-	(pt 390 448)
-	(pt 408 448)
-)
-(connector
-	(text "N[6]" (rect 368 416 388 433)(font "Intel Clear" ))
-	(pt 390 432)
-	(pt 408 432)
-)
-(connector
-	(pt 512 24)
-	(pt 512 56)
-	(bus)
-)
-(connector
-	(pt 512 56)
-	(pt 512 120)
-	(bus)
-)
-(connector
-	(pt 512 120)
-	(pt 512 184)
-	(bus)
-)
-(connector
-	(pt 512 184)
-	(pt 512 248)
-	(bus)
-)
-(connector
-	(pt 512 312)
-	(pt 512 376)
-	(bus)
-)
-(connector
-	(text "T[0]" (rect 482 40 500 57)(font "Intel Clear" ))
-	(pt 472 56)
-	(pt 512 56)
-)
-(connector
-	(text "T[1]" (rect 482 104 500 121)(font "Intel Clear" ))
-	(pt 472 120)
-	(pt 512 120)
-)
-(connector
-	(text "T[2]" (rect 482 168 500 185)(font "Intel Clear" ))
-	(pt 472 184)
-	(pt 512 184)
-)
-(connector
-	(text "T[3]" (rect 482 232 500 249)(font "Intel Clear" ))
-	(pt 472 248)
-	(pt 512 248)
-)
-(connector
-	(text "T[4]" (rect 482 296 500 313)(font "Intel Clear" ))
-	(pt 472 312)
-	(pt 512 312)
-)
-(connector
-	(text "T[5]" (rect 482 360 500 377)(font "Intel Clear" ))
-	(pt 472 376)
-	(pt 512 376)
-)
-(connector
-	(text "T[6]" (rect 482 424 500 441)(font "Intel Clear" ))
-	(pt 472 440)
-	(pt 512 440)
-)
-(connector
-	(pt 512 376)
-	(pt 512 440)
-	(bus)
-)
-(connector
-	(text "N[7]" (rect 368 496 388 513)(font "Intel Clear" ))
-	(pt 390 512)
-	(pt 408 512)
-)
-(connector
-	(text "N[7]" (rect 368 480 388 497)(font "Intel Clear" ))
-	(pt 390 496)
-	(pt 408 496)
-)
-(connector
-	(pt 512 440)
-	(pt 512 504)
-	(bus)
-)
-(connector
-	(pt 512 504)
-	(pt 512 520)
-	(bus)
-)
-(connector
-	(text "T[7]" (rect 482 488 500 505)(font "Intel Clear" ))
-	(pt 472 504)
-	(pt 512 504)
-)
-(connector
-	(pt 1128 232)
-	(pt 1152 232)
-	(bus)
-)
-(connector
-	(text "1" (rect 120 315 137 320)(font "Intel Clear" )(vertical))
-	(pt 136 304)
-	(pt 136 320)
-)
-(connector
-	(text "0" (rect 168 273 185 278)(font "Intel Clear" )(vertical))
-	(pt 184 256)
-	(pt 184 280)
-)
-(connector
-	(text "N[7]" (rect 824 205 841 225)(font "Intel Clear" )(vertical))
-	(pt 840 208)
-	(pt 840 232)
-)
-(connector
-	(text "0,0,0,0,0,0,0,0" (rect 682 136 745 153)(font "Intel Clear" ))
-	(pt 784 152)
-	(pt 672 152)
-	(bus)
-)
-(connector
-	(text "0,0,0,0,0,0,0,1" (rect 682 168 745 185)(font "Intel Clear" ))
-	(pt 672 184)
-	(pt 784 184)
-	(bus)
-)
-(connector
-	(pt 896 168)
-	(pt 912 168)
-	(bus)
-)
-(connector
-	(pt 912 168)
-	(pt 912 208)
-	(bus)
-)
-(connector
-	(pt 912 208)
-	(pt 968 208)
-	(bus)
-)
-(connector
-	(text "T[7..0]" (rect 522 256 551 273)(font "Intel Clear" ))
-	(pt 856 272)
-	(pt 512 272)
-	(bus)
-)
-(connector
-	(pt 856 272)
-	(pt 856 256)
-	(bus)
-)
-(connector
-	(pt 512 248)
-	(pt 512 272)
-	(bus)
-)
-(connector
-	(pt 512 272)
-	(pt 512 312)
-	(bus)
-)
-(connector
-	(pt 856 256)
-	(pt 968 256)
-	(bus)
-)
-(connector
-	(text "1" (rect 954 152 959 169)(font "Intel Clear" ))
-	(pt 968 168)
-	(pt 944 168)
-)
-(junction (pt 512 56))
-(junction (pt 512 120))
-(junction (pt 512 184))
-(junction (pt 512 248))
-(junction (pt 512 312))
-(junction (pt 512 376))
-(junction (pt 512 440))
-(junction (pt 512 272))
-(junction (pt 512 504))
diff --git a/abs.bsf b/abs.bsf
deleted file mode 100644
index f6d0608..0000000
--- a/abs.bsf
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2019  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and any partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-(header "symbol" (version "1.2"))
-(symbol
-	(rect 16 16 168 112)
-	(text "abs" (rect 5 0 26 19)(font "Intel Clear" (font_size 8)))
-	(text "inst" (rect 8 75 24 92)(font "Intel Clear" ))
-	(port
-		(pt 0 32)
-		(input)
-		(text "N[7..0]" (rect 0 0 40 19)(font "Intel Clear" (font_size 8)))
-		(text "N[7..0]" (rect 21 27 61 46)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 32)(pt 16 32)(line_width 3))
-	)
-	(port
-		(pt 152 32)
-		(output)
-		(text "ABS[7..0]" (rect 0 0 55 19)(font "Intel Clear" (font_size 8)))
-		(text "ABS[7..0]" (rect 76 27 131 46)(font "Intel Clear" (font_size 8)))
-		(line (pt 152 32)(pt 136 32)(line_width 3))
-	)
-	(drawing
-		(rectangle (rect 16 16 136 80))
-	)
-)
diff --git a/min.bsf b/max_min.bsf
similarity index 66%
rename from min.bsf
rename to max_min.bsf
index 5a7c022..bd160c7 100644
--- a/min.bsf
+++ b/max_min.bsf
@@ -21,38 +21,38 @@ https://fpgasoftware.intel.com/eula.
 */
 (header "symbol" (version "1.1"))
 (symbol
-	(rect 16 16 176 128)
-	(text "min" (rect 5 0 19 12)(font "Arial" ))
-	(text "inst" (rect 8 96 20 108)(font "Arial" ))
+	(rect 16 16 200 96)
+	(text "max_min" (rect 5 0 42 12)(font "Arial" ))
+	(text "inst" (rect 8 64 20 76)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "sign" (rect 0 0 15 12)(font "Arial" ))
-		(text "sign" (rect 21 27 36 39)(font "Arial" ))
-		(line (pt 0 32)(pt 16 32)(line_width 1))
+		(text "a[7..0]" (rect 0 0 24 12)(font "Arial" ))
+		(text "a[7..0]" (rect 21 27 45 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "a[7..0]" (rect 0 0 24 12)(font "Arial" ))
-		(text "a[7..0]" (rect 21 43 45 55)(font "Arial" ))
+		(text "b[7..0]" (rect 0 0 24 12)(font "Arial" ))
+		(text "b[7..0]" (rect 21 43 45 55)(font "Arial" ))
 		(line (pt 0 48)(pt 16 48)(line_width 3))
 	)
 	(port
-		(pt 0 64)
-		(input)
-		(text "b[7..0]" (rect 0 0 24 12)(font "Arial" ))
-		(text "b[7..0]" (rect 21 59 45 71)(font "Arial" ))
-		(line (pt 0 64)(pt 16 64)(line_width 3))
+		(pt 184 32)
+		(output)
+		(text "maximum[7..0]" (rect 0 0 60 12)(font "Arial" ))
+		(text "maximum[7..0]" (rect 103 27 163 39)(font "Arial" ))
+		(line (pt 184 32)(pt 168 32)(line_width 3))
 	)
 	(port
-		(pt 160 32)
+		(pt 184 48)
 		(output)
-		(text "num[7..0]" (rect 0 0 37 12)(font "Arial" ))
-		(text "num[7..0]" (rect 102 27 139 39)(font "Arial" ))
-		(line (pt 160 32)(pt 144 32)(line_width 3))
+		(text "minimum[7..0]" (rect 0 0 56 12)(font "Arial" ))
+		(text "minimum[7..0]" (rect 107 43 163 55)(font "Arial" ))
+		(line (pt 184 48)(pt 168 48)(line_width 3))
 	)
 	(drawing
-		(rectangle (rect 16 16 144 96)(line_width 1))
+		(rectangle (rect 16 16 168 64)(line_width 1))
 	)
 )
diff --git a/max_min.v b/max_min.v
new file mode 100644
index 0000000..8ea1773
--- /dev/null
+++ b/max_min.v
@@ -0,0 +1,11 @@
+module max_min(a, b, maximum, minimum);
+
+input unsigned [7:0] a;
+input unsigned [7:0] b;
+output unsigned [7:0] maximum;
+output unsigned [7:0] minimum;
+
+assign minimum = (a<b) ? a:b;
+assign maximum = (a>b) ? a:b;
+
+endmodule
\ No newline at end of file
diff --git a/max_min.v.bak b/max_min.v.bak
new file mode 100644
index 0000000..ec205cc
--- /dev/null
+++ b/max_min.v.bak
@@ -0,0 +1,11 @@
+module min_max(a, b, minimum, maximum);
+
+input unsigned [7..0] a;
+input unsigned [7..0] b;
+output unsigned [7..0] minimum;
+output unsigned [7..0] maximum;
+
+assign minimum = (a<b) ? a:b;
+assign maximum = (a>b) ? a:b;
+
+endmodule
\ No newline at end of file
diff --git a/min.v b/min.v
deleted file mode 100644
index 1ca5b39..0000000
--- a/min.v
+++ /dev/null
@@ -1,7 +0,0 @@
-module min(sign, a, b, num);
-	input sign;
-	input [7:0] a;
-	input [7:0] b;
-	output [7:0] num;
-	assign num = sign ? a[7:0]:b[7:0];
-endmodule
diff --git a/min.v.bak b/min.v.bak
deleted file mode 100644
index c07952b..0000000
--- a/min.v.bak
+++ /dev/null
@@ -1,12 +0,0 @@
-module MIN(
-	input sign,
-	input a[7..0],
-	input b[7..0],
-	output [7..0] num;
-);
-
-assign num = sign ? a[7..0]:b[7..0]
-
-
-
-endmodule
diff --git a/mul16.bdf b/mul16.bdf
index 024ecc3..0ba7f7e 100644
--- a/mul16.bdf
+++ b/mul16.bdf
@@ -145,7 +145,7 @@ https://fpgasoftware.intel.com/eula.
 		(pt 160 144)
 		(output)
 		(text "cout" (rect 120 129 144 143)(font "Arial" (font_size 8)))
-		(text "cout" (rect 120 129 140 143)(font "Arial" (font_size 8)))
+		(text "cout" (rect 120 129 144 143)(font "Arial" (font_size 8)))
 		(line (pt 145 144)(pt 160 144))
 		(unused)
 	)
@@ -153,7 +153,7 @@ https://fpgasoftware.intel.com/eula.
 		(pt 160 128)
 		(output)
 		(text "overflow" (rect 99 113 150 127)(font "Arial" (font_size 8)))
-		(text "overflow" (rect 97 113 140 127)(font "Arial" (font_size 8)))
+		(text "overflow" (rect 97 113 148 127)(font "Arial" (font_size 8)))
 		(line (pt 145 128)(pt 160 128))
 		(unused)
 	)
@@ -161,7 +161,7 @@ https://fpgasoftware.intel.com/eula.
 		(pt 160 96)
 		(output)
 		(text "result[LPM_WIDTH-1..0]" (rect 109 81 242 95)(font "Arial" (font_size 8)))
-		(text "result[]" (rect 108 81 140 95)(font "Arial" (font_size 8)))
+		(text "result[]" (rect 108 81 146 95)(font "Arial" (font_size 8)))
 		(line (pt 145 96)(pt 160 96)(line_width 3))
 	)
 	(parameter
@@ -286,7 +286,7 @@ https://fpgasoftware.intel.com/eula.
 		(pt 160 144)
 		(output)
 		(text "cout" (rect 120 129 144 143)(font "Arial" (font_size 8)))
-		(text "cout" (rect 120 129 140 143)(font "Arial" (font_size 8)))
+		(text "cout" (rect 120 129 144 143)(font "Arial" (font_size 8)))
 		(line (pt 145 144)(pt 160 144))
 		(unused)
 	)
@@ -294,7 +294,7 @@ https://fpgasoftware.intel.com/eula.
 		(pt 160 128)
 		(output)
 		(text "overflow" (rect 99 113 150 127)(font "Arial" (font_size 8)))
-		(text "overflow" (rect 97 113 140 127)(font "Arial" (font_size 8)))
+		(text "overflow" (rect 97 113 148 127)(font "Arial" (font_size 8)))
 		(line (pt 145 128)(pt 160 128))
 		(unused)
 	)
@@ -302,7 +302,7 @@ https://fpgasoftware.intel.com/eula.
 		(pt 160 96)
 		(output)
 		(text "result[LPM_WIDTH-1..0]" (rect 109 81 242 95)(font "Arial" (font_size 8)))
-		(text "result[]" (rect 108 81 140 95)(font "Arial" (font_size 8)))
+		(text "result[]" (rect 108 81 146 95)(font "Arial" (font_size 8)))
 		(line (pt 145 96)(pt 160 96)(line_width 3))
 	)
 	(parameter
@@ -427,7 +427,7 @@ https://fpgasoftware.intel.com/eula.
 		(pt 160 144)
 		(output)
 		(text "cout" (rect 120 129 144 143)(font "Arial" (font_size 8)))
-		(text "cout" (rect 120 129 140 143)(font "Arial" (font_size 8)))
+		(text "cout" (rect 120 129 144 143)(font "Arial" (font_size 8)))
 		(line (pt 145 144)(pt 160 144))
 		(unused)
 	)
@@ -435,7 +435,7 @@ https://fpgasoftware.intel.com/eula.
 		(pt 160 128)
 		(output)
 		(text "overflow" (rect 99 113 150 127)(font "Arial" (font_size 8)))
-		(text "overflow" (rect 97 113 140 127)(font "Arial" (font_size 8)))
+		(text "overflow" (rect 97 113 148 127)(font "Arial" (font_size 8)))
 		(line (pt 145 128)(pt 160 128))
 		(unused)
 	)
@@ -443,7 +443,7 @@ https://fpgasoftware.intel.com/eula.
 		(pt 160 96)
 		(output)
 		(text "result[LPM_WIDTH-1..0]" (rect 109 81 242 95)(font "Arial" (font_size 8)))
-		(text "result[]" (rect 108 81 140 95)(font "Arial" (font_size 8)))
+		(text "result[]" (rect 108 81 146 95)(font "Arial" (font_size 8)))
 		(line (pt 145 96)(pt 160 96)(line_width 3))
 	)
 	(parameter
@@ -507,150 +507,6 @@ https://fpgasoftware.intel.com/eula.
 	)
 	(annotation_block (parameter)(rect 1728 48 2038 181))
 )
-(symbol
-	(rect 648 56 816 152)
-	(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
-	(text "MUL1" (rect 8 75 36 92)(font "Intel Clear" ))
-	(port
-		(pt 0 32)
-		(input)
-		(text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
-		(text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 32)(pt 16 32))
-	)
-	(port
-		(pt 0 48)
-		(input)
-		(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
-		(text "A[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 48)(pt 16 48)(line_width 3))
-	)
-	(port
-		(pt 0 64)
-		(input)
-		(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
-		(text "B[7..0]" (rect 21 59 59 78)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 64)(pt 16 64)(line_width 3))
-	)
-	(port
-		(pt 168 32)
-		(output)
-		(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
-		(text "PROD[15..0]" (rect 73 27 147 46)(font "Intel Clear" (font_size 8)))
-		(line (pt 168 32)(pt 152 32)(line_width 3))
-	)
-	(drawing
-		(rectangle (rect 16 16 152 80))
-	)
-)
-(symbol
-	(rect 648 176 816 272)
-	(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
-	(text "MUL2" (rect 8 75 36 92)(font "Intel Clear" ))
-	(port
-		(pt 0 32)
-		(input)
-		(text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
-		(text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 32)(pt 16 32))
-	)
-	(port
-		(pt 0 48)
-		(input)
-		(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
-		(text "A[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 48)(pt 16 48)(line_width 3))
-	)
-	(port
-		(pt 0 64)
-		(input)
-		(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
-		(text "B[7..0]" (rect 21 59 59 78)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 64)(pt 16 64)(line_width 3))
-	)
-	(port
-		(pt 168 32)
-		(output)
-		(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
-		(text "PROD[15..0]" (rect 73 27 147 46)(font "Intel Clear" (font_size 8)))
-		(line (pt 168 32)(pt 152 32)(line_width 3))
-	)
-	(drawing
-		(rectangle (rect 16 16 152 80))
-	)
-)
-(symbol
-	(rect 648 288 816 384)
-	(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
-	(text "MUL3" (rect 8 75 36 92)(font "Intel Clear" ))
-	(port
-		(pt 0 32)
-		(input)
-		(text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
-		(text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 32)(pt 16 32))
-	)
-	(port
-		(pt 0 48)
-		(input)
-		(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
-		(text "A[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 48)(pt 16 48)(line_width 3))
-	)
-	(port
-		(pt 0 64)
-		(input)
-		(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
-		(text "B[7..0]" (rect 21 59 59 78)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 64)(pt 16 64)(line_width 3))
-	)
-	(port
-		(pt 168 32)
-		(output)
-		(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
-		(text "PROD[15..0]" (rect 73 27 147 46)(font "Intel Clear" (font_size 8)))
-		(line (pt 168 32)(pt 152 32)(line_width 3))
-	)
-	(drawing
-		(rectangle (rect 16 16 152 80))
-	)
-)
-(symbol
-	(rect 648 392 816 488)
-	(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
-	(text "MUL4" (rect 8 75 36 92)(font "Intel Clear" ))
-	(port
-		(pt 0 32)
-		(input)
-		(text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
-		(text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 32)(pt 16 32))
-	)
-	(port
-		(pt 0 48)
-		(input)
-		(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
-		(text "A[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 48)(pt 16 48)(line_width 3))
-	)
-	(port
-		(pt 0 64)
-		(input)
-		(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
-		(text "B[7..0]" (rect 21 59 59 78)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 64)(pt 16 64)(line_width 3))
-	)
-	(port
-		(pt 168 32)
-		(output)
-		(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
-		(text "PROD[15..0]" (rect 73 27 147 46)(font "Intel Clear" (font_size 8)))
-		(line (pt 168 32)(pt 152 32)(line_width 3))
-	)
-	(drawing
-		(rectangle (rect 16 16 152 80))
-	)
-)
 (symbol
 	(rect 168 160 200 192)
 	(text "GND" (rect 8 16 29 26)(font "Arial" (font_size 6)))
@@ -668,6 +524,150 @@ https://fpgasoftware.intel.com/eula.
 		(line (pt 8 8)(pt 24 8))
 	)
 )
+(symbol
+	(rect 648 56 848 152)
+	(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
+	(text "MUL1" (rect 8 75 36 92)(font "Intel Clear" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
+		(text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "NUM1[7..0]" (rect 0 0 68 19)(font "Intel Clear" (font_size 8)))
+		(text "NUM1[7..0]" (rect 21 43 89 62)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "NUM2[7..0]" (rect 0 0 68 19)(font "Intel Clear" (font_size 8)))
+		(text "NUM2[7..0]" (rect 21 59 89 78)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 200 32)
+		(output)
+		(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
+		(text "PROD[15..0]" (rect 105 27 179 46)(font "Intel Clear" (font_size 8)))
+		(line (pt 200 32)(pt 184 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 184 80))
+	)
+)
+(symbol
+	(rect 648 176 848 272)
+	(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
+	(text "MUL2" (rect 8 75 36 92)(font "Intel Clear" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
+		(text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "NUM1[7..0]" (rect 0 0 68 19)(font "Intel Clear" (font_size 8)))
+		(text "NUM1[7..0]" (rect 21 43 89 62)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "NUM2[7..0]" (rect 0 0 68 19)(font "Intel Clear" (font_size 8)))
+		(text "NUM2[7..0]" (rect 21 59 89 78)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 200 32)
+		(output)
+		(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
+		(text "PROD[15..0]" (rect 105 27 179 46)(font "Intel Clear" (font_size 8)))
+		(line (pt 200 32)(pt 184 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 184 80))
+	)
+)
+(symbol
+	(rect 648 288 848 384)
+	(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
+	(text "MUL3" (rect 8 75 36 92)(font "Intel Clear" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
+		(text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "NUM1[7..0]" (rect 0 0 68 19)(font "Intel Clear" (font_size 8)))
+		(text "NUM1[7..0]" (rect 21 43 89 62)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "NUM2[7..0]" (rect 0 0 68 19)(font "Intel Clear" (font_size 8)))
+		(text "NUM2[7..0]" (rect 21 59 89 78)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 200 32)
+		(output)
+		(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
+		(text "PROD[15..0]" (rect 105 27 179 46)(font "Intel Clear" (font_size 8)))
+		(line (pt 200 32)(pt 184 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 184 80))
+	)
+)
+(symbol
+	(rect 648 392 848 488)
+	(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
+	(text "MUL4" (rect 8 75 36 92)(font "Intel Clear" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
+		(text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "NUM1[7..0]" (rect 0 0 68 19)(font "Intel Clear" (font_size 8)))
+		(text "NUM1[7..0]" (rect 21 43 89 62)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "NUM2[7..0]" (rect 0 0 68 19)(font "Intel Clear" (font_size 8)))
+		(text "NUM2[7..0]" (rect 21 59 89 78)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 200 32)
+		(output)
+		(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
+		(text "PROD[15..0]" (rect 105 27 179 46)(font "Intel Clear" (font_size 8)))
+		(line (pt 200 32)(pt 184 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 184 80))
+	)
+)
 (connector
 	(text "B[15..8]" (rect 570 104 606 121)(font "Intel Clear" ))
 	(pt 648 120)
@@ -716,30 +716,6 @@ https://fpgasoftware.intel.com/eula.
 	(pt 584 456)
 	(bus)
 )
-(connector
-	(text "P1[15..0]" (rect 826 72 868 89)(font "Intel Clear" ))
-	(pt 816 88)
-	(pt 880 88)
-	(bus)
-)
-(connector
-	(text "P2[15..0]" (rect 826 192 868 209)(font "Intel Clear" ))
-	(pt 816 208)
-	(pt 880 208)
-	(bus)
-)
-(connector
-	(text "P3[15..0]" (rect 834 296 876 313)(font "Intel Clear" ))
-	(pt 816 320)
-	(pt 888 320)
-	(bus)
-)
-(connector
-	(text "P4[15..0]" (rect 826 408 868 425)(font "Intel Clear" ))
-	(pt 816 424)
-	(pt 888 424)
-	(bus)
-)
 (connector
 	(pt 520 88)
 	(pt 648 88)
@@ -865,6 +841,30 @@ https://fpgasoftware.intel.com/eula.
 	(pt 216 216)
 	(pt 520 216)
 )
+(connector
+	(text "P1[15..0]" (rect 858 72 900 89)(font "Intel Clear" ))
+	(pt 848 88)
+	(pt 912 88)
+	(bus)
+)
+(connector
+	(text "P2[15..0]" (rect 858 192 900 209)(font "Intel Clear" ))
+	(pt 848 208)
+	(pt 896 208)
+	(bus)
+)
+(connector
+	(text "P3[15..0]" (rect 858 304 900 321)(font "Intel Clear" ))
+	(pt 848 320)
+	(pt 904 320)
+	(bus)
+)
+(connector
+	(text "P4[15..0]" (rect 858 408 900 425)(font "Intel Clear" ))
+	(pt 848 424)
+	(pt 888 424)
+	(bus)
+)
 (junction (pt 520 208))
 (junction (pt 520 216))
 (junction (pt 520 320))
diff --git a/mul8.bdf b/mul8.bdf
index 08eaa18..35635f3 100644
--- a/mul8.bdf
+++ b/mul8.bdf
@@ -20,38 +20,6 @@ refer to the applicable agreement for further details, at
 https://fpgasoftware.intel.com/eula.
 */
 (header "graphic" (version "1.4"))
-(pin
-	(input)
-	(rect -416 152 -248 168)
-	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
-	(text "A[7..0]" (rect 5 0 38 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 84 12)(pt 109 12))
-		(line (pt 84 4)(pt 109 4))
-		(line (pt 113 8)(pt 168 8))
-		(line (pt 84 12)(pt 84 4))
-		(line (pt 109 4)(pt 113 8))
-		(line (pt 109 12)(pt 113 8))
-	)
-	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
-)
-(pin
-	(input)
-	(rect -424 296 -256 312)
-	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
-	(text "B[7..0]" (rect 5 0 38 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 84 12)(pt 109 12))
-		(line (pt 84 4)(pt 109 4))
-		(line (pt 113 8)(pt 168 8))
-		(line (pt 84 12)(pt 84 4))
-		(line (pt 109 4)(pt 113 8))
-		(line (pt 109 12)(pt 113 8))
-	)
-	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
-)
 (pin
 	(input)
 	(rect 320 40 488 56)
@@ -68,6 +36,38 @@ https://fpgasoftware.intel.com/eula.
 	)
 	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
 )
+(pin
+	(input)
+	(rect -752 216 -584 232)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "NUM1[7..0]" (rect 5 0 62 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect -752 232 -584 248)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "NUM2[7..0]" (rect 5 0 59 17)(font "Intel Clear" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
 (pin
 	(output)
 	(rect 1584 160 1760 176)
@@ -642,64 +642,6 @@ https://fpgasoftware.intel.com/eula.
 	)
 	(annotation_block (parameter)(rect 1128 -8 1322 30))
 )
-(symbol
-	(rect 312 216 464 312)
-	(text "abs" (rect 5 0 26 19)(font "Intel Clear" (font_size 8)))
-	(text "inst1" (rect 8 75 30 92)(font "Intel Clear" ))
-	(port
-		(pt 0 32)
-		(input)
-		(text "N[7..0]" (rect 0 0 40 19)(font "Intel Clear" (font_size 8)))
-		(text "N[7..0]" (rect 21 27 61 46)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 32)(pt 16 32)(line_width 3))
-	)
-	(port
-		(pt 152 32)
-		(output)
-		(text "ABS[7..0]" (rect 0 0 55 19)(font "Intel Clear" (font_size 8)))
-		(text "ABS[7..0]" (rect 76 27 131 46)(font "Intel Clear" (font_size 8)))
-		(line (pt 152 32)(pt 136 32)(line_width 3))
-	)
-	(drawing
-		(rectangle (rect 16 16 136 80))
-	)
-)
-(symbol
-	(rect 360 440 520 552)
-	(text "min" (rect 5 0 22 12)(font "Arial" ))
-	(text "inst4" (rect 8 96 30 113)(font "Intel Clear" ))
-	(port
-		(pt 0 32)
-		(input)
-		(text "sign" (rect 0 0 20 12)(font "Arial" ))
-		(text "sign" (rect 21 27 41 39)(font "Arial" ))
-		(line (pt 0 32)(pt 16 32))
-	)
-	(port
-		(pt 0 48)
-		(input)
-		(text "a[7..0]" (rect 0 0 31 12)(font "Arial" ))
-		(text "a[7..0]" (rect 21 43 52 55)(font "Arial" ))
-		(line (pt 0 48)(pt 16 48)(line_width 3))
-	)
-	(port
-		(pt 0 64)
-		(input)
-		(text "b[7..0]" (rect 0 0 31 12)(font "Arial" ))
-		(text "b[7..0]" (rect 21 59 52 71)(font "Arial" ))
-		(line (pt 0 64)(pt 16 64)(line_width 3))
-	)
-	(port
-		(pt 160 32)
-		(output)
-		(text "num[7..0]" (rect 0 0 47 12)(font "Arial" ))
-		(text "num[7..0]" (rect 100 27 147 39)(font "Arial" ))
-		(line (pt 160 32)(pt 144 32)(line_width 3))
-	)
-	(drawing
-		(rectangle (rect 16 16 144 96))
-	)
-)
 (symbol
 	(rect 688 -48 944 72)
 	(text "LUT" (rect 112 0 139 16)(font "Arial" (font_size 10)))
@@ -774,26 +716,52 @@ https://fpgasoftware.intel.com/eula.
 		(line (pt 0 0)(pt 0 0))
 	)
 )
+(symbol
+	(rect -544 192 -360 272)
+	(text "max_min" (rect 5 0 49 12)(font "Arial" ))
+	(text "maxmin" (rect 8 64 45 81)(font "Intel Clear" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "a[7..0]" (rect 0 0 31 12)(font "Arial" ))
+		(text "a[7..0]" (rect 21 27 52 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "b[7..0]" (rect 0 0 31 12)(font "Arial" ))
+		(text "b[7..0]" (rect 21 43 52 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 184 32)
+		(output)
+		(text "maximum[7..0]" (rect 0 0 74 12)(font "Arial" ))
+		(text "maximum[7..0]" (rect 101 27 175 39)(font "Arial" ))
+		(line (pt 184 32)(pt 168 32)(line_width 3))
+	)
+	(port
+		(pt 184 48)
+		(output)
+		(text "minimum[7..0]" (rect 0 0 70 12)(font "Arial" ))
+		(text "minimum[7..0]" (rect 104 43 174 55)(font "Arial" ))
+		(line (pt 184 48)(pt 168 48)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 168 64))
+	)
+)
 (connector
 	(text "1" (rect -94 -64 -89 -47)(font "Intel Clear" ))
 	(pt -80 -48)
 	(pt -104 -48)
 )
-(connector
-	(pt -200 160)
-	(pt -248 160)
-	(bus)
-)
 (connector
 	(pt -200 -8)
 	(pt -80 -8)
 	(bus)
 )
-(connector
-	(pt -256 304)
-	(pt -160 304)
-	(bus)
-)
 (connector
 	(pt -160 40)
 	(pt -80 40)
@@ -855,11 +823,6 @@ https://fpgasoftware.intel.com/eula.
 	(pt 1024 104)
 	(bus)
 )
-(connector
-	(pt 976 152)
-	(pt 1024 152)
-	(bus)
-)
 (connector
 	(pt 1184 128)
 	(pt 1224 128)
@@ -930,38 +893,11 @@ https://fpgasoftware.intel.com/eula.
 	(pt 728 440)
 	(bus)
 )
-(connector
-	(text "0,S[7..1]" (rect 530 -40 567 -23)(font "Intel Clear" ))
-	(pt 520 -16)
-	(pt 688 -16)
-	(bus)
-)
-(connector
-	(pt 976 16)
-	(pt 976 152)
-	(bus)
-)
-(connector
-	(pt 944 16)
-	(pt 976 16)
-	(bus)
-)
-(connector
-	(pt 944 -16)
-	(pt 992 -16)
-	(bus)
-)
 (connector
 	(pt 992 104)
 	(pt 992 -16)
 	(bus)
 )
-(connector
-	(text "0,D[7..1]" (rect 538 0 576 17)(font "Intel Clear" ))
-	(pt 528 16)
-	(pt 688 16)
-	(bus)
-)
 (connector
 	(pt 688 48)
 	(pt 488 48)
@@ -973,43 +909,84 @@ https://fpgasoftware.intel.com/eula.
 	(bus)
 )
 (connector
-	(text "DIFF[7..0]" (rect 106 392 150 409)(font "Intel Clear" ))
-	(pt 96 408)
-	(pt 152 408)
-	(bus)
-)
-(connector
-	(text "D[7..0]" (rect 474 232 504 249)(font "Intel Clear" ))
-	(pt 464 248)
-	(pt 512 248)
-	(bus)
-)
-(connector
-	(text "DIFF[7..0]" (rect 282 232 326 249)(font "Intel Clear" ))
-	(pt 312 248)
-	(pt 272 248)
-	(bus)
-)
-(connector
+	(text "B[7..0]" (rect 530 456 560 473)(font "Intel Clear" ))
 	(pt 520 472)
 	(pt 800 472)
 	(bus)
 )
 (connector
-	(text "DIFF[7]" (rect 298 456 332 473)(font "Intel Clear" ))
-	(pt 360 472)
-	(pt 288 472)
-)
-(connector
-	(text "A[7..0]" (rect 298 472 328 489)(font "Intel Clear" ))
-	(pt 360 488)
-	(pt 288 488)
+	(text "D[7..0]" (rect 106 392 136 409)(font "Intel Clear" ))
+	(pt 96 408)
+	(pt 152 408)
 	(bus)
 )
 (connector
-	(text "B[7..0]" (rect 298 488 328 505)(font "Intel Clear" ))
-	(pt 360 504)
-	(pt 288 504)
+	(pt -360 224)
+	(pt -320 224)
+	(bus)
+)
+(connector
+	(pt -320 224)
+	(pt -320 160)
+	(bus)
+)
+(connector
+	(text "A[7..0]" (rect -262 144 -232 161)(font "Intel Clear" ))
+	(pt -320 160)
+	(pt -200 160)
+	(bus)
+)
+(connector
+	(pt -360 240)
+	(pt -360 304)
+	(bus)
+)
+(connector
+	(text "B[7..0]" (rect -270 288 -240 305)(font "Intel Clear" ))
+	(pt -360 304)
+	(pt -160 304)
+	(bus)
+)
+(connector
+	(pt -544 224)
+	(pt -584 224)
+	(bus)
+)
+(connector
+	(pt -544 240)
+	(pt -584 240)
+	(bus)
+)
+(connector
+	(text "0,S[7..1]" (rect 530 -40 567 -23)(font "Intel Clear" ))
+	(pt 520 -16)
+	(pt 688 -16)
+	(bus)
+)
+(connector
+	(text "0,D[7..1]" (rect 538 0 576 17)(font "Intel Clear" ))
+	(pt 528 16)
+	(pt 688 16)
+	(bus)
+)
+(connector
+	(pt 944 -16)
+	(pt 992 -16)
+	(bus)
+)
+(connector
+	(pt 944 16)
+	(pt 976 16)
+	(bus)
+)
+(connector
+	(pt 976 16)
+	(pt 976 152)
+	(bus)
+)
+(connector
+	(pt 976 152)
+	(pt 1024 152)
 	(bus)
 )
 (junction (pt -200 160))
diff --git a/mul8.bsf b/mul8.bsf
index 8e5e353..42bdc3e 100644
--- a/mul8.bsf
+++ b/mul8.bsf
@@ -21,7 +21,7 @@ https://fpgasoftware.intel.com/eula.
 */
 (header "symbol" (version "1.2"))
 (symbol
-	(rect 16 16 184 112)
+	(rect 16 16 216 112)
 	(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
 	(text "inst" (rect 8 75 24 92)(font "Intel Clear" ))
 	(port
@@ -34,25 +34,25 @@ https://fpgasoftware.intel.com/eula.
 	(port
 		(pt 0 48)
 		(input)
-		(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
-		(text "A[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
+		(text "NUM1[7..0]" (rect 0 0 68 19)(font "Intel Clear" (font_size 8)))
+		(text "NUM1[7..0]" (rect 21 43 89 62)(font "Intel Clear" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 3))
 	)
 	(port
 		(pt 0 64)
 		(input)
-		(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
-		(text "B[7..0]" (rect 21 59 59 78)(font "Intel Clear" (font_size 8)))
+		(text "NUM2[7..0]" (rect 0 0 68 19)(font "Intel Clear" (font_size 8)))
+		(text "NUM2[7..0]" (rect 21 59 89 78)(font "Intel Clear" (font_size 8)))
 		(line (pt 0 64)(pt 16 64)(line_width 3))
 	)
 	(port
-		(pt 168 32)
+		(pt 200 32)
 		(output)
 		(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
-		(text "PROD[15..0]" (rect 73 27 147 46)(font "Intel Clear" (font_size 8)))
-		(line (pt 168 32)(pt 152 32)(line_width 3))
+		(text "PROD[15..0]" (rect 105 27 179 46)(font "Intel Clear" (font_size 8)))
+		(line (pt 200 32)(pt 184 32)(line_width 3))
 	)
 	(drawing
-		(rectangle (rect 16 16 152 80))
+		(rectangle (rect 16 16 184 80))
 	)
 )

From 5dd725f7bf5f015748a9351ec8831f3b01affd00 Mon Sep 17 00:00:00 2001
From: Kacper <kacper.neumann19@imperial.ac.uk>
Date: Sun, 14 Jun 2020 15:47:34 +0100
Subject: [PATCH 4/4] Brought up to date with Pipelined

---
 ALU_top.bdf    |  11 ++-
 ALU_top.bsf    |   7 +-
 CPUProject.bdf | 223 ++++++++++++++++++++++++-------------------------
 CPUProject.qsf |  12 +--
 CPUProject.qws | Bin 673 -> 2985 bytes
 DECODE.bsf     |   7 +-
 DECODE.v       |  48 ++++++-----
 alu.bsf        |  11 ++-
 alu.v          |  19 +++--
 mux_3x16.bsf   |  64 --------------
 mux_3x16.v     |  19 -----
 mux_3x16.v.bak |  18 ----
 12 files changed, 168 insertions(+), 271 deletions(-)
 delete mode 100644 mux_3x16.bsf
 delete mode 100644 mux_3x16.v
 delete mode 100644 mux_3x16.v.bak

diff --git a/ALU_top.bdf b/ALU_top.bdf
index 785f265..63139ce 100644
--- a/ALU_top.bdf
+++ b/ALU_top.bdf
@@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 2019  Intel Corporation. All rights reserved.
+Copyright (C) 2018  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and any partner logic 
+and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
 (including device programming or simulation files), and any 
 associated documentation or information are expressly subject 
@@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license
 agreement, including, without limitation, that your use is for
 the sole purpose of programming logic devices manufactured by
 Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
+refer to the applicable agreement for further details.
 */
 (header "graphic" (version "1.4"))
 (pin
@@ -299,8 +298,8 @@ https://fpgasoftware.intel.com/eula.
 	(port
 		(pt 0 96)
 		(input)
-		(text "opcode[5..0]" (rect 0 0 61 12)(font "Arial" ))
-		(text "opcode[5..0]" (rect 21 91 82 103)(font "Arial" ))
+		(text "instr[15..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "instr[15..0]" (rect 21 91 74 103)(font "Arial" ))
 		(line (pt 0 96)(pt 16 96)(line_width 3))
 	)
 	(port
diff --git a/ALU_top.bsf b/ALU_top.bsf
index dac5b6c..d8e24ad 100644
--- a/ALU_top.bsf
+++ b/ALU_top.bsf
@@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 2019  Intel Corporation. All rights reserved.
+Copyright (C) 2018  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and any partner logic 
+and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
 (including device programming or simulation files), and any 
 associated documentation or information are expressly subject 
@@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license
 agreement, including, without limitation, that your use is for
 the sole purpose of programming logic devices manufactured by
 Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
+refer to the applicable agreement for further details.
 */
 (header "symbol" (version "1.2"))
 (symbol
diff --git a/CPUProject.bdf b/CPUProject.bdf
index 9cdc317..763dfc9 100644
--- a/CPUProject.bdf
+++ b/CPUProject.bdf
@@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 2019  Intel Corporation. All rights reserved.
+Copyright (C) 2018  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and any partner logic 
+and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
 (including device programming or simulation files), and any 
 associated documentation or information are expressly subject 
@@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license
 agreement, including, without limitation, that your use is for
 the sole purpose of programming logic devices manufactured by
 Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
+refer to the applicable agreement for further details.
 */
 (header "graphic" (version "1.4"))
 (properties
@@ -270,7 +269,7 @@ https://fpgasoftware.intel.com/eula.
 		(pt 184 32)
 		(output)
 		(text "result[15..0]" (rect 0 0 59 12)(font "Arial" ))
-		(text "result[15..0]" (rect 114 27 163 39)(font "Arial" ))
+		(text "result[15..0]" (rect 114 27 173 39)(font "Arial" ))
 		(line (pt 184 32)(pt 168 32)(line_width 3))
 	)
 	(drawing
@@ -348,7 +347,7 @@ https://fpgasoftware.intel.com/eula.
 		(pt 184 32)
 		(output)
 		(text "result[15..0]" (rect 0 0 59 12)(font "Arial" ))
-		(text "result[15..0]" (rect 114 27 163 39)(font "Arial" ))
+		(text "result[15..0]" (rect 114 27 173 39)(font "Arial" ))
 		(line (pt 184 32)(pt 168 32)(line_width 3))
 	)
 	(drawing
@@ -426,7 +425,7 @@ https://fpgasoftware.intel.com/eula.
 		(pt 184 32)
 		(output)
 		(text "result[15..0]" (rect 0 0 59 12)(font "Arial" ))
-		(text "result[15..0]" (rect 114 27 163 39)(font "Arial" ))
+		(text "result[15..0]" (rect 114 27 173 39)(font "Arial" ))
 		(line (pt 184 32)(pt 168 32)(line_width 3))
 	)
 	(drawing
@@ -652,21 +651,21 @@ https://fpgasoftware.intel.com/eula.
 		(pt 152 32)
 		(output)
 		(text "FETCH" (rect 0 0 36 12)(font "Arial" ))
-		(text "FETCH" (rect 101 27 131 39)(font "Arial" ))
+		(text "FETCH" (rect 101 27 137 39)(font "Arial" ))
 		(line (pt 152 32)(pt 136 32))
 	)
 	(port
 		(pt 152 48)
 		(output)
 		(text "EXEC1" (rect 0 0 34 12)(font "Arial" ))
-		(text "EXEC1" (rect 103 43 131 55)(font "Arial" ))
+		(text "EXEC1" (rect 103 43 137 55)(font "Arial" ))
 		(line (pt 152 48)(pt 136 48))
 	)
 	(port
 		(pt 152 64)
 		(output)
 		(text "EXEC2" (rect 0 0 34 12)(font "Arial" ))
-		(text "EXEC2" (rect 103 59 131 71)(font "Arial" ))
+		(text "EXEC2" (rect 103 59 137 71)(font "Arial" ))
 		(line (pt 152 64)(pt 136 64))
 	)
 	(drawing
@@ -716,112 +715,13 @@ https://fpgasoftware.intel.com/eula.
 		(pt 184 32)
 		(output)
 		(text "Dout[15..0]" (rect 0 0 55 12)(font "Arial" ))
-		(text "Dout[15..0]" (rect 117 27 163 39)(font "Arial" ))
+		(text "Dout[15..0]" (rect 117 27 172 39)(font "Arial" ))
 		(line (pt 184 32)(pt 168 32)(line_width 3))
 	)
 	(drawing
 		(rectangle (rect 16 16 168 128))
 	)
 )
-(symbol
-	(rect 928 320 1184 512)
-	(text "ALU_top" (rect 5 0 56 19)(font "Intel Clear" (font_size 8)))
-	(text "ALU" (rect 8 171 28 188)(font "Intel Clear" ))
-	(port
-		(pt 0 32)
-		(input)
-		(text "ALU_en" (rect 0 0 46 19)(font "Intel Clear" (font_size 8)))
-		(text "ALU_en" (rect 21 27 67 46)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 32)(pt 16 32))
-	)
-	(port
-		(pt 0 48)
-		(input)
-		(text "Rs1[15..0]" (rect 0 0 61 19)(font "Intel Clear" (font_size 8)))
-		(text "Rs1[15..0]" (rect 21 43 82 62)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 48)(pt 16 48)(line_width 3))
-	)
-	(port
-		(pt 0 64)
-		(input)
-		(text "Rs2[15..0]" (rect 0 0 61 19)(font "Intel Clear" (font_size 8)))
-		(text "Rs2[15..0]" (rect 21 59 82 78)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 64)(pt 16 64)(line_width 3))
-	)
-	(port
-		(pt 0 80)
-		(input)
-		(text "Rd[15..0]" (rect 0 0 55 19)(font "Intel Clear" (font_size 8)))
-		(text "Rd[15..0]" (rect 21 75 76 94)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 80)(pt 16 80)(line_width 3))
-	)
-	(port
-		(pt 0 96)
-		(input)
-		(text "op[5..0]" (rect 0 0 46 19)(font "Intel Clear" (font_size 8)))
-		(text "op[5..0]" (rect 21 91 67 110)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 96)(pt 16 96)(line_width 3))
-	)
-	(port
-		(pt 0 112)
-		(input)
-		(text "EXEC2" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
-		(text "EXEC2" (rect 21 107 59 126)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 112)(pt 16 112))
-	)
-	(port
-		(pt 0 128)
-		(input)
-		(text "stack_data[15..0]" (rect 0 0 103 19)(font "Intel Clear" (font_size 8)))
-		(text "stack_data[15..0]" (rect 21 123 124 142)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 128)(pt 16 128)(line_width 3))
-	)
-	(port
-		(pt 0 144)
-		(input)
-		(text "CLK" (rect 0 0 23 19)(font "Intel Clear" (font_size 8)))
-		(text "CLK" (rect 21 139 44 158)(font "Intel Clear" (font_size 8)))
-		(line (pt 0 144)(pt 16 144))
-	)
-	(port
-		(pt 256 32)
-		(output)
-		(text "mul1[15..0]" (rect 0 0 69 19)(font "Intel Clear" (font_size 8)))
-		(text "mul1[15..0]" (rect 166 27 235 46)(font "Intel Clear" (font_size 8)))
-		(line (pt 256 32)(pt 240 32)(line_width 3))
-	)
-	(port
-		(pt 256 48)
-		(output)
-		(text "mul2[15..0]" (rect 0 0 69 19)(font "Intel Clear" (font_size 8)))
-		(text "mul2[15..0]" (rect 166 43 235 62)(font "Intel Clear" (font_size 8)))
-		(line (pt 256 48)(pt 240 48)(line_width 3))
-	)
-	(port
-		(pt 256 64)
-		(output)
-		(text "Rout[15..0]" (rect 0 0 66 19)(font "Intel Clear" (font_size 8)))
-		(text "Rout[15..0]" (rect 169 59 235 78)(font "Intel Clear" (font_size 8)))
-		(line (pt 256 64)(pt 240 64)(line_width 3))
-	)
-	(port
-		(pt 256 80)
-		(output)
-		(text "COND" (rect 0 0 36 19)(font "Intel Clear" (font_size 8)))
-		(text "COND" (rect 199 75 235 94)(font "Intel Clear" (font_size 8)))
-		(line (pt 256 80)(pt 240 80))
-	)
-	(port
-		(pt 256 96)
-		(output)
-		(text "memaddr[10..0]" (rect 0 0 97 19)(font "Intel Clear" (font_size 8)))
-		(text "memaddr[10..0]" (rect 138 91 235 110)(font "Intel Clear" (font_size 8)))
-		(line (pt 256 96)(pt 240 96)(line_width 3))
-	)
-	(drawing
-		(rectangle (rect 16 16 240 176))
-	)
-)
 (symbol
 	(rect 936 160 1152 304)
 	(text "ram_data" (rect 74 0 137 16)(font "Arial" (font_size 10)))
@@ -942,7 +842,7 @@ https://fpgasoftware.intel.com/eula.
 		(pt 112 48)
 		(output)
 		(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
-		(text "result[]" (rect 75 35 107 49)(font "Arial" (font_size 8)))
+		(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
 		(line (pt 68 48)(pt 112 48)(line_width 3))
 	)
 	(parameter
@@ -990,7 +890,7 @@ https://fpgasoftware.intel.com/eula.
 		(pt 112 48)
 		(output)
 		(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
-		(text "result[]" (rect 75 35 107 49)(font "Arial" (font_size 8)))
+		(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
 		(line (pt 68 48)(pt 112 48)(line_width 3))
 	)
 	(parameter
@@ -1297,6 +1197,105 @@ https://fpgasoftware.intel.com/eula.
 		(rectangle (rect 16 16 192 384))
 	)
 )
+(symbol
+	(rect 928 320 1184 512)
+	(text "ALU_top" (rect 5 0 56 19)(font "Intel Clear" (font_size 8)))
+	(text "ALU" (rect 8 171 28 188)(font "Intel Clear" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "ALU_en" (rect 0 0 46 19)(font "Intel Clear" (font_size 8)))
+		(text "ALU_en" (rect 21 27 67 46)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "Rs1[15..0]" (rect 0 0 61 19)(font "Intel Clear" (font_size 8)))
+		(text "Rs1[15..0]" (rect 21 43 82 62)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "Rs2[15..0]" (rect 0 0 61 19)(font "Intel Clear" (font_size 8)))
+		(text "Rs2[15..0]" (rect 21 59 82 78)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "Rd[15..0]" (rect 0 0 55 19)(font "Intel Clear" (font_size 8)))
+		(text "Rd[15..0]" (rect 21 75 76 94)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "op[5..0]" (rect 0 0 46 19)(font "Intel Clear" (font_size 8)))
+		(text "op[5..0]" (rect 21 91 67 110)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 96)(pt 16 96)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "EXEC2" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
+		(text "EXEC2" (rect 21 107 59 126)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 112)(pt 16 112))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "stack_data[15..0]" (rect 0 0 103 19)(font "Intel Clear" (font_size 8)))
+		(text "stack_data[15..0]" (rect 21 123 124 142)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 128)(pt 16 128)(line_width 3))
+	)
+	(port
+		(pt 0 144)
+		(input)
+		(text "CLK" (rect 0 0 23 19)(font "Intel Clear" (font_size 8)))
+		(text "CLK" (rect 21 139 44 158)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 144)(pt 16 144))
+	)
+	(port
+		(pt 256 32)
+		(output)
+		(text "mul1[15..0]" (rect 0 0 69 19)(font "Intel Clear" (font_size 8)))
+		(text "mul1[15..0]" (rect 166 27 235 46)(font "Intel Clear" (font_size 8)))
+		(line (pt 256 32)(pt 240 32)(line_width 3))
+	)
+	(port
+		(pt 256 48)
+		(output)
+		(text "mul2[15..0]" (rect 0 0 69 19)(font "Intel Clear" (font_size 8)))
+		(text "mul2[15..0]" (rect 166 43 235 62)(font "Intel Clear" (font_size 8)))
+		(line (pt 256 48)(pt 240 48)(line_width 3))
+	)
+	(port
+		(pt 256 64)
+		(output)
+		(text "Rout[15..0]" (rect 0 0 66 19)(font "Intel Clear" (font_size 8)))
+		(text "Rout[15..0]" (rect 169 59 235 78)(font "Intel Clear" (font_size 8)))
+		(line (pt 256 64)(pt 240 64)(line_width 3))
+	)
+	(port
+		(pt 256 80)
+		(output)
+		(text "COND" (rect 0 0 36 19)(font "Intel Clear" (font_size 8)))
+		(text "COND" (rect 199 75 235 94)(font "Intel Clear" (font_size 8)))
+		(line (pt 256 80)(pt 240 80))
+	)
+	(port
+		(pt 256 96)
+		(output)
+		(text "memaddr[10..0]" (rect 0 0 97 19)(font "Intel Clear" (font_size 8)))
+		(text "memaddr[10..0]" (rect 138 91 235 110)(font "Intel Clear" (font_size 8)))
+		(line (pt 256 96)(pt 240 96)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 240 176))
+	)
+)
 (connector
 	(pt 856 192)
 	(pt 936 192)
diff --git a/CPUProject.qsf b/CPUProject.qsf
index 0e69956..d8e4b39 100644
--- a/CPUProject.qsf
+++ b/CPUProject.qsf
@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE AUTO
 set_global_assignment -name TOP_LEVEL_ENTITY CPUProject
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11  MAY 20, 2020"
-set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
@@ -62,12 +62,13 @@ set_global_assignment -name POWER_USE_PVA ON
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name VERILOG_FILE max_min.v
 set_global_assignment -name SDC_FILE CPUProject.sdc
 set_global_assignment -name VERILOG_FILE LIFOstack.v
 set_global_assignment -name VERILOG_FILE alu.v
 set_global_assignment -name MIF_FILE LUTSquares.mif
 set_global_assignment -name BDF_FILE mul8.bdf
-set_global_assignment -name BDF_FILE abs.bdf
 set_global_assignment -name BDF_FILE CPUProject.bdf
 set_global_assignment -name BDF_FILE reg_file.bdf
 set_global_assignment -name QIP_FILE ram_data.qip
@@ -77,13 +78,8 @@ set_global_assignment -name MIF_FILE data.mif
 set_global_assignment -name MIF_FILE instr.mif
 set_global_assignment -name BDF_FILE mul16.bdf
 set_global_assignment -name QIP_FILE LUT.qip
-set_global_assignment -name VERILOG_FILE min.v
 set_global_assignment -name VERILOG_FILE SM.v
 set_global_assignment -name BDF_FILE ALU_top.bdf
 set_global_assignment -name VERILOG_FILE mux_8x16.v
-set_global_assignment -name VERILOG_FILE mux_3x16.v
 set_global_assignment -name VERILOG_FILE ADD_1.v
-set_global_assignment -name VERILOG_FILE SM_pipelined.v
-set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
-set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
+set_global_assignment -name VERILOG_FILE SM_pipelined.v
\ No newline at end of file
diff --git a/CPUProject.qws b/CPUProject.qws
index d4099da20b1bda1e89b73250ae070e8477b55336..0371c294b31179f8778a90c83a1462484b66f0c7 100644
GIT binary patch
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fH&3o(NmOBg0**GI!m}{m|NsC0fiRHI$ix5u8gLi-

diff --git a/DECODE.bsf b/DECODE.bsf
index 8255261..7a4bebf 100644
--- a/DECODE.bsf
+++ b/DECODE.bsf
@@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 2019  Intel Corporation. All rights reserved.
+Copyright (C) 2018  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and any partner logic 
+and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
 (including device programming or simulation files), and any 
 associated documentation or information are expressly subject 
@@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license
 agreement, including, without limitation, that your use is for
 the sole purpose of programming logic devices manufactured by
 Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
+refer to the applicable agreement for further details.
 */
 (header "symbol" (version "1.1"))
 (symbol
diff --git a/DECODE.v b/DECODE.v
index 83f16e7..e20de6e 100644
--- a/DECODE.v
+++ b/DECODE.v
@@ -41,7 +41,8 @@ module DECODE
 	//Different opcodes (refer to documentation):
 	wire LDA =  msb & ~ls;
 	wire STA =  msb &  ls;
-	wire JMP = ~msb & ~op[5] & ~op[4] & ~op[3] & ~op[2];
+	wire JMP = ~msb & ~op[5] & ~op[4] & ~op[3] & ~op[2] & ~op[1] & ~op[0];
+	wire JMA = ~msb & ~op[5] & ~op[4] & ~op[3] & ~op[2] & ~op[1] &  op[0];
 	wire JCX = ~msb & ((~op[5] & ~op[4] & ~op[3] & op[2]) | (~op[5] & ~op[4] & op[3] & ~op[2]));
 	wire MUL = ~msb & ~op[5] &  op[4] &  op[3] &  op[2] & ~op[1] & ~op[0];
 	wire MLA = ~msb & ~op[5] &  op[4] &  op[3] &  op[2] & ~op[1] &  op[0];
@@ -50,37 +51,38 @@ module DECODE
 	wire POP = ~msb &  op[5] & ~op[4] &  op[3] & ~op[2] & ~op[1] &  op[0];
 	wire LDR = ~msb &  op[5] & ~op[4] &  op[3] & ~op[2] &  op[1] & ~op[0];
 	wire STR = ~msb &  op[5] & ~op[4] &  op[3] & ~op[2] &  op[1] &  op[0];
+	wire CLL = ~msb &  op[5] & ~op[4] & ~op[3] &  op[2] &  op[1] & ~op[0];
+	wire RTN = ~msb &  op[5] & ~op[4] & ~op[3] &  op[2] &  op[1] &  op[0];
 	wire NOP = ~msb &  op[5] &  op[4] &  op[3] &  op[2] &  op[1] & ~op[0];
 	wire STP = ~msb &  op[5] &  op[4] &  op[3] &  op[2] &  op[1] &  op[0];
 	
-	assign R0_count = EXEC1 & (~(JMP | (JCX & COND_result) | STP));
-	assign R0_en = (EXEC1 & (~(STA | NOP | STP | LDA | PSH | LDR) & ~Rd[2] & ~Rd[1] & ~Rd[0] | JMP | JCX & COND_result)) | (EXEC2 & LDA & ~Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & ~Rd[1] & ~Rd[0]);
-	assign R1_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & ~Rd[2] & ~Rd[1] &  Rd[0]) | (EXEC2 & LDA & ~Rls[2] & ~Rls[1] &  Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & ~Rd[1] &  Rd[0]);
-	assign R2_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & ~Rd[2] &  Rd[1] & ~Rd[0]) | (EXEC2 & LDA & ~Rls[2] &  Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] &  Rd[1] & ~Rd[0]);
-	assign R3_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & ~Rd[2] &  Rd[1] &  Rd[0]) | (EXEC2 & LDA & ~Rls[2] &  Rls[1] &  Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] &  Rd[1] &  Rd[0]);
-	assign R4_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) &  Rd[2] & ~Rd[1] & ~Rd[0]) | (EXEC2 & LDA &  Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) &  Rd[2] & ~Rd[1] & ~Rd[0]);
-	assign R5_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) &  Rd[2] & ~Rd[1] &  Rd[0]) | (EXEC2 & LDA &  Rls[2] & ~Rls[1] &  Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) &  Rd[2] & ~Rd[1] &  Rd[0]);
-	assign R6_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) &  Rd[2] &  Rd[1] & ~Rd[0]) | (EXEC2 & LDA &  Rls[2] &  Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) &  Rd[2] &  Rd[1] & ~Rd[0]);
-	assign R7_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) &  Rd[2] &  Rd[1] &  Rd[0]) | (EXEC2 & LDA &  Rls[2] &  Rls[1] &  Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) &  Rd[2] &  Rd[1] &  Rd[0]);
-	assign s1[2] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[2]) | (STA & Rls[2]);
-	assign s1[1] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[1]) | (STA & Rls[1]);
-	assign s1[0] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[0]) | (STA & Rls[0]);
-	assign s2[2] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[2]);
-	assign s2[1] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[1]);
-	assign s2[0] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[0]);
-	assign s3[2] = (~(STA | LDA | NOP | STP | PSH | POP) & Rd[2]);
-	assign s3[1] = (~(STA | LDA | NOP | STP | PSH | POP) & Rd[1]);
-	assign s3[0] = (~(STA | LDA | NOP | STP | PSH | POP) & Rd[0]);
+	assign R0_count = EXEC1 & (~(JMP | JMA | (JCX & COND_result) | STP | CLL | RTN));
+	assign R0_en = (EXEC1 & (~(STA | NOP | STP | LDA | PSH | LDR | CLL | RTN) & ~Rd[2] & ~Rd[1] & ~Rd[0] | JMP | (JCX & COND_result) | JMA)) | (EXEC2 & LDA & ~Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & ~Rd[1] & ~Rd[0]) | (EXEC2 & RTN) | (EXEC1 & CLL);
+	assign R1_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) & ~Rd[2] & ~Rd[1] &  Rd[0]) | (EXEC2 & LDA & ~Rls[2] & ~Rls[1] &  Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) & ~Rd[2] & ~Rd[1] &  Rd[0]);
+	assign R2_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) & ~Rd[2] &  Rd[1] & ~Rd[0]) | (EXEC2 & LDA & ~Rls[2] &  Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) & ~Rd[2] &  Rd[1] & ~Rd[0]);
+	assign R3_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) & ~Rd[2] &  Rd[1] &  Rd[0]) | (EXEC2 & LDA & ~Rls[2] &  Rls[1] &  Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) & ~Rd[2] &  Rd[1] &  Rd[0]);
+	assign R4_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) &  Rd[2] & ~Rd[1] & ~Rd[0]) | (EXEC2 & LDA &  Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) &  Rd[2] & ~Rd[1] & ~Rd[0]);
+	assign R5_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) &  Rd[2] & ~Rd[1] &  Rd[0]) | (EXEC2 & LDA &  Rls[2] & ~Rls[1] &  Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) &  Rd[2] & ~Rd[1] &  Rd[0]);
+	assign R6_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) &  Rd[2] &  Rd[1] & ~Rd[0]) | (EXEC2 & LDA &  Rls[2] &  Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) &  Rd[2] &  Rd[1] & ~Rd[0]);
+	assign R7_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) &  Rd[2] &  Rd[1] &  Rd[0]) | (EXEC2 & LDA &  Rls[2] &  Rls[1] &  Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) &  Rd[2] &  Rd[1] &  Rd[0]);
+	assign s1[2] = (~(JMP | JMA | STA | LDA | NOP | STP | POP | CLL | RTN) & Rs1[2]) | (STA & Rls[2]);
+	assign s1[1] = (~(JMP | JMA | STA | LDA | NOP | STP | POP | CLL | RTN) & Rs1[1]) | (STA & Rls[1]);
+	assign s1[0] = (~(JMP | JMA | STA | LDA | NOP | STP | POP | CLL | RTN) & Rs1[0]) | (STA & Rls[0]);
+	assign s2[2] = (~(JMP | JMA | STA | LDA | NOP | STP | POP | PSH | LDR | STR | CLL | RTN) & Rs2[2]);
+	assign s2[1] = (~(JMP | JMA | STA | LDA | NOP | STP | POP | PSH | LDR | STR | CLL | RTN) & Rs2[1]);
+	assign s2[0] = (~(JMP | JMA | STA | LDA | NOP | STP | POP | PSH | LDR | STR | CLL | RTN) & Rs2[0]);
+	assign s3[2] = (~(STA | LDA | NOP | STP | PSH | POP | RTN) & Rd[2]);
+	assign s3[1] = (~(STA | LDA | NOP | STP | PSH | POP | RTN) & Rd[1]);
+	assign s3[0] = (~(STA | LDA | NOP | STP | PSH | POP | RTN) & Rd[0]);
 	assign s4 = ~(LDA | LDR);
 	assign RAMd_wren = EXEC1 & (STA | STR);
 	assign RAMd_en = EXEC1 & (STA | LDA | STR | LDR);
 	assign RAMi_en = FETCH;
 	assign ALU_en = LDA | STA;
-	assign E2 = EXEC1 & (LDA | MUL | MLA | MLS | POP | LDR);
-	assign stack_en = (EXEC1 & PSH) | ((EXEC1 | EXEC2) & POP);
+	assign E2 = EXEC1 & (LDA | MUL | MLA | MLS | POP | LDR | RTN);
+	assign stack_en = (EXEC1 & (PSH | CLL | RTN | POP));
 	assign stack_rst = STP;
-	assign stack_rw = EXEC1 & PSH;
+	assign stack_rw = EXEC1 & (PSH | CLL);
 	assign s5 = EXEC1 & (STR | LDR);
 	
 endmodule
-	
\ No newline at end of file
diff --git a/alu.bsf b/alu.bsf
index 010863f..1882d43 100644
--- a/alu.bsf
+++ b/alu.bsf
@@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 2019  Intel Corporation. All rights reserved.
+Copyright (C) 2018  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and any partner logic 
+and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
 (including device programming or simulation files), and any 
 associated documentation or information are expressly subject 
@@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license
 agreement, including, without limitation, that your use is for
 the sole purpose of programming logic devices manufactured by
 Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
+refer to the applicable agreement for further details.
 */
 (header "symbol" (version "1.1"))
 (symbol
@@ -55,8 +54,8 @@ https://fpgasoftware.intel.com/eula.
 	(port
 		(pt 0 96)
 		(input)
-		(text "opcode[5..0]" (rect 0 0 48 12)(font "Arial" ))
-		(text "opcode[5..0]" (rect 21 91 69 103)(font "Arial" ))
+		(text "instr[15..0]" (rect 0 0 40 12)(font "Arial" ))
+		(text "instr[15..0]" (rect 21 91 61 103)(font "Arial" ))
 		(line (pt 0 96)(pt 16 96)(line_width 3))
 	)
 	(port
diff --git a/alu.v b/alu.v
index f9205c8..d1eeb68 100644
--- a/alu.v
+++ b/alu.v
@@ -1,10 +1,10 @@
-module alu (enable, Rs1, Rs2, Rd, opcode, mulresult, exec2, stackout, mul1, mul2, Rout, jump, memaddr);
+module alu (enable, Rs1, Rs2, Rd, instr, mulresult, exec2, stackout, mul1, mul2, Rout, jump, memaddr);
 
 input enable; // active LOW, disables the ALU during load/store operations so that undefined behaviour does not occur
 input signed [15:0] Rs1; // input source register 1
 input signed [15:0] Rs2; // input source register 2
 input signed [15:0] Rd; // input destination register
-input [5:0] opcode; // opcode is fed in from instruction using wires outside ALU
+input [15:0] instr; // opcode is fed in from instruction using wires outside ALU
 input signed [31:0] mulresult; // 32-bit result from multiplier
 input exec2; // Input from state machine to indicate when to take in result from multiplication
 input [15:0] stackout; // input from stack to be fed back to registers
@@ -13,9 +13,10 @@ output reg signed [15:0] mul1; // first number to be multiplied
 output reg signed [15:0] mul2; // second number to be multiplied
 output signed [15:0] Rout; // value to be saved to destination register
 output jump; // tells decoder whether Jump condition is true
-reg carry; // Internal carry register that is updated during appropriate opcodes
+reg carry; // Internal carry register that is updated during appropriate opcodes, also provides output for debugging
 output reg [10:0] memaddr; // address to load data from / store data to RAMd
 
+wire [5:0]opcode = instr[14:9]; //opcode of current instruction
 reg signed [16:0] alusum; // extra bit to hold carry from operations other than Multiply
 assign Rout = alusum [15:0];
 assign jump = (alusum[16] && ((opcode[5:2] == 4'b0000) | (opcode[5:2] == 4'b0001) | (opcode[5:2] == 4'b0010)));
@@ -157,9 +158,13 @@ always @(opcode, mulresult)
 				6'b100011: ;
 				
 				6'b100100: alusum = {1'b0, (Rs1 >> Rs2[3:0]) | (Rs1 << (16 - Rs2[3:0]))}; // ROR Shift Right Loop (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Rs1[15])
-				6'b100101: alusum = ({Rs1, carry} >> (Rs2 % 17)) | ({Rs1, carry} << (17 - (Rs2 % 17)));// RRC Shift Right Loop w/ Carry (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Carry & Carry -> Rs1[15])
-				6'b100110: ;
-				6'b100111: ;
+//				6'b100101: alusum = ({Rs1, carry} >> (Rs2 % 17)) | ({Rs1, carry} << (17 - (Rs2 % 17)));// RRC Shift Right Loop w/ Carry (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Carry & Carry -> Rs1[15])
+				6'b100110: alusum = {1'b1, Rd}; //CLL function call
+				6'b100111: begin  //RTN return to prev call
+						if(exec2) begin
+								alusum = {1'b0, stackout}; 
+							end
+					end
 				
 				6'b101000: alusum = {1'b0, Rs1}; // PSH Push value to stack (Stack = Rs1)
 				6'b101001: alusum = {1'b0, stackout}; // POP Pop value from stack (Rd = Stack)
@@ -183,4 +188,4 @@ always @(opcode, mulresult)
 			end
 	end
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/mux_3x16.bsf b/mux_3x16.bsf
deleted file mode 100644
index 398ef64..0000000
--- a/mux_3x16.bsf
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2018  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
-	(rect 16 16 200 128)
-	(text "mux_3x16" (rect 5 0 46 12)(font "Arial" ))
-	(text "inst" (rect 8 96 20 108)(font "Arial" ))
-	(port
-		(pt 0 32)
-		(input)
-		(text "s[1..0]" (rect 0 0 23 12)(font "Arial" ))
-		(text "s[1..0]" (rect 21 27 44 39)(font "Arial" ))
-		(line (pt 0 32)(pt 16 32)(line_width 3))
-	)
-	(port
-		(pt 0 48)
-		(input)
-		(text "in0[15..0]" (rect 0 0 34 12)(font "Arial" ))
-		(text "in0[15..0]" (rect 21 43 55 55)(font "Arial" ))
-		(line (pt 0 48)(pt 16 48)(line_width 3))
-	)
-	(port
-		(pt 0 64)
-		(input)
-		(text "in1[15..0]" (rect 0 0 33 12)(font "Arial" ))
-		(text "in1[15..0]" (rect 21 59 54 71)(font "Arial" ))
-		(line (pt 0 64)(pt 16 64)(line_width 3))
-	)
-	(port
-		(pt 0 80)
-		(input)
-		(text "in2[15..0]" (rect 0 0 34 12)(font "Arial" ))
-		(text "in2[15..0]" (rect 21 75 55 87)(font "Arial" ))
-		(line (pt 0 80)(pt 16 80)(line_width 3))
-	)
-	(port
-		(pt 184 32)
-		(output)
-		(text "result[15..0]" (rect 0 0 44 12)(font "Arial" ))
-		(text "result[15..0]" (rect 119 27 163 39)(font "Arial" ))
-		(line (pt 184 32)(pt 168 32)(line_width 3))
-	)
-	(drawing
-		(rectangle (rect 16 16 168 96)(line_width 1))
-	)
-)
diff --git a/mux_3x16.v b/mux_3x16.v
deleted file mode 100644
index 850df4f..0000000
--- a/mux_3x16.v
+++ /dev/null
@@ -1,19 +0,0 @@
-module mux_3x16 (s, in0, in1, in2, result);
-
-input [1:0]s;
-input [15:0]in0;
-input [15:0]in1;
-input [15:0]in2;
-
-output reg [15:0]result;
-
-always @(*) begin
-	case(s)
-		2'b00: result = in0;
-		2'b01: result = in1;
-		2'b10: result = in2;
-		default: result = in0;
-	endcase
-end
-
-endmodule
diff --git a/mux_3x16.v.bak b/mux_3x16.v.bak
deleted file mode 100644
index 710f8c1..0000000
--- a/mux_3x16.v.bak
+++ /dev/null
@@ -1,18 +0,0 @@
-module mux_3x16 (s, in0, in1, in2, result);
-
-input [1:0]s;
-input [15:0]in0;
-input [15:0]in1;
-input [15:0]in2;
-
-output reg [15:0]result;
-
-always @(*) begin
-	case(s)
-		2'b00: result = in0;
-		2'b01: result = in1;
-		2'b10: result = in2;
-	endcase
-end
-
-endmodule