Source files and notes of my Final Year Project, as part of an MEng in Electronics and Information Engineering from Imperial College London
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2023-05-18 12:35:39 +01:00
demo Update note.cpp and main.cpp for new CSRStorage layout 2023-05-18 11:38:39 +01:00
rtl Support selecting waveform in genSaw 2023-05-18 12:35:39 +01:00
.gitignore Update .gitignore 2023-05-15 17:55:41 +01:00
.svlint.toml Clean up .svlint.toml 2023-05-18 12:34:03 +01:00
build.sh Fix build script, incorrectly traps on ERR 2023-05-12 19:53:52 +01:00
make.py Update note.cpp and main.cpp for new CSRStorage layout 2023-05-18 11:38:39 +01:00
options.sh Initial commit to prevent data loss 2023-02-05 00:56:34 +00:00
pcmFifo.py Add shell pcmFifo LiteX module (basic inst, no logic) 2023-03-10 17:48:18 +00:00
readme.md Add docs link for MigenAsyncFIFO to readme 2023-05-16 22:22:19 +01:00
testLED.py Signal prefixes are removed by migen, so double 2023-03-03 17:05:53 +00:00
testRGB.py Remove reset value from TestRgb 2023-03-04 14:54:09 +00:00
testSaw.py Support selecting waveform in genSaw 2023-05-18 12:35:39 +01:00

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