Source files and notes of my Final Year Project, as part of an MEng in Electronics and Information Engineering from Imperial College London
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2023-06-25 12:15:05 +01:00
demo Increase CORDIC time to 7 cycles from 3, reduce osc to 32 2023-06-25 12:15:05 +01:00
modules Tidy project 2023-06-18 17:25:53 +01:00
notes Tidy project 2023-06-18 17:25:53 +01:00
rtl Increase CORDIC time to 7 cycles from 3, reduce osc to 32 2023-06-25 12:15:05 +01:00
.gitignore Tidy project 2023-06-18 17:25:53 +01:00
.svlint.toml Clean up .svlint.toml 2023-05-18 12:34:03 +01:00
build.sh Fix build script exits 2023-06-24 15:50:19 +01:00
make.py Comment out LiteScope Analyzer, low comb remaining 2023-06-24 20:52:22 +01:00
readme.md Add links to readme 2023-06-24 20:52:44 +01:00

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