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Łukasz Czyż 2019-12-02 12:30:07 +01:00 committed by GitHub
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@ -4,6 +4,15 @@ Zero-cost abstraction register library generator.
*svd2cpp* is a generator that parses .svd files provided by ARM chip vendor. *svd2cpp* is a generator that parses .svd files provided by ARM chip vendor.
It generates header file that allows for reading and writing to microcontroller's registers with zero overhead. It generates header file that allows for reading and writing to microcontroller's registers with zero overhead.
### Benefits
1. **Compile-time checking.** This is an aspect that is making this solution better than any other parser/pre-generated header.
* You won't be able to write to wrong register.
* You won't be able to write wrong value (i.e. 0b1011 to 3-bit field) to register.
* You can't read from write-only or write to read-only register.
Any attempt to do something wrong will succeed in error at **compile-time** - no more runtime debugging to find out misspelling errors!
2. **Zero-cost abstraction.** Another strong aspect of headers generated by *svd2cpp* is that using it in code will result in zero overhead because all of the checking is done at compile-time.
3. **Portability.** As long as manufacturer provides .svd files in CMSIS-SVD format (and most major manufacturers of Cortex-M based chips does), you can use it with this parser.
## How to get *svd2cpp*? ## How to get *svd2cpp*?
Download source code and compile it. Note that this repo uses submodules thus do not forget to `git submodule init` and `git submodule update` after cloning. Download source code and compile it. Note that this repo uses submodules thus do not forget to `git submodule init` and `git submodule update` after cloning.
@ -25,22 +34,22 @@ Syntax is quite simple and easy to use:
operation<PERIPHERAL::REGISTER::BIT>(); operation<PERIPHERAL::REGISTER::BIT>();
``` ```
### Examples: ### Examples:
Set bit UE(USART enable) in USART1 Control Register 1 Set bit UE(USART enable) in USART1 Control Register 1:
```cpp ```cpp
set<USART1::CR1::UE>(); set<USART1::CR1::UE>();
``` ```
Reset bit UE(USART enable) in USART1 Control Register 1 Reset bit UE(USART enable) in USART1 Control Register 1:
```cpp ```cpp
reset<USART1::CR1::UE>(); reset<USART1::CR1::UE>();
``` ```
Read Channel 1 Transfer Complete flag in DMA1 ISR Register Read Channel 1 Transfer Complete flag in DMA1 ISR Register:
```cpp ```cpp
bool transferComplete = read<DMA1::ISR::TCIF1>(); bool transferComplete = read<DMA1::ISR::TCIF1>();
``` ```
Set Memory address for DMA1 channel 2 Set Memory address for DMA1 channel 2:
```cpp ```cpp
set<DMA1::CMAR2::MA>(0xDEADBEEF); set<DMA1::CMAR2::MA>(0xDEADBEEF);
``` ```