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SystemVerilog CORDIC block that converts from an input phase (sawtooth wave) to a sine wave
4 commits 1 branch 0 tags 34 KiB
SystemVerilog 78.6%
Python 15.6%
Makefile 5.8%
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Aadi Desai 6475de9495
Add cordic.sv and test_saw2sin.py 
test_saw2sin.py: cocotb testbench using verilator
cordic.sv: o_sin adjustments mask erratic results at extremes, avg error is 1.346 vs testbench
2023-05-28 16:15:56 +01:00
cordic.sv Add cordic.sv and test_saw2sin.py 2023-05-28 16:15:56 +01:00
LICENSE Initial commit 2023-05-28 16:01:36 +01:00
Makefile Add cordic.sv and test_saw2sin.py 2023-05-28 16:15:56 +01:00
README.md Initial commit 2023-05-28 16:01:36 +01:00
saw2sin.sv Add saw2sin.sv 2023-05-28 16:04:18 +01:00
saw2sin_poly.sv Add saw2sin_poly.sv 2023-05-28 16:03:39 +01:00
test_saw2sin.py Add cordic.sv and test_saw2sin.py 2023-05-28 16:15:56 +01:00

README.md

cordic

SystemVerilog CORDIC block that converts from an input phase (sawtooth wave) to a sine wave