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SystemVerilog CORDIC block that converts from an input phase (sawtooth wave) to a sine wave
9 commits 1 branch 0 tags 34 KiB
SystemVerilog 78.6%
Python 15.6%
Makefile 5.8%
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Aadi Desai 550827217c
Output error from expected correctly, - means low
2023-05-30 14:15:44 +01:00
cordic.sv Further adjust bit offsets, improve accuracy from 1.34601 to 0.455326 2023-05-30 13:49:23 +01:00
LICENSE Initial commit 2023-05-28 16:01:36 +01:00
Makefile Add cordic.sv and test_saw2sin.py 2023-05-28 16:15:56 +01:00
README.md Update README.md 2023-05-28 16:24:06 +01:00
saw2sin.sv Further adjust bit offsets, improve accuracy from 1.34601 to 0.455326 2023-05-30 13:49:23 +01:00
saw2sin_poly.sv Add saw2sin_poly.sv 2023-05-28 16:03:39 +01:00
test_saw2sin.py Output error from expected correctly, - means low 2023-05-30 14:15:44 +01:00

README.md

cordic

SystemVerilog CORDIC block that converts from an input phase (sawtooth wave) to a sine wave

cordic.sv

Input: 0-65535 (16 bit) = $0$-\frac{\pi}{2} radians or $0$-$90$°

Output: 0-65535 (16 bit) = $0$-1