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// Driver module for use with AXI4-Lite bus, with exported DPI-C functions
// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
module Axi4LiteDriver
#(parameter int AWIDTH = 12 // Default: 4KB, [1:0] ignored = word aligned accesses
, parameter int DWIDTH = 32 // AXI4-Lite Data bus is 32/64 bit only
, parameter int SWIDTH = DWIDTH / 8 // Strobe width = data width / 8
)(input var logic i_aClk
, input var logic i_aResetn
// Read Address Channel (Master -> Slave)
, output var logic o_arValid
, input var logic i_arReady
, output var logic [AWIDTH-1:0] o_arAddr
, output var Protection o_arProt
// Read Data Channel (Slave -> Master)
, input var logic i_rValid
, output var logic o_rReady
, input var logic [DWIDTH-1:0] i_rData
, input var Response i_rResp
// Write Address Channel (Master -> Slave)
, output var logic o_awValid
, input var logic i_awReady
, output var logic [AWIDTH-1:0] o_awAddr
, output var Protection o_awProt
// Write Data Channel (Master -> Slave)
, output var logic o_wValid
, input var logic i_wReady
, output var logic [DWIDTH-1:0] o_wData
, output var logic [SWIDTH-1:0] o_wStrb
// Write Response Channel (Slave -> Master)
, input var logic i_bValid
, output var logic o_bReady
, input var Response i_bResp
);
endmodule
`resetall

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// AXI4-Lite compatible memory module, for testing driver module
// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
typedef enum bit [1:0]
{ OKAY = 2'b00
, EXOKAY = 2'b01
, SLVERR = 2'b10
, DECERR = 2'b11
} Response;
typedef enum bit [2:0]
{ UNPRIV_SEC_DATA = 3'b000 // Unprivileged, secure, data access
, PRIV_SEC_DATA = 3'b001 // Privileged, secure, data access
, UNPRIV_NONSEC_DATA = 3'b010 // Unprivileged, non-secure, data access
, PRIV_NONSEC_DATA = 3'b011 // Privileged, non-secure, data access
, UNPRIV_SEC_INSTR = 3'b100 // Unprivileged, secure, instruction access
, PRIV_SEC_INSTR = 3'b101 // Privileged, secure, instruction access
, UNPRIV_NONSEC_INSTR = 3'b110 // Unprivileged, non-secure, instruction access
, PRIV_NONSEC_INSTR = 3'b111 // Privileged, non-secure, instruction access
} Protection;
module Axi4LiteSlave
#(parameter int AWIDTH = 12
, parameter int DWIDTH = 32
, parameter int SWIDTH = DWIDTH / 8
)(input var logic i_aClk
, input var logic i_aResetn
// Read Address Channel (Master -> Slave)
, input var logic i_arValid
, output var logic o_arReady
, input var logic [AWIDTH-1:0] i_arAddr
, input var Protection i_arProt
// Read Data Channel (Slave -> Master)
, output var logic o_rValid
, input var logic i_rReady
, output var logic [DWIDTH-1:0] o_rData
, output var Response o_rResp
// Write Address Channel (Master -> Slave)
, input var logic i_awValid
, output var logic o_awReady
, input var logic [AWIDTH-1:0] i_awAddr
, input var Protection i_awProt
// Write Data Channel (Master -> Slave)
, input var logic i_wValid
, output var logic o_wReady
, input var logic [DWIDTH-1:0] i_wData
, input var logic [SWIDTH-1:0] i_wStrb
// Write Response Channel (Slave -> Master)
, output var logic o_bValid
, input var logic i_bReady
, output var Response o_bResp
);
logic [DWIDTH-1:0] mem [4096];
logic [DWIDTH-1:0] wDataStrb;
for (genvar i = 0; i < SWIDTH; i++) begin : la_StrobedWriteData
assign wDataStrb[8*i+7:8*i] = i_wStrb[i] ? i_wData[8*i+7:8*i] : mem[i_awAddr][8*i+7:8*i];
end
enum bit [0:0]
{ IDLE
, READ
} rState;
enum bit [2:0]
{ IDLE
, WRITE
} wState;
always_ff @(posedge i_aClk)
if (!i_aResetn) begin
o_arReady <= '0;
o_rValid <= '0;
o_rData <= '0;
o_rResp <= '0;
end else
case (rState)
IDLE: begin
if (i_arValid) begin
o_arReady <= '1;
o_rValid <= '1;
o_rData <= mem[i_arAddr];
o_rResp <= Response'(OKAY);
rState <= READ;
end else
rState <= IDLE;
end
READ: begin
o_arReady <= '0;
if (i_rReady) begin
o_rValid <= '0;
o_rData <= '0;
o_rResp <= '0;
rState <= IDLE;
end else
rState <= READ;
end
default: begin
o_arReady <= '0;
o_rValid <= '0;
o_rData <= '0;
o_rResp <= '0;
end
endcase
always_ff @(posedge i_aClk)
if (!i_aResetn) begin
o_awReady <= '0;
o_wReady <= '0;
o_bValid <= '0;
o_bResp <= '0;
end else
case (wState)
IDLE: begin
if (i_awValid && i_wValid) begin
o_awReady <= '1;
mem[i_awAddr] <= wDataStrb;
o_wReady <= '1;
o_bValid <= '1;
o_bResp <= Response'(OKAY);
wState <= WRITE;
end else
wState <= IDLE;
end
WRITE: begin
o_awReady <= '0;
o_wReady <= '0;
if (i_bReady) begin
o_bValid <= '0;
o_bResp <= '0;
wState <= IDLE;
end else
wState <= WRITE;
end
default: begin
o_awReady <= '0;
o_wReady <= '0;
o_bValid <= '0;
o_bResp <= '0;
end
endcase
endmodule
`resetall

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# axiTest
AXI4-Lite compatible Driver module for use with Verilator and other DPI-C compatible simulators. WIP

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// Header file to be used in verilator C++ testbenches.
// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
// SPDX-License-Identifier: Apache-2.0
//
// Intended usage / order:
// - VerilatorTbFst<Vtest_DUT> *tb = new VerilatorTbFst<Vtest_DUT>();
// - tb->setClockPeriodPS(clock_period_in_picoseconds);
// - This value can be taken from within the SystemVerilog Testbench
// - tb->opentrace("output/test_DUT.verilator.fst");
// - tb->m_trace->dump(0);
// - Followed by arst/rst and signals matching the intended testbench flow.
#ifndef _VERILATORTBFST_H
#define _VERILATORTBFST_H
#include <stdbool.h>
#include <stdio.h>
#include <string.h>
#include <svdpi.h>
#include <verilated_fst_c.h>
typedef enum {
ERROR,
WARN,
NOTE
} TbPrintLevel;
template <class VA>
class VerilatorTbFst {
public:
VA *m_dut;
VerilatedFstC *m_trace;
uint64_t m_tickcount;
uint64_t m_clockperiod;
bool m_dodump;
VerilatorTbFst(void) : m_trace(NULL), m_tickcount(0l) {
m_dut = new VA;
Verilated::traceEverOn(true);
m_dut->i_clk = 0;
m_dut->i_rst = 1;
m_dodump = true;
eval(); // Get our initial values set properly.
}
virtual ~VerilatorTbFst(void) {
closetrace();
delete m_dut;
m_dut = NULL;
}
virtual void setClockPeriodPS(const uint64_t ps) {
m_clockperiod = ps;
}
virtual void opentrace(const char *fstname) {
opentrace(fstname, 99);
}
virtual void opentrace(const char *fstname, int tracedepth) {
if (!m_trace) {
m_trace = new VerilatedFstC;
m_dut->trace(m_trace, tracedepth);
m_trace->open(fstname);
}
}
virtual void closetrace(void) {
if (m_trace) {
m_trace->close();
delete m_trace;
m_trace = NULL;
}
}
virtual void eval(void) {
m_dut->eval();
}
// Call from loop {check, drive, tick}
virtual void tick(void) {
// check
// drive
// rise eval dump
// fall eval dump
m_dut->i_clk = 1;
eval();
if (m_dodump && m_trace) {
m_trace->dump((uint64_t)(m_clockperiod * m_tickcount));
}
m_dut->i_clk = 0;
eval();
if (m_dodump && m_trace) {
m_trace->dump((uint64_t)(m_clockperiod * m_tickcount + (m_clockperiod / 2)));
m_trace->flush();
}
m_tickcount++;
}
virtual void ticks(int numTicks) {
for (int i = 0; i < numTicks; i++)
tick();
}
virtual void areset(void) {
m_dut->i_arst = 0;
tick();
m_dut->i_arst = 1;
ticks(4);
m_dut->i_arst = 0;
}
virtual void reset(void) {
m_dut->i_rst = 1;
ticks(5);
m_dut->i_rst = 0;
}
unsigned long tickcount(void) {
return m_tickcount;
}
virtual bool done(void) {
return Verilated::gotFinish();
}
virtual void setScope(const char *scopeName) {
char fullScopeName[1024];
svSetScope(svGetScopeFromName(strcat(strcpy(fullScopeName, "TOP."), scopeName)));
}
};
#endif // _VERILATORTBFST_H

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// C++ Verilator testbench for checking AXI4-Lite Driver module
// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
// SPDX-License-Identifier: Apache-2.0
#include <VaxiTest.h>
#include <VaxiTest__Dpi.h>
#include <VerilatorTbFst.h>
#include <iostream>
#include <stdlib.h>
#include <string>
#include <svdpi.h>
#include <verilated.h>
#ifndef N_CYCLES
#define N_CYCLES 100
#endif
int main(int argc, char **argv, char **env) {
Verilated::commandArgs(argc, argv);
VerilatorTbFst<VaxiTest> *tb = new VerilatorTbFst<VaxiTest>();
tb->setScope("axiTest");
// Get SystemVerilog Parameters
const uint64_t CLOCK_PERIOD_PS = 10;
tb->setClockPeriodPS(2 * (CLOCK_PERIOD_PS / 3));
tb->opentrace("output/VaxiTest.fst");
tb->m_trace->dump(0); // Initialize waveform at beginning of time.
printf("Starting!\n");
tb->m_dut->i_rst = 1;
tb->ticks(2);
tb->m_dut->i_rst = 0;
tb->ticks(2);
while (tb->tickcount() < N_CYCLES * 2) {
tb->ticks(2); // Run Tests
}
printf("Time: %ldns\n", tb->tickcount());
printf("Stopped.\n");
tb->closetrace();
exit(EXIT_SUCCESS);
}

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// SystemVerilog testbench to instantiate AXI4-Lite driver and memory modules
// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
// Verilator Class support is limited but in active development. Verilator
// supports members, and methods. Verilator does not support class static
// members, class extend, or class parameters.
module axiTest
( input var logic i_clk
, input var logic i_rst
, input var logic i_arst
);
Axi4LiteSlave
#(.AWIDTH (12 )
, .DWIDTH (32 )
) u_axiSlave
( .i_aClk (aClk )
, .i_aResetn (aResetn)
// Read Address Channel (Master -> Slave)
, .i_arValid (arValid)
, .o_arReady (arReady)
, .i_arAddr (arAddr )
, .i_arProt (arProt )
// Read Data Channel (Slave -> Master)
, .o_rValid (rValid )
, .i_rReady (rReady )
, .o_rData (rData )
, .o_rResp (rResp )
// Write Address Channel (Master -> Slave)
, .i_awValid (awValid)
, .o_awReady (awReady)
, .i_awAddr (awAddr )
, .i_awProt (awProt )
// Write Data Channel (Master -> Slave)
, .i_wValid (wValid )
, .o_wReady (wReady )
, .i_wData (wData )
, .i_wStrb (wStrb )
// Write Response Channel (Slave -> Master)
, .o_bValid (bValid )
, .i_bReady (bReady )
, .o_bResp (bResp )
);
generateClock u_generateClock
( .o_clk (aClk ) // Generated clock for testbench
, .i_rootClk (i_clk) // V_erilator clock input
, .i_periodHi (0 ) // Number of rootClk cycles-1 to stay high
, .i_periodLo (0 ) // Number of rootClk cycles-1 to stay low
, .i_jitterControl (0 ) // Random jitter control (0: none --> higher number: more jitter)
);
Axi4LiteDriver
#(.AWIDTH (12 )
, .DWIDTH (32 )
) u_axiDriver
( .i_aClk (aClk )
, .i_aResetn (aResetn)
// Read Address Channel (Master -> Slave)
, .o_arValid (arValid)
, .i_arReady (arReady)
, .o_arAddr (arAddr )
, .o_arProt (arProt )
// Read Data Channel (Slave -> Master)
, .i_rValid (rValid )
, .o_rReady (rReady )
, .i_rData (rData )
, .i_rResp (rResp )
// Write Address Channel (Master -> Slave)
, .o_awValid (awValid)
, .i_awReady (awReady)
, .o_awAddr (awAddr )
, .o_awProt (awProt )
// Write Data Channel (Master -> Slave)
, .o_wValid (wValid )
, .i_wReady (wReady )
, .o_wData (wData )
, .o_wStrb (wStrb )
// Write Response Channel (Slave -> Master)
, .i_bValid (bValid )
, .o_bReady (bReady )
, .i_bResp (bResp )
);
endmodule
`resetall

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// V_erilator clock generation module, allows for the clock to be "stepped down" for use within the testbench
// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
module generateClock
( output var logic o_clk // Generated clock for testbench
, input var logic i_rootClk // V_erilator clock input
, input var logic [63:0] i_periodHi // Number of rootClk cycles-1 to stay high
, input var logic [63:0] i_periodLo // Number of rootClk cycles-1 to stay low
, input var logic [ 7:0] i_jitterControl // Random jitter control (0: none --> higher number: more jitter)
);
logic intClk_d;
logic intClk_q;
logic [63:0] downCounter_d;
logic [63:0] downCounter_q;
/* svlint off legacy_always */
always @(posedge i_rootClk)
intClk_q <= intClk_d;
always @(posedge i_rootClk)
downCounter_q <= downCounter_d;
/* svlint on legacy_always */
logic [7:0] rndJitter;
always_ff @(posedge i_rootClk)
/* verilator lint_off WIDTH */
rndJitter <= $random;
/* verilator lint_on WIDTH */
logic jitterThisCycle;
assign jitterThisCycle = (rndJitter < i_jitterControl);
always_comb
if (downCounter_q == '0)
if (jitterThisCycle)
downCounter_d = downCounter_q;
else if (intClk_q)
downCounter_d = i_periodLo;
else
downCounter_d = i_periodHi;
else
downCounter_d = downCounter_q - 'd1;
always_comb
if ((downCounter_q == '0) && !jitterThisCycle)
intClk_d = ~intClk_q;
else
intClk_d = intClk_q;
assign o_clk = intClk_q;
endmodule
`resetall

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#!/usr/bin/env bash
rm output/*
mkdir -p output
verilator --trace-fst -DUSE_FST -CFLAGS -DUSEFST --cc --exe --default-language 1800-2017 --trace-depth 5 -DN_CYCLES=25 -CFLAGS -DN_CYCLES=25 --Mdir output -Wall axiTest.cpp axiTest.sv
make -C output -f VaxiTest.mk VaxiTest
time output/VaxiTest > output/verilator.log
! grep -q ERROR output/verilator.log