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149 lines
4.2 KiB
Systemverilog
149 lines
4.2 KiB
Systemverilog
// AXI4-Lite compatible memory module, for testing driver module
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// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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typedef enum bit [1:0]
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{ OKAY = 2'b00
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, EXOKAY = 2'b01
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, SLVERR = 2'b10
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, DECERR = 2'b11
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} Response;
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typedef enum bit [2:0]
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{ UNPRIV_SEC_DATA = 3'b000 // Unprivileged, secure, data access
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, PRIV_SEC_DATA = 3'b001 // Privileged, secure, data access
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, UNPRIV_NONSEC_DATA = 3'b010 // Unprivileged, non-secure, data access
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, PRIV_NONSEC_DATA = 3'b011 // Privileged, non-secure, data access
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, UNPRIV_SEC_INSTR = 3'b100 // Unprivileged, secure, instruction access
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, PRIV_SEC_INSTR = 3'b101 // Privileged, secure, instruction access
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, UNPRIV_NONSEC_INSTR = 3'b110 // Unprivileged, non-secure, instruction access
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, PRIV_NONSEC_INSTR = 3'b111 // Privileged, non-secure, instruction access
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} Protection;
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module Axi4LiteSlave
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#(parameter int AWIDTH = 12
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, parameter int DWIDTH = 32
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, parameter int SWIDTH = DWIDTH / 8
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)(input var logic i_aClk
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, input var logic i_aResetn
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// Read Address Channel (Master -> Slave)
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, input var logic i_arValid
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, output var logic o_arReady
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, input var logic [AWIDTH-1:0] i_arAddr
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, input var Protection i_arProt
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// Read Data Channel (Slave -> Master)
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, output var logic o_rValid
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, input var logic i_rReady
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, output var logic [DWIDTH-1:0] o_rData
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, output var Response o_rResp
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// Write Address Channel (Master -> Slave)
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, input var logic i_awValid
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, output var logic o_awReady
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, input var logic [AWIDTH-1:0] i_awAddr
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, input var Protection i_awProt
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// Write Data Channel (Master -> Slave)
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, input var logic i_wValid
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, output var logic o_wReady
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, input var logic [DWIDTH-1:0] i_wData
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, input var logic [SWIDTH-1:0] i_wStrb
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// Write Response Channel (Slave -> Master)
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, output var logic o_bValid
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, input var logic i_bReady
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, output var Response o_bResp
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);
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logic [DWIDTH-1:0] mem [4096];
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logic [DWIDTH-1:0] wDataStrb;
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for (genvar i = 0; i < SWIDTH; i++) begin : la_StrobedWriteData
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assign wDataStrb[8*i+7:8*i] = i_wStrb[i] ? i_wData[8*i+7:8*i] : mem[i_awAddr][8*i+7:8*i];
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end
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enum bit [0:0]
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{ IDLE
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, READ
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} rState;
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enum bit [2:0]
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{ IDLE
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, WRITE
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} wState;
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always_ff @(posedge i_aClk)
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if (!i_aResetn) begin
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o_arReady <= '0;
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o_rValid <= '0;
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o_rData <= '0;
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o_rResp <= '0;
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end else
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case (rState)
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IDLE: begin
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if (i_arValid) begin
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o_arReady <= '1;
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o_rValid <= '1;
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o_rData <= mem[i_arAddr];
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o_rResp <= Response'(OKAY);
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rState <= READ;
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end else
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rState <= IDLE;
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end
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READ: begin
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o_arReady <= '0;
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if (i_rReady) begin
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o_rValid <= '0;
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o_rData <= '0;
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o_rResp <= '0;
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rState <= IDLE;
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end else
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rState <= READ;
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end
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default: begin
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o_arReady <= '0;
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o_rValid <= '0;
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o_rData <= '0;
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o_rResp <= '0;
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end
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endcase
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always_ff @(posedge i_aClk)
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if (!i_aResetn) begin
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o_awReady <= '0;
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o_wReady <= '0;
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o_bValid <= '0;
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o_bResp <= '0;
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end else
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case (wState)
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IDLE: begin
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if (i_awValid && i_wValid) begin
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o_awReady <= '1;
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mem[i_awAddr] <= wDataStrb;
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o_wReady <= '1;
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o_bValid <= '1;
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o_bResp <= Response'(OKAY);
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wState <= WRITE;
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end else
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wState <= IDLE;
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end
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WRITE: begin
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o_awReady <= '0;
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o_wReady <= '0;
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if (i_bReady) begin
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o_bValid <= '0;
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o_bResp <= '0;
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wState <= IDLE;
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end else
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wState <= WRITE;
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end
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default: begin
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o_awReady <= '0;
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o_wReady <= '0;
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o_bValid <= '0;
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o_bResp <= '0;
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end
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endcase
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endmodule
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`resetall
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