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41 lines
1.5 KiB
Systemverilog
41 lines
1.5 KiB
Systemverilog
// Driver module for use with AXI4-Lite bus, with exported DPI-C functions
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// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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module Axi4LiteDriver
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#(parameter int AWIDTH = 12 // Default: 4KB, [1:0] ignored = word aligned accesses
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, parameter int DWIDTH = 32 // AXI4-Lite Data bus is 32/64 bit only
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, parameter int SWIDTH = DWIDTH / 8 // Strobe width = data width / 8
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)(input var logic i_aClk
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, input var logic i_aResetn
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// Read Address Channel (Master -> Slave)
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, output var logic o_arValid
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, input var logic i_arReady
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, output var logic [AWIDTH-1:0] o_arAddr
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, output var Protection o_arProt
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// Read Data Channel (Slave -> Master)
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, input var logic i_rValid
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, output var logic o_rReady
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, input var logic [DWIDTH-1:0] i_rData
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, input var Response i_rResp
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// Write Address Channel (Master -> Slave)
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, output var logic o_awValid
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, input var logic i_awReady
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, output var logic [AWIDTH-1:0] o_awAddr
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, output var Protection o_awProt
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// Write Data Channel (Master -> Slave)
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, output var logic o_wValid
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, input var logic i_wReady
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, output var logic [DWIDTH-1:0] o_wData
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, output var logic [SWIDTH-1:0] o_wStrb
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// Write Response Channel (Slave -> Master)
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, input var logic i_bValid
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, output var logic o_bReady
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, input var Response i_bResp
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);
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endmodule
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`resetall
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