mirror of
https://github.com/supleed2/ELEC70056-HSV-CW2.git
synced 2024-12-22 21:55:48 +00:00
Increase covergroups and test inputs for VGA, Integrate gpio checker in tb
This commit is contained in:
parent
f586cd95d9
commit
aabd220e6a
17
Makefile
Normal file
17
Makefile
Normal file
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@ -0,0 +1,17 @@
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gpio:
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vlog -work work +acc=blnr +cover -noincr -timescale 1ns/1ps rtl/**/*.sv tbench/*.sv
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vopt -work work ahb_gpio_tb -o work_opt
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vsim -coverage work_opt -do setup.do -l sim.log
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vga:
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vlog -work work +acc=blnr +cover -noincr -timescale 1ns/1ps rtl/**/*.sv tbench/*.sv
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vopt -work work ahb_vga_tb -o work_opt
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vsim -coverage work_opt -do setup.do -l sim.log
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sys:
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vlog -work work +acc=blnr -noincr -timescale 1ns/1ps rtl/**/*.sv tbench/*.sv
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vopt -work work ahblite_sys_tb -o work_opt
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vsim work_opt -do setup.do -l sim.log
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# jg:
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# jg rtl/AHB_GPIO/AHBGPIO.tcl
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@ -114,46 +114,46 @@ module AHBGPIO
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//check behaviour
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//check behaviour
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assert_parity: assert property
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// assert_parity: assert property
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( @(posedge HCLK) disable iff (!HRESETn)
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// ( @(posedge HCLK) disable iff (!HRESETn)
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!PARITYERR
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// !PARITYERR
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);
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// );
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assert_gpio_write: assert property
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// assert_gpio_write: assert property
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( @(posedge HCLK) disable iff (!HRESETn)
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// ( @(posedge HCLK) disable iff (!HRESETn)
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((HADDR[7:0] == gpio_data_addr)
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// ((HADDR[7:0] == gpio_data_addr)
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&& HSEL
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// && HSEL
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&& HWRITE
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// && HWRITE
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&& HTRANS[1]
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// && HTRANS[1]
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&& HREADY) |-> ##1
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// && HREADY) |-> ##1
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(gpio_dir == 16'h0001) |-> ##1
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// (gpio_dir == 16'h0001) |-> ##1
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(GPIOOUT[15:0] == $past(HWDATA[15:0], 1))
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// (GPIOOUT[15:0] == $past(HWDATA[15:0], 1))
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);
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// );
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assert_gpio_read: assert property
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// assert_gpio_read: assert property
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( @(posedge HCLK) disable iff (!HRESETn)
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// ( @(posedge HCLK) disable iff (!HRESETn)
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((gpio_dir == 16'h0000)
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// ((gpio_dir == 16'h0000)
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&& (HADDR[7:0] == gpio_data_addr)
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// && (HADDR[7:0] == gpio_data_addr)
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// && HSEL // HSEL not used in Read always_ff
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// // && HSEL // HSEL not used in Read always_ff
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&& !HWRITE
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// && !HWRITE
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&& HTRANS[1]
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// && HTRANS[1]
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&& HREADY) |-> ##1
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// && HREADY) |-> ##1
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((HRDATA[15:0]==$past(GPIOIN[15:0],1)) && HREADYOUT)
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// ((HRDATA[15:0]==$past(GPIOIN[15:0],1)) && HREADYOUT)
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);
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// );
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assert_gpio_dir: assert property
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// assert_gpio_dir: assert property
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( @(posedge HCLK) disable iff (!HRESETn)
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// ( @(posedge HCLK) disable iff (!HRESETn)
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((HADDR[7:0] == gpio_dir_addr)
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// ((HADDR[7:0] == gpio_dir_addr)
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&& HSEL
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// && HSEL
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&& HWRITE
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// && HWRITE
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&& HTRANS[1]
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// && HTRANS[1]
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&& HREADY) |-> ##1
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// && HREADY) |-> ##1
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((HWDATA[7:0] == 8'h00 || HWDATA[7:0] == 8'h01)) ##1 (gpio_dir == $past(HWDATA[15:0], 1))
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// ((HWDATA[7:0] == 8'h00 || HWDATA[7:0] == 8'h01)) ##1 (gpio_dir == $past(HWDATA[15:0], 1))
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);
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// );
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assume_initial_valid: assume property
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// assume_initial_valid: assume property
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( @(posedge HCLK)
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// ( @(posedge HCLK)
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gpio_dir == 16'h0000
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// gpio_dir == 16'h0000
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|| gpio_dir == 16'h0001
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// || gpio_dir == 16'h0001
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);
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// );
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endmodule
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endmodule
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@ -8,8 +8,6 @@ module ahb_gpio_checker
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, input wire HSEL
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, input wire HSEL
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, input wire HREADY
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, input wire HREADY
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, input wire [16:0] GPIOIN
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, input wire [16:0] GPIOIN
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, input wire PARITYSEL
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, input wire INJECT_FAULT
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, input wire HREADYOUT
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, input wire HREADYOUT
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, input wire [31:0] HRDATA
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, input wire [31:0] HRDATA
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, input wire [16:0] GPIOOUT
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, input wire [16:0] GPIOOUT
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@ -27,15 +25,15 @@ module ahb_gpio_checker
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@(posedge HCLK) disable iff (!HRESETn)
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@(posedge HCLK) disable iff (!HRESETn)
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(HADDR[7:0] == gpio_data_addr) && gpio_cmd
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(HADDR[7:0] == gpio_data_addr) && gpio_cmd
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##1
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##1
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(gpio_dir=='1)
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(gpio_dir=='1) |->
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##1
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##1
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(GPIOOUT[15:0] == $past(HWDATA,1));
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(GPIOOUT[15:0] == $past(HWDATA[15:0],1));
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endproperty
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endproperty
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property gpio_read;
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property gpio_read;
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@(posedge HCLK) disable iff (!HRESETn)
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@(posedge HCLK) disable iff (!HRESETn)
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(HADDR[7:0] == gpio_data_addr) && gpio_cmd
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(HADDR[7:0] == gpio_data_addr) && gpio_cmd
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&& (gpio_dir=='0)
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&& (gpio_dir=='0) |->
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##1
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##1
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((HRDATA[15:0]==$past(GPIOIN[15:0],1)) && HREADYOUT);
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((HRDATA[15:0]==$past(GPIOIN[15:0],1)) && HREADYOUT);
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endproperty
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endproperty
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@ -3,7 +3,7 @@
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// //
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// //
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//Copyright (c) 2012, ARM All rights reserved. //
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//Copyright (c) 2012, ARM All rights reserved. //
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// //
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// //
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//THIS END USER LICENCE AGREEMENT (<EFBFBD>LICENCE<EFBFBD>) IS A LEGAL AGREEMENT BETWEEN //
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//THIS END USER LICENCE AGREEMENT (“LICENCE”) IS A LEGAL AGREEMENT BETWEEN //
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//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
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//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
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//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
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//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
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//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
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//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
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@ -34,20 +34,23 @@
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// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
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// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module AHBVGA
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( input wire HCLK
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module AHBVGA(
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, input wire HRESETn
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input wire HCLK,
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, input wire [31:0] HADDR
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input wire HRESETn,
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, input wire [31:0] HWDATA
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input wire [31:0] HADDR,
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, input wire HREADY
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input wire [31:0] HWDATA,
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, input wire HWRITE
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input wire HREADY,
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, input wire [1:0] HTRANS
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input wire HWRITE,
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, input wire HSEL
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input wire [1:0] HTRANS,
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, output wire [31:0] HRDATA
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input wire HSEL,
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, output wire HREADYOUT
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, output wire HSYNC
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output wire [31:0] HRDATA,
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, output wire VSYNC
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output wire HREADYOUT,
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, output wire [7:0] RGB
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output wire HSYNC,
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output wire VSYNC,
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output wire [7:0] RGB
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);
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);
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//Register locations
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//Register locations
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localparam IMAGEADDR = 4'hA;
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localparam IMAGEADDR = 4'hA;
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@ -76,8 +79,10 @@ module AHBVGA
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wire sel_image;
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wire sel_image;
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reg [7:0] cin;
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reg [7:0] cin;
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always_ff @(posedge HCLK)
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if(HREADY) begin
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always @(posedge HCLK)
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if(HREADY)
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begin
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last_HADDR <= HADDR;
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last_HADDR <= HADDR;
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last_HWRITE <= HWRITE;
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last_HWRITE <= HWRITE;
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last_HSEL <= HSEL;
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last_HSEL <= HSEL;
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@ -88,71 +93,87 @@ module AHBVGA
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assign HREADYOUT = ~scroll;
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assign HREADYOUT = ~scroll;
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//VGA interface: control the synchronization and color signals for a particular resolution
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//VGA interface: control the synchronization and color signals for a particular resolution
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VGAInterface uVGAInterface
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VGAInterface uVGAInterface (
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( .CLK (HCLK)
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.CLK(HCLK),
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, .COLOUR_IN (cin)
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.resetn(HRESETn),
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, .cout (RGB)
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.COLOUR_IN(cin),
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, .hs (HSYNC)
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.cout(RGB),
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, .vs (VSYNC)
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.hs(HSYNC),
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, .addrh (pixel_x)
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.vs(VSYNC),
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, .addrv (pixel_y)
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.addrh(pixel_x),
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.addrv(pixel_y)
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);
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);
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//VGA console module: output the pixels in the text region
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//VGA console module: output the pixels in the text region
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vga_console uvga_console
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vga_console uvga_console(
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( .clk (HCLK)
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.clk(HCLK),
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, .resetn (HRESETn)
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.resetn(HRESETn),
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, .pixel_x (pixel_x)
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.pixel_x(pixel_x),
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, .pixel_y (pixel_y)
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.pixel_y(pixel_y),
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, .text_rgb (console_rgb)
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.text_rgb(console_rgb),
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, .font_we (console_write)
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.font_we(console_write),
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, .font_data (console_wdata)
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.font_data(console_wdata),
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, .scroll (scroll)
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.scroll(scroll)
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);
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);
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//VGA image buffer: output the pixels in the image region
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//VGA image buffer: output the pixels in the image region
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vga_image uvga_image
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vga_image uvga_image(
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( .clk (HCLK)
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.clk(HCLK),
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, .resetn (HRESETn)
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.resetn(HRESETn),
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, .address (last_HADDR[15:2])
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.address(last_HADDR[15:2]),
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, .pixel_x (pixel_x)
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.pixel_x(pixel_x),
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, .pixel_y (pixel_y)
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.pixel_y(pixel_y),
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, .image_we (image_write)
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.image_we(image_write),
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, .image_data (image_wdata)
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.image_data(image_wdata),
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, .image_rgb (image_rgb)
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.image_rgb(image_rgb)
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);
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);
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assign sel_console = (last_HADDR[23:0]== 12'h000000000000);
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assign sel_console = (last_HADDR[23:0]== 12'h000000000000);
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assign sel_image = (last_HADDR[23:0] != 12'h000000000000);
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assign sel_image = (last_HADDR[23:0] != 12'h000000000000);
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//Set console write and write data
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//Set console write and write data
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always_ff @(posedge HCLK, negedge HRESETn)
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always @(posedge HCLK, negedge HRESETn)
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if(!HRESETn) begin
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begin
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if(!HRESETn)
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begin
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console_write <= 0;
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console_write <= 0;
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console_wdata <= 0;
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console_wdata <= 0;
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end else if (last_HWRITE & last_HSEL & last_HTRANS[1] & HREADYOUT & sel_console) begin
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end
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else if(last_HWRITE & last_HSEL & last_HTRANS[1] & HREADYOUT & sel_console)
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begin
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console_write <= 1'b1;
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console_write <= 1'b1;
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console_wdata <= HWDATA[7:0];
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console_wdata <= HWDATA[7:0];
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end else begin
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end
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else
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begin
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console_write <= 1'b0;
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console_write <= 1'b0;
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console_wdata <= 0;
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console_wdata <= 0;
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end
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end
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end
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//Set image write and image write data
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//Set image write and image write data
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always_ff @(posedge HCLK, negedge HRESETn)
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always @(posedge HCLK, negedge HRESETn)
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if(!HRESETn) begin
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begin
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if(!HRESETn)
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begin
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image_write <= 0;
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image_write <= 0;
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image_wdata <= 0;
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image_wdata <= 0;
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end else if(last_HWRITE & last_HSEL & last_HTRANS[1] & HREADYOUT & sel_image) begin
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end
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else if(last_HWRITE & last_HSEL & last_HTRANS[1] & HREADYOUT & sel_image)
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begin
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image_write <= 1'b1;
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image_write <= 1'b1;
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image_wdata <= HWDATA[7:0];
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image_wdata <= HWDATA[7:0];
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end else begin
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end
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else
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begin
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image_write <= 1'b0;
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image_write <= 1'b0;
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image_wdata <= 0;
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image_wdata <= 0;
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end
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end
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end
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//Select the rgb color for a particular region
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//Select the rgb color for a particular region
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always_comb
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always @*
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begin
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if(!HRESETn)
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if(!HRESETn)
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cin <= 8'h00;
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cin <= 8'h00;
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else
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else
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@ -160,6 +181,7 @@ module AHBVGA
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cin <= console_rgb ;
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cin <= console_rgb ;
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else
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else
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cin <= image_rgb;
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cin <= image_rgb;
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end
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endmodule
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endmodule
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@ -62,6 +62,7 @@ module ahb_vgasys_checker(
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begin
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begin
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pixel_x <= 0;
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pixel_x <= 0;
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pixel_y <= 0;
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pixel_y <= 0;
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if(!HRESETn)
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console_text_reg <= "";
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console_text_reg <= "";
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counter <= 0;
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counter <= 0;
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countup <= 0;
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countup <= 0;
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@ -39,6 +39,7 @@ module ahb_gpio_tb;
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localparam max_test_count = 1000;
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localparam max_test_count = 1000;
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logic parity_sel = '0;
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logic parity_sel = '0;
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logic parity_err;
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integer test_count;
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integer test_count;
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ahb_gpio_if gpioif();
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ahb_gpio_if gpioif();
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@ -57,7 +58,23 @@ module ahb_gpio_tb;
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.HREADYOUT (gpioif.HREADYOUT),
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.HREADYOUT (gpioif.HREADYOUT),
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.HRDATA (gpioif.HRDATA),
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.HRDATA (gpioif.HRDATA),
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.GPIOOUT (gpioif.GPIOOUT),
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.GPIOOUT (gpioif.GPIOOUT),
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.PARITYERR ()
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.PARITYERR (parity_err)
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);
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ahb_gpio_checker gpio_checker(
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.HCLK (gpioif.HCLK),
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.HRESETn (gpioif.HRESETn),
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.HADDR (gpioif.HADDR),
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.HTRANS (gpioif.HTRANS),
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.HWDATA (gpioif.HWDATA),
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.HWRITE (gpioif.HWRITE),
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.HSEL (gpioif.HSEL),
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.HREADY (gpioif.HREADY),
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.GPIOIN (gpioif.GPIOIN),
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.HREADYOUT (gpioif.HREADYOUT),
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.HRDATA (gpioif.HRDATA),
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.GPIOOUT (gpioif.GPIOOUT),
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.PARITYERR (parity_err)
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);
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);
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class gpio_stimulus;
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class gpio_stimulus;
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@ -121,20 +138,20 @@ module ahb_gpio_tb;
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|
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endgroup
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endgroup
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|
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covergroup cover_ahb_write_values;
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covergroup cover_hwdata_values;
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coverpoint gpioif.HWDATA;
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coverpoint gpioif.HWDATA;
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endgroup
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endgroup
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covergroup cover_ahb_read_values;
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covergroup cover_hrdata_values;
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coverpoint gpioif.HRDATA;
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coverpoint gpioif.HRDATA[15:0];
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endgroup
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endgroup
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|
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covergroup cover_gpio_in_values;
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covergroup cover_gpio_in_values;
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coverpoint gpioif.GPIOIN;
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coverpoint gpioif.GPIOIN[15:0];
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endgroup
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endgroup
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||||||
covergroup cover_gpio_out_values;
|
covergroup cover_gpio_out_values;
|
||||||
coverpoint gpioif.GPIOOUT;
|
coverpoint gpioif.GPIOOUT[15:0];
|
||||||
endgroup
|
endgroup
|
||||||
|
|
||||||
task deassert_reset();
|
task deassert_reset();
|
||||||
|
@ -147,13 +164,13 @@ module ahb_gpio_tb;
|
||||||
endtask
|
endtask
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
cover_ahb_write_values covahbwrite;
|
cover_hwdata_values covhwdata;
|
||||||
cover_ahb_read_values covahbread;
|
cover_hrdata_values covhrdata;
|
||||||
cover_gpio_in_values covgpioin;
|
cover_gpio_in_values covgpioin;
|
||||||
cover_gpio_out_values covgpioout;
|
cover_gpio_out_values covgpioout;
|
||||||
cover_ahb_transaction_vals covahbtransactionvals;
|
cover_ahb_transaction_vals covahbtransactionvals;
|
||||||
covahbwrite = new();
|
covhwdata = new();
|
||||||
covahbread = new();
|
covhrdata = new();
|
||||||
covgpioin = new();
|
covgpioin = new();
|
||||||
covgpioout = new();
|
covgpioout = new();
|
||||||
covahbtransactionvals = new();
|
covahbtransactionvals = new();
|
||||||
|
@ -171,9 +188,9 @@ module ahb_gpio_tb;
|
||||||
gpioif.HADDR = stimulus_vals.HADDR;
|
gpioif.HADDR = stimulus_vals.HADDR;
|
||||||
gpioif.GPIOIN = stimulus_vals.GPIOIN;
|
gpioif.GPIOIN = stimulus_vals.GPIOIN;
|
||||||
|
|
||||||
covahbwrite.sample();
|
covhwdata.sample();
|
||||||
covgpioin.sample();
|
covgpioin.sample();
|
||||||
covahbread.sample();
|
covhrdata.sample();
|
||||||
covgpioout.sample();
|
covgpioout.sample();
|
||||||
|
|
||||||
covahbtransactionvals.sample();
|
covahbtransactionvals.sample();
|
||||||
|
|
|
@ -76,7 +76,7 @@ module ahb_vga_tb;
|
||||||
);
|
);
|
||||||
|
|
||||||
logic display_enable;
|
logic display_enable;
|
||||||
|
integer reset_time;
|
||||||
task deassert_reset();
|
task deassert_reset();
|
||||||
begin
|
begin
|
||||||
vgaif.HRESETn = 0;
|
vgaif.HRESETn = 0;
|
||||||
|
@ -118,7 +118,7 @@ module ahb_vga_tb;
|
||||||
endtask
|
endtask
|
||||||
|
|
||||||
class vga_stimulus;
|
class vga_stimulus;
|
||||||
rand logic [31:0] HWDATA;
|
randc logic [31:0] HWDATA;
|
||||||
|
|
||||||
constraint c_hwdata
|
constraint c_hwdata
|
||||||
{0 <= HWDATA; HWDATA <= 8'h7f;}
|
{0 <= HWDATA; HWDATA <= 8'h7f;}
|
||||||
|
@ -128,32 +128,40 @@ module ahb_vga_tb;
|
||||||
|
|
||||||
covergroup cover_vga_chars;
|
covergroup cover_vga_chars;
|
||||||
cp_hwdata: coverpoint vgaif.HWDATA{
|
cp_hwdata: coverpoint vgaif.HWDATA{
|
||||||
bins invalid = {[128:255]};
|
bins lo_1 = {[0:15]};
|
||||||
option.auto_bin_max = 128;
|
bins lo_2 = {[16:31]};
|
||||||
|
bins mid_1 = {[32:47]};
|
||||||
|
bins mid_2 = {[48:63]};
|
||||||
|
bins mid_3 = {[64:79]};
|
||||||
|
bins mid_4 = {[80:95]};
|
||||||
|
bins hi_1 = {[96:111]};
|
||||||
|
bins hi_2 = {[112:127]};
|
||||||
}
|
}
|
||||||
endgroup
|
endgroup
|
||||||
|
|
||||||
|
|
||||||
integer char_index;
|
integer char_index;
|
||||||
string test_value = "";
|
string test_value = "";
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
cover_vga_chars covvgachars;
|
cover_vga_chars covvgachars;
|
||||||
covvgachars = new();
|
covvgachars = new();
|
||||||
stimulus_vals = new();
|
stimulus_vals = new();
|
||||||
deassert_reset();
|
|
||||||
display_enable = 0;
|
display_enable = 0;
|
||||||
|
deassert_reset();
|
||||||
|
display_enable = 1;
|
||||||
|
test_value = "";
|
||||||
@(posedge vgaif.VSYNC);
|
@(posedge vgaif.VSYNC);
|
||||||
display_enable = 1;
|
display_enable = 1;
|
||||||
$display(test_value);
|
$display(test_value);
|
||||||
for(char_index = 0; char_index < 16; char_index++)
|
for(char_index = 0; char_index < 30; char_index++)
|
||||||
begin
|
begin
|
||||||
|
|
||||||
assert (stimulus_vals.randomize) else $fatal;
|
assert (stimulus_vals.randomize) else $fatal;
|
||||||
setChar(stimulus_vals.HWDATA);
|
setChar(stimulus_vals.HWDATA);
|
||||||
|
covvgachars.sample();
|
||||||
test_value = {test_value, font_map[stimulus_vals.HWDATA]};
|
test_value = {test_value, font_map[stimulus_vals.HWDATA]};
|
||||||
end
|
end
|
||||||
setChar(8'h08);
|
// setChar(8'h08);
|
||||||
// setChar(8'h54);
|
// setChar(8'h54);
|
||||||
// setChar(8'h45);
|
// setChar(8'h45);
|
||||||
// setChar(8'h53);
|
// setChar(8'h53);
|
||||||
|
|
Loading…
Reference in a new issue