mirror of
https://github.com/supleed2/ELEC70056-HSV-CW2.git
synced 2024-11-10 02:15:47 +00:00
Format top tb and add vga image buffer reset task
This commit is contained in:
parent
f586cd95d9
commit
9c9536016b
|
@ -1,31 +1,32 @@
|
||||||
`timescale 1ns/1ps
|
`timescale 1ns/1ps
|
||||||
module ahblite_sys_tb(
|
module ahblite_sys_tb();
|
||||||
|
reg RESET, CLK;
|
||||||
|
wire [7:0] LED;
|
||||||
|
AHBLITE_SYS dut(.CLK(CLK), .RESET(RESET), .LED(LED));
|
||||||
|
// Note: you can modify this to give a 50MHz clock or whatever is appropriate
|
||||||
|
|
||||||
);
|
task resetVgaImageBuffers;
|
||||||
|
for (int i = 0; i < (2**dut.uAHBVGA.uvga_image.uimage_ram.ADDR_WIDTH)-1; i++) begin
|
||||||
|
dut.uAHBVGA.uvga_image.uimage_ram.ram[i] = '0;
|
||||||
|
end
|
||||||
|
for (int i = 0; i < (2**dut.uAHBVGA2.uvga_image.uimage_ram.ADDR_WIDTH)-1; i++) begin
|
||||||
|
dut.uAHBVGA2.uvga_image.uimage_ram.ram[i] = '0;
|
||||||
|
end
|
||||||
|
endtask
|
||||||
|
|
||||||
reg RESET, CLK;
|
initial begin
|
||||||
wire [7:0] LED;
|
|
||||||
|
|
||||||
AHBLITE_SYS dut(.CLK(CLK), .RESET(RESET), .LED(LED));
|
|
||||||
|
|
||||||
// Note: you can modify this to give a 50MHz clock or whatever is appropriate
|
|
||||||
|
|
||||||
initial
|
|
||||||
begin
|
|
||||||
CLK=0;
|
CLK=0;
|
||||||
forever
|
forever begin
|
||||||
begin
|
|
||||||
#5 CLK=1;
|
#5 CLK=1;
|
||||||
#5 CLK=0;
|
#5 CLK=0;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
initial
|
initial begin
|
||||||
begin
|
resetVgaImageBuffers();
|
||||||
RESET=0;
|
RESET=0;
|
||||||
#30 RESET=1;
|
#30 RESET=1;
|
||||||
#20 RESET=0;
|
#20 RESET=0;
|
||||||
end
|
end
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue