diff --git a/tbench/ahblite_sys_tb.sv b/tbench/ahblite_sys_tb.sv
index b7d7ca4..726648a 100644
--- a/tbench/ahblite_sys_tb.sv
+++ b/tbench/ahblite_sys_tb.sv
@@ -1,31 +1,32 @@
 `timescale 1ns/1ps
-module ahblite_sys_tb(
+module ahblite_sys_tb();
+  reg RESET, CLK;
+  wire [7:0] LED;
+  AHBLITE_SYS dut(.CLK(CLK), .RESET(RESET), .LED(LED));
+  // Note: you can modify this to give a 50MHz clock or whatever is appropriate
 
-);
+  task resetVgaImageBuffers;
+    for (int i = 0; i < (2**dut.uAHBVGA.uvga_image.uimage_ram.ADDR_WIDTH)-1; i++) begin
+      dut.uAHBVGA.uvga_image.uimage_ram.ram[i] = '0;
+    end
+    for (int i = 0; i < (2**dut.uAHBVGA2.uvga_image.uimage_ram.ADDR_WIDTH)-1; i++) begin
+      dut.uAHBVGA2.uvga_image.uimage_ram.ram[i] = '0;
+    end
+  endtask
 
-reg RESET, CLK;
-wire [7:0] LED;
-
-AHBLITE_SYS dut(.CLK(CLK), .RESET(RESET), .LED(LED));
-
-// Note: you can modify this to give a 50MHz clock or whatever is appropriate
-
-initial
-begin
-   CLK=0;
-   forever
-   begin
+  initial begin
+    CLK=0;
+    forever begin
       #5 CLK=1;
       #5 CLK=0;
-   end
-end
-
-initial
-begin
-   RESET=0;
-   #30 RESET=1;
-   #20 RESET=0;
-end
+    end
+  end
 
+  initial begin
+    resetVgaImageBuffers();
+    RESET=0;
+    #30 RESET=1;
+    #20 RESET=0;
+  end
 endmodule