mirror of
https://github.com/supleed2/ELEC60011-DSD-CW.git
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142 lines
7.1 KiB
Plaintext
142 lines
7.1 KiB
Plaintext
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2012 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 32-bit
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# Version 12.0 Build 178 05/31/2012 SJ Full Version
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# Date created = 12:12:59 November 25, 2012
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# hello_world_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone V"
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set_global_assignment -name DEVICE 5CSEMA5F31C6
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set_global_assignment -name TOP_LEVEL_ENTITY hello_world
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:12:59 NOVEMBER 25, 2012"
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set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING ON
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set_global_assignment -name BOARD "DE1-SoC Board"
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set_location_assignment PIN_AF14 -to iCLK_50
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set_location_assignment PIN_AK6 -to DRAM_DQ[0]
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set_location_assignment PIN_AJ7 -to DRAM_DQ[1]
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set_location_assignment PIN_AJ9 -to DRAM_DQ[10]
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set_location_assignment PIN_AH9 -to DRAM_DQ[11]
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set_location_assignment PIN_AH8 -to DRAM_DQ[12]
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set_location_assignment PIN_AH7 -to DRAM_DQ[13]
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set_location_assignment PIN_AJ6 -to DRAM_DQ[14]
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set_location_assignment PIN_AJ5 -to DRAM_DQ[15]
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set_location_assignment PIN_AK7 -to DRAM_DQ[2]
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set_location_assignment PIN_AK8 -to DRAM_DQ[3]
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set_location_assignment PIN_AK9 -to DRAM_DQ[4]
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set_location_assignment PIN_AG10 -to DRAM_DQ[5]
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set_location_assignment PIN_AK11 -to DRAM_DQ[6]
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set_location_assignment PIN_AJ11 -to DRAM_DQ[7]
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set_location_assignment PIN_AH10 -to DRAM_DQ[8]
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set_location_assignment PIN_AJ10 -to DRAM_DQ[9]
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set_location_assignment PIN_V16 -to oLEDG[0]
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set_location_assignment PIN_W16 -to oLEDG[1]
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set_location_assignment PIN_V17 -to oLEDG[2]
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set_location_assignment PIN_V18 -to oLEDG[3]
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set_location_assignment PIN_W17 -to oLEDG[4]
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set_location_assignment PIN_W19 -to oLEDG[5]
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set_location_assignment PIN_Y19 -to oLEDG[6]
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set_location_assignment PIN_W20 -to oLEDG[7]
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set_location_assignment PIN_AJ12 -to oDRAM_BA[1]
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set_location_assignment PIN_AF13 -to oDRAM_BA[0]
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set_location_assignment PIN_AF11 -to oDRAM_CAS_N
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set_location_assignment PIN_AK13 -to oDRAM_CKE
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set_location_assignment PIN_AH12 -to oDRAM_CLK
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set_location_assignment PIN_AG11 -to oDRAM_CS_N
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set_location_assignment PIN_AE13 -to oDRAM_RAS_N
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set_location_assignment PIN_AA13 -to oDRAM_WE_N
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set_location_assignment PIN_AJ14 -to oDRAM_A[12]
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set_location_assignment PIN_AH13 -to oDRAM_A[11]
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set_location_assignment PIN_AG12 -to oDRAM_A[10]
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set_location_assignment PIN_AG13 -to oDRAM_A[9]
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set_location_assignment PIN_AH15 -to oDRAM_A[8]
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set_location_assignment PIN_AF15 -to oDRAM_A[7]
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set_location_assignment PIN_AD14 -to oDRAM_A[6]
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set_location_assignment PIN_AC14 -to oDRAM_A[5]
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set_location_assignment PIN_AB15 -to oDRAM_A[4]
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set_location_assignment PIN_AE14 -to oDRAM_A[3]
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set_location_assignment PIN_AG15 -to oDRAM_A[2]
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set_location_assignment PIN_AH14 -to oDRAM_A[1]
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set_location_assignment PIN_AK14 -to oDRAM_A[0]
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set_location_assignment PIN_AK12 -to oDRAM_DQM[1]
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set_location_assignment PIN_AB13 -to oDRAM_DQM[0]
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name SEARCH_PATH "c:\\users\\suple\\desktop\\dsd-cw\\system_template_de1_soc"
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set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
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set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id adder_tb
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set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME adder_tb -section_id adder_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE adder_tb.sv -section_id adder_tb
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set_global_assignment -name BDF_FILE fullfunction.bdf
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set_global_assignment -name BDF_FILE fullfunction_t.bdf
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set_global_assignment -name VERILOG_FILE fp_div2.v
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set_global_assignment -name VERILOG_FILE fp_div128.v
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set_global_assignment -name VERILOG_FILE cordic.v
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set_global_assignment -name VERILOG_FILE cordic_t.v
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set_global_assignment -name QSYS_FILE first_nios2_system.qsys
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set_global_assignment -name SDC_FILE hw_dev_tutorial.sdc
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set_global_assignment -name BDF_FILE hello_world.bdf
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set_global_assignment -name QIP_FILE pll.qip
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set_global_assignment -name SIP_FILE pll.sip
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set_global_assignment -name QIP_FILE fp_add.qip
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set_global_assignment -name QIP_FILE fp_sub.qip
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set_global_assignment -name SIP_FILE fp_sub.sip
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set_global_assignment -name QIP_FILE fp_mul.qip
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set_global_assignment -name SIP_FILE fp_mul.sip
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set_global_assignment -name QIP_FILE fp_to_fix.qip
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set_global_assignment -name SIP_FILE fp_to_fix.sip
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set_global_assignment -name QIP_FILE fix_to_fp.qip
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set_global_assignment -name SIP_FILE fix_to_fp.sip
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set_global_assignment -name VERILOG_FILE const128.v
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set_global_assignment -name BDF_FILE dualfunction.bdf
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name BDF_FILE dualfunction_t.bdf
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set_global_assignment -name QIP_FILE fp_sum.qip
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set_global_assignment -name SIP_FILE fp_sum.sip
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |