# -------------------------------------------------------------------------- # # # Copyright (C) 1991-2012 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 32-bit # Version 12.0 Build 178 05/31/2012 SJ Full Version # Date created = 12:12:59 November 25, 2012 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # hello_world_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "Cyclone V" set_global_assignment -name DEVICE 5CSEMA5F31C6 set_global_assignment -name TOP_LEVEL_ENTITY hello_world set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:12:59 NOVEMBER 25, 2012" set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING ON set_global_assignment -name BOARD "DE1-SoC Board" set_location_assignment PIN_AF14 -to iCLK_50 set_location_assignment PIN_AK6 -to DRAM_DQ[0] set_location_assignment PIN_AJ7 -to DRAM_DQ[1] set_location_assignment PIN_AJ9 -to DRAM_DQ[10] set_location_assignment PIN_AH9 -to DRAM_DQ[11] set_location_assignment PIN_AH8 -to DRAM_DQ[12] set_location_assignment PIN_AH7 -to DRAM_DQ[13] set_location_assignment PIN_AJ6 -to DRAM_DQ[14] set_location_assignment PIN_AJ5 -to DRAM_DQ[15] set_location_assignment PIN_AK7 -to DRAM_DQ[2] set_location_assignment PIN_AK8 -to DRAM_DQ[3] set_location_assignment PIN_AK9 -to DRAM_DQ[4] set_location_assignment PIN_AG10 -to DRAM_DQ[5] set_location_assignment PIN_AK11 -to DRAM_DQ[6] set_location_assignment PIN_AJ11 -to DRAM_DQ[7] set_location_assignment PIN_AH10 -to DRAM_DQ[8] set_location_assignment PIN_AJ10 -to DRAM_DQ[9] set_location_assignment PIN_V16 -to oLEDG[0] set_location_assignment PIN_W16 -to oLEDG[1] set_location_assignment PIN_V17 -to oLEDG[2] set_location_assignment PIN_V18 -to oLEDG[3] set_location_assignment PIN_W17 -to oLEDG[4] set_location_assignment PIN_W19 -to oLEDG[5] set_location_assignment PIN_Y19 -to oLEDG[6] set_location_assignment PIN_W20 -to oLEDG[7] set_location_assignment PIN_AJ12 -to oDRAM_BA[1] set_location_assignment PIN_AF13 -to oDRAM_BA[0] set_location_assignment PIN_AF11 -to oDRAM_CAS_N set_location_assignment PIN_AK13 -to oDRAM_CKE set_location_assignment PIN_AH12 -to oDRAM_CLK set_location_assignment PIN_AG11 -to oDRAM_CS_N set_location_assignment PIN_AE13 -to oDRAM_RAS_N set_location_assignment PIN_AA13 -to oDRAM_WE_N set_location_assignment PIN_AJ14 -to oDRAM_A[12] set_location_assignment PIN_AH13 -to oDRAM_A[11] set_location_assignment PIN_AG12 -to oDRAM_A[10] set_location_assignment PIN_AG13 -to oDRAM_A[9] set_location_assignment PIN_AH15 -to oDRAM_A[8] set_location_assignment PIN_AF15 -to oDRAM_A[7] set_location_assignment PIN_AD14 -to oDRAM_A[6] set_location_assignment PIN_AC14 -to oDRAM_A[5] set_location_assignment PIN_AB15 -to oDRAM_A[4] set_location_assignment PIN_AE14 -to oDRAM_A[3] set_location_assignment PIN_AG15 -to oDRAM_A[2] set_location_assignment PIN_AH14 -to oDRAM_A[1] set_location_assignment PIN_AK14 -to oDRAM_A[0] set_location_assignment PIN_AK12 -to oDRAM_DQM[1] set_location_assignment PIN_AB13 -to oDRAM_DQM[0] set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name SEARCH_PATH "c:\\users\\suple\\desktop\\dsd-cw\\system_template_de1_soc" set_global_assignment -name EDA_SIMULATION_TOOL "" set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id adder_tb set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME adder_tb -section_id adder_tb set_global_assignment -name EDA_TEST_BENCH_FILE adder_tb.sv -section_id adder_tb set_global_assignment -name BDF_FILE fullfunction.bdf set_global_assignment -name BDF_FILE fullfunction_t.bdf set_global_assignment -name VERILOG_FILE fp_div2.v set_global_assignment -name VERILOG_FILE fp_div128.v set_global_assignment -name VERILOG_FILE cordic.v set_global_assignment -name VERILOG_FILE cordic_t.v set_global_assignment -name QSYS_FILE first_nios2_system.qsys set_global_assignment -name SDC_FILE hw_dev_tutorial.sdc set_global_assignment -name BDF_FILE hello_world.bdf set_global_assignment -name QIP_FILE pll.qip set_global_assignment -name SIP_FILE pll.sip set_global_assignment -name QIP_FILE fp_add.qip set_global_assignment -name QIP_FILE fp_sub.qip set_global_assignment -name SIP_FILE fp_sub.sip set_global_assignment -name QIP_FILE fp_mul.qip set_global_assignment -name SIP_FILE fp_mul.sip set_global_assignment -name QIP_FILE fp_to_fix.qip set_global_assignment -name SIP_FILE fp_to_fix.sip set_global_assignment -name QIP_FILE fix_to_fp.qip set_global_assignment -name SIP_FILE fix_to_fp.sip set_global_assignment -name VERILOG_FILE const128.v set_global_assignment -name BDF_FILE dualfunction.bdf set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name BDF_FILE dualfunction_t.bdf set_global_assignment -name QIP_FILE fp_sum.qip set_global_assignment -name SIP_FILE fp_sum.sip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top