Task 1 & 2

Add source files and update to completed state at end of Task 2
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Aadi Desai 2022-01-30 17:18:39 +00:00
parent 94e215043a
commit 8ed2b5bc0e
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4 changed files with 633 additions and 2 deletions

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@ -4,9 +4,10 @@ import numpy as np
start = 0
stop = 255
step = 5
step = 1 / 1024
x = list(np.arange(start, stop, step)) + [stop]
acc = 0
for i in x:
acc += 0.5 * i + i * i * cos((i - 128) / 128)
# acc += 0.5 * i + i * i * cos((i - 128) / 128)
acc += i + i * i
print(acc.real)

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@ -0,0 +1,48 @@
#include <stdlib.h>
#include <sys/alt_stdio.h>
#include <sys/alt_alarm.h>
#include <sys/times.h>
#include <alt_types.h>
#include <system.h>
#include <stdio.h>
#include <unistd.h>
// test_case 1
#define step 5
#define N 52
// test_case 2
//#define step 1/8.0
//#define N 2041
//Test case 3
//#define step 1/1024.0
//#define N 261121
void generateVector(float x[N]){
int i;
x[0] = 0;
for (i=1; i<N; i++){
x[i] = x[i-1] + step;
}
}
float sumVector(float x[], int M){
float y = 0.0;
for(int i = 0; i < M; i++){
y += x[i] + x[i] * x[i];
}
return y;
}
int main()
{
float x[N];
float y;
generateVector(x);
clock_t exec_t1, exec_t2;
exec_t1 = times(NULL);
y = sumVector(x, N);
exec_t2 = times(NULL);
printf("T: %d, A: %d", (int)(exec_t2 - exec_t1), (int) y);
return 0;
}

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@ -0,0 +1,56 @@
`timescale 1 ns / 100 ps
module tb ();
//Inputs to DUT are reg type
reg [31:0] dataa;
reg [31:0] datab;
//Output from DUT is wire type
wire [31:0] result;
//Instantiate the DUT
//mul refers to the verilog module defined by the LPM_MULT ip
mul unit(
.dataa(dataa),
.datab(datab),
.result(result)
);
// ---- If a clock is required, see below ----
// //Create a 50MHz clock
// always
// #10 clk = ~clk;
// -----------------------
//Initial Block
initial
begin
$display($time, " << Starting Simulation >> ");
// intialise/set input
// clk = 1'b0;
// If using a clock
// @(posedge clk);
// Wait 10 cycles (corresponds to timescale at the top)
#10
// set dataa and datab
dataa <= 32'd1;
datab <= 32'd2;
#10
dataa <= 32'd332;
datab <= 32'd22;
#10
dataa <= 32'd2;
datab <= 32'd23;
#10
$display($time, "<< Simulation Complete >>");
$stop;
end
endmodule