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ELEC60011-DSD-CW/.gitignore

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Initial Commit Include Coursework PDF and basic test script for checking answer in Python
2022-01-25 16:48:03 +00:00
**
Add specific entries to .gitignore For Verilog and C source files within project
2022-01-30 17:17:51 +00:00
!system_template_de1_soc/
Initial Commit Include Coursework PDF and basic test script for checking answer in Python
2022-01-25 16:48:03 +00:00
!*.v
!*.qsys
Add specific entries to .gitignore For Verilog and C source files within project
2022-01-30 17:17:51 +00:00
!system_template_de1_soc/software/
!system_template_de1_soc/software/*
system_template_de1_soc/software/*_bsp
!system_template_de1_soc/software/*/*.c
Initial Commit Include Coursework PDF and basic test script for checking answer in Python
2022-01-25 16:48:03 +00:00
!DSD_coursework_DE1-SoC.pdf
!README.md
!Python/
!*.py
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