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ELEC60011-DSD-CW/system_template_de1_soc/first_nios2_system.qsys

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<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element clk_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element cpu
{
datum _sortIndex
{
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value = "1";
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type = "int";
}
}
element cpu.debug_mem_slave
{
datum baseAddress
{
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value = "16779264";
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type = "String";
}
}
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element first_nios2_system
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element first_nios2_system
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element first_nios2_system
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element first_nios2_system
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element first_nios2_system
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element first_nios2_system
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element first_nios2_system
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element first_nios2_system
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element first_nios2_system
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element fp_add
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{
datum _sortIndex
{
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value = "7";
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type = "int";
}
}
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element fp_mul
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{
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datum _sortIndex
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{
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value = "9";
type = "int";
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}
}
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element fp_sub
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{
datum _sortIndex
{
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value = "8";
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type = "int";
}
}
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element jtag_uart
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
element jtag_uart.avalon_jtag_slave
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{
datum baseAddress
{
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value = "16781368";
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type = "String";
}
}
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element led_pio
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{
datum _sortIndex
{
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value = "5";
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type = "int";
}
}
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element led_pio.s1
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{
datum baseAddress
{
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value = "16781344";
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type = "String";
}
}
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element sdram
{
datum _sortIndex
{
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value = "6";
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type = "int";
}
}
element sdram.s1
{
datum baseAddress
{
value = "8388608";
type = "String";
}
}
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element sys_clk_timer
{
datum _sortIndex
{
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value = "3";
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type = "int";
}
}
element sys_clk_timer.s1
{
datum baseAddress
{
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value = "16781312";
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type = "String";
}
}
element sysid
{
datum _sortIndex
{
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value = "4";
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type = "int";
}
}
element sysid.control_slave
{
datum baseAddress
{
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value = "16781360";
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type = "String";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="5CSEMA5F31C6" />
<parameter name="deviceFamily" value="Cyclone V" />
<parameter name="deviceSpeedGrade" value="6" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="hello_world.qpf" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
<interface
name="led_pio_external_connection"
internal="led_pio.external_connection"
type="conduit"
dir="end" />
<interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
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<interface name="sdram_wire" internal="sdram.wire" type="conduit" dir="end" />
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<module name="clk_0" kind="clock_source" version="20.1" enabled="1">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
<module name="cpu" kind="altera_nios2_gen2" version="20.1" enabled="1">
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
<parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
<parameter name="AUTO_DEVICE" value="5CSEMA5F31C6" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
<parameter name="bht_ramBlockType" value="Automatic" />
<parameter name="breakOffset" value="32" />
<parameter name="breakSlave" value="None" />
<parameter name="cdx_enabled" value="false" />
<parameter name="clockFrequency" value="50000000" />
<parameter name="cpuArchRev" value="1" />
<parameter name="cpuID" value="0" />
<parameter name="cpuReset" value="false" />
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<parameter name="customInstSlavesSystemInfo"><![CDATA[<info><slave name="fp_add" baseAddress="0" addressSpan="1" clockCycleType="MULTICYCLE" /><slave name="fp_sub" baseAddress="1" addressSpan="1" clockCycleType="MULTICYCLE" /><slave name="fp_mul" baseAddress="2" addressSpan="1" clockCycleType="MULTICYCLE" /></info>]]></parameter>
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<parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
<parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
<parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
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<parameter name="dataAddrWidth" value="25" />
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<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" />
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<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sdram.s1' start='0x800000' end='0x1000000' type='altera_avalon_new_sdram_controller.s1' /><slave name='cpu.debug_mem_slave' start='0x1000800' end='0x1001000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x1001000' end='0x1001020' type='altera_avalon_timer.s1' /><slave name='led_pio.s1' start='0x1001020' end='0x1001030' type='altera_avalon_pio.s1' /><slave name='sysid.control_slave' start='0x1001030' end='0x1001038' type='altera_avalon_sysid_qsys.control_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x1001038' end='0x1001040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
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<parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" />
<parameter name="data_master_paddr_size" value="0" />
<parameter name="dcache_bursts" value="false" />
<parameter name="dcache_numTCDM" value="0" />
<parameter name="dcache_ramBlockType" value="Automatic" />
<parameter name="dcache_size" value="2048" />
<parameter name="dcache_tagramBlockType" value="Automatic" />
<parameter name="dcache_victim_buf_impl" value="ram" />
<parameter name="debug_OCIOnchipTrace" value="_128" />
<parameter name="debug_assignJtagInstanceID" value="false" />
<parameter name="debug_datatrigger" value="0" />
<parameter name="debug_debugReqSignals" value="false" />
<parameter name="debug_enabled" value="true" />
<parameter name="debug_hwbreakpoint" value="0" />
<parameter name="debug_jtagInstanceID" value="0" />
<parameter name="debug_traceStorage" value="onchip_trace" />
<parameter name="debug_traceType" value="none" />
<parameter name="debug_triggerArming" value="true" />
<parameter name="deviceFamilyName" value="Cyclone V" />
<parameter name="deviceFeaturesSystemInfo">COMPILER_SUPPORT 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 ANY_QFP 0 ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 HARDCOPY 0 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_S
<parameter name="dividerType" value="no_div" />
<parameter name="exceptionOffset" value="32" />
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<parameter name="exceptionSlave" value="sdram.s1" />
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<parameter name="faAddrWidth" value="1" />
<parameter name="faSlaveMapParam" value="" />
<parameter name="fa_cache_line" value="2" />
<parameter name="fa_cache_linesize" value="0" />
<parameter name="flash_instruction_master_paddr_base" value="0" />
<parameter name="flash_instruction_master_paddr_size" value="0" />
<parameter name="icache_burstType" value="None" />
<parameter name="icache_numTCIM" value="0" />
<parameter name="icache_ramBlockType" value="Automatic" />
<parameter name="icache_size" value="2048" />
<parameter name="icache_tagramBlockType" value="Automatic" />
<parameter name="impl" value="Fast" />
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<parameter name="instAddrWidth" value="25" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sdram.s1' start='0x800000' end='0x1000000' type='altera_avalon_new_sdram_controller.s1' /><slave name='cpu.debug_mem_slave' start='0x1000800' end='0x1001000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
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<parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
<parameter name="instructionMasterHighPerformanceMapParam" value="" />
<parameter name="instruction_master_high_performance_paddr_base" value="0" />
<parameter name="instruction_master_high_performance_paddr_size" value="0" />
<parameter name="instruction_master_paddr_base" value="0" />
<parameter name="instruction_master_paddr_size" value="0" />
<parameter name="internalIrqMaskSystemInfo" value="65538" />
<parameter name="io_regionbase" value="0" />
<parameter name="io_regionsize" value="0" />
<parameter name="master_addr_map" value="false" />
<parameter name="mmu_TLBMissExcOffset" value="0" />
<parameter name="mmu_TLBMissExcSlave" value="None" />
<parameter name="mmu_autoAssignTlbPtrSz" value="true" />
<parameter name="mmu_enabled" value="false" />
<parameter name="mmu_processIDNumBits" value="8" />
<parameter name="mmu_ramBlockType" value="Automatic" />
<parameter name="mmu_tlbNumWays" value="16" />
<parameter name="mmu_tlbPtrSz" value="7" />
<parameter name="mmu_udtlbNumEntries" value="6" />
<parameter name="mmu_uitlbNumEntries" value="4" />
<parameter name="mpu_enabled" value="false" />
<parameter name="mpu_minDataRegionSize" value="12" />
<parameter name="mpu_minInstRegionSize" value="12" />
<parameter name="mpu_numOfDataRegion" value="8" />
<parameter name="mpu_numOfInstRegion" value="8" />
<parameter name="mpu_useLimit" value="false" />
<parameter name="mpx_enabled" value="false" />
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<parameter name="mul_32_impl" value="0" />
<parameter name="mul_64_impl" value="0" />
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<parameter name="mul_shift_choice" value="1" />
<parameter name="ocimem_ramBlockType" value="Automatic" />
<parameter name="ocimem_ramInit" value="false" />
<parameter name="regfile_ramBlockType" value="Automatic" />
<parameter name="register_file_por" value="false" />
<parameter name="resetOffset" value="0" />
Task 5 Update QSYS, add PLL block, update main C file to Task 5 end
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<parameter name="resetSlave" value="sdram.s1" />
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<parameter name="resetrequest_enabled" value="true" />
<parameter name="setting_HBreakTest" value="false" />
<parameter name="setting_HDLSimCachesCleared" value="true" />
<parameter name="setting_activateMonitors" value="true" />
<parameter name="setting_activateTestEndChecker" value="false" />
<parameter name="setting_activateTrace" value="false" />
<parameter name="setting_allow_break_inst" value="false" />
<parameter name="setting_alwaysEncrypt" value="true" />
<parameter name="setting_asic_add_scan_mode_input" value="false" />
<parameter name="setting_asic_enabled" value="false" />
<parameter name="setting_asic_synopsys_translate_on_off" value="false" />
<parameter name="setting_asic_third_party_synthesis" value="false" />
<parameter name="setting_avalonDebugPortPresent" value="false" />
<parameter name="setting_bhtPtrSz" value="8" />
<parameter name="setting_bigEndian" value="false" />
<parameter name="setting_branchpredictiontype" value="Dynamic" />
<parameter name="setting_breakslaveoveride" value="false" />
<parameter name="setting_clearXBitsLDNonBypass" value="true" />
<parameter name="setting_dc_ecc_present" value="true" />
<parameter name="setting_disable_tmr_inj" value="false" />
<parameter name="setting_disableocitrace" value="false" />
<parameter name="setting_dtcm_ecc_present" value="true" />
<parameter name="setting_ecc_present" value="false" />
<parameter name="setting_ecc_sim_test_ports" value="false" />
<parameter name="setting_exportHostDebugPort" value="false" />
<parameter name="setting_exportPCB" value="false" />
<parameter name="setting_export_large_RAMs" value="false" />
<parameter name="setting_exportdebuginfo" value="false" />
<parameter name="setting_exportvectors" value="false" />
<parameter name="setting_fast_register_read" value="false" />
<parameter name="setting_ic_ecc_present" value="true" />
<parameter name="setting_interruptControllerType" value="Internal" />
<parameter name="setting_itcm_ecc_present" value="true" />
<parameter name="setting_mmu_ecc_present" value="true" />
<parameter name="setting_oci_export_jtag_signals" value="false" />
<parameter name="setting_oci_version" value="1" />
<parameter name="setting_preciseIllegalMemAccessException" value="false" />
<parameter name="setting_removeRAMinit" value="false" />
<parameter name="setting_rf_ecc_present" value="true" />
<parameter name="setting_shadowRegisterSets" value="0" />
<parameter name="setting_showInternalSettings" value="false" />
<parameter name="setting_showUnpublishedSettings" value="false" />
<parameter name="setting_support31bitdcachebypass" value="true" />
<parameter name="setting_tmr_output_disable" value="false" />
<parameter name="setting_usedesignware" value="false" />
<parameter name="shift_rot_impl" value="1" />
<parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster0MapParam" value="" />
<parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster1MapParam" value="" />
<parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster2MapParam" value="" />
<parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster3MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
<parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
<parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
<parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
<parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
<parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
<parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
<parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
<parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
<parameter name="tmr_enabled" value="false" />
<parameter name="tracefilename" value="" />
<parameter name="userDefinedSettings" value="" />
</module>
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<module name="fp_add" kind="fp_add" version="20.1" enabled="1" />
<module name="fp_mul" kind="fp_mul" version="20.1" enabled="1" />
<module name="fp_sub" kind="fp_sub" version="20.1" enabled="1" />
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<module
name="jtag_uart"
kind="altera_avalon_jtag_uart"
version="20.1"
enabled="1">
<parameter name="allowMultipleConnections" value="false" />
<parameter name="avalonSpec" value="2.0" />
<parameter name="clkFreq" value="50000000" />
<parameter name="hubInstanceID" value="0" />
<parameter name="readBufferDepth" value="64" />
<parameter name="readIRQThreshold" value="8" />
<parameter name="simInputCharacterStream" value="" />
<parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
<parameter name="useRegistersForReadBuffer" value="false" />
<parameter name="useRegistersForWriteBuffer" value="false" />
<parameter name="useRelativePathForSimFile" value="false" />
<parameter name="writeBufferDepth" value="64" />
<parameter name="writeIRQThreshold" value="8" />
</module>
<module name="led_pio" kind="altera_avalon_pio" version="20.1" enabled="1">
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
<parameter name="clockRate" value="50000000" />
<parameter name="direction" value="Output" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
<parameter name="irqType" value="LEVEL" />
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="8" />
</module>
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<module
name="sdram"
kind="altera_avalon_new_sdram_controller"
version="20.1"
enabled="1">
<parameter name="TAC" value="5.5" />
<parameter name="TMRD" value="3" />
<parameter name="TRCD" value="20.0" />
<parameter name="TRFC" value="70.0" />
<parameter name="TRP" value="20.0" />
<parameter name="TWR" value="14.0" />
<parameter name="casLatency" value="3" />
<parameter name="clockRate" value="50000000" />
<parameter name="columnWidth" value="8" />
<parameter name="componentName" value="$${FILENAME}_sdram" />
<parameter name="dataWidth" value="16" />
<parameter name="generateSimulationModel" value="false" />
<parameter name="initNOPDelay" value="0.0" />
<parameter name="initRefreshCommands" value="2" />
<parameter name="masteredTristateBridgeSlave" value="0" />
<parameter name="model">single_Micron_MT48LC4M32B2_7_chip</parameter>
<parameter name="numberOfBanks" value="4" />
<parameter name="numberOfChipSelects" value="1" />
<parameter name="pinsSharedViaTriState" value="false" />
<parameter name="powerUpDelay" value="100.0" />
<parameter name="refreshPeriod" value="15.625" />
<parameter name="registerDataIn" value="true" />
<parameter name="rowWidth" value="12" />
</module>
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<module
name="sys_clk_timer"
kind="altera_avalon_timer"
version="20.1"
enabled="1">
<parameter name="alwaysRun" value="false" />
<parameter name="counterSize" value="32" />
<parameter name="fixedPeriod" value="false" />
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<parameter name="period" value="100" />
<parameter name="periodUnits" value="USEC" />
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<parameter name="resetOutput" value="false" />
<parameter name="snapshot" value="true" />
<parameter name="systemFrequency" value="50000000" />
<parameter name="timeoutPulseOutput" value="false" />
<parameter name="watchdogPulse" value="2" />
</module>
<module
name="sysid"
kind="altera_avalon_sysid_qsys"
version="20.1"
enabled="1">
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<parameter name="id" value="305419896" />
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</module>
<connection
kind="avalon"
version="20.1"
start="cpu.data_master"
end="jtag_uart.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
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<parameter name="baseAddress" value="0x01001038" />
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<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="20.1"
start="cpu.data_master"
end="sysid.control_slave">
<parameter name="arbitrationPriority" value="1" />
Task 5 Update QSYS, add PLL block, update main C file to Task 5 end
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<parameter name="baseAddress" value="0x01001030" />
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<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="20.1"
start="cpu.data_master"
end="cpu.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
Task 5 Update QSYS, add PLL block, update main C file to Task 5 end
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<parameter name="baseAddress" value="0x01000800" />
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<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="20.1"
start="cpu.data_master"
end="sys_clk_timer.s1">
<parameter name="arbitrationPriority" value="1" />
Task 5 Update QSYS, add PLL block, update main C file to Task 5 end
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<parameter name="baseAddress" value="0x01001000" />
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<parameter name="defaultConnection" value="false" />
</connection>
<connection kind="avalon" version="20.1" start="cpu.data_master" end="led_pio.s1">
<parameter name="arbitrationPriority" value="1" />
Task 5 Update QSYS, add PLL block, update main C file to Task 5 end
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<parameter name="baseAddress" value="0x01001020" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection kind="avalon" version="20.1" start="cpu.data_master" end="sdram.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00800000" />
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<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="20.1"
start="cpu.instruction_master"
end="cpu.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
Task 5 Update QSYS, add PLL block, update main C file to Task 5 end
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<parameter name="baseAddress" value="0x01000800" />
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<parameter name="defaultConnection" value="false" />
</connection>
Task 5 Update QSYS, add PLL block, update main C file to Task 5 end
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<connection
kind="avalon"
version="20.1"
start="cpu.instruction_master"
end="sdram.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00800000" />
<parameter name="defaultConnection" value="false" />
</connection>
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<connection kind="clock" version="20.1" start="clk_0.clk" end="cpu.clk" />
<connection kind="clock" version="20.1" start="clk_0.clk" end="jtag_uart.clk" />
<connection kind="clock" version="20.1" start="clk_0.clk" end="sys_clk_timer.clk" />
<connection kind="clock" version="20.1" start="clk_0.clk" end="sysid.clk" />
<connection kind="clock" version="20.1" start="clk_0.clk" end="led_pio.clk" />
Task 5 Update QSYS, add PLL block, update main C file to Task 5 end
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<connection kind="clock" version="20.1" start="clk_0.clk" end="sdram.clk" />
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<connection
kind="interrupt"
version="20.1"
start="cpu.irq"
end="sys_clk_timer.irq">
<parameter name="irqNumber" value="1" />
</connection>
<connection kind="interrupt" version="20.1" start="cpu.irq" end="jtag_uart.irq">
<parameter name="irqNumber" value="16" />
</connection>
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<connection
kind="nios_custom_instruction"
version="20.1"
start="cpu.custom_instruction_master"
end="fp_add.fp_add_slave">
<parameter name="CIName" value="fp_add" />
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0" />
</connection>
<connection
kind="nios_custom_instruction"
version="20.1"
start="cpu.custom_instruction_master"
end="fp_mul.fp_mul_slave">
<parameter name="CIName" value="fp_mul" />
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="2" />
</connection>
<connection
kind="nios_custom_instruction"
version="20.1"
start="cpu.custom_instruction_master"
end="fp_sub.fp_sub_slave">
<parameter name="CIName" value="fp_sub" />
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="1" />
</connection>
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<connection kind="reset" version="20.1" start="clk_0.clk_reset" end="cpu.reset" />
<connection
kind="reset"
version="20.1"
start="clk_0.clk_reset"
end="jtag_uart.reset" />
<connection
kind="reset"
version="20.1"
start="clk_0.clk_reset"
end="sys_clk_timer.reset" />
<connection kind="reset" version="20.1" start="clk_0.clk_reset" end="sysid.reset" />
<connection
kind="reset"
version="20.1"
start="clk_0.clk_reset"
end="led_pio.reset" />
Task 5 Update QSYS, add PLL block, update main C file to Task 5 end
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<connection kind="reset" version="20.1" start="clk_0.clk_reset" end="sdram.reset" />
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<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
Reference in a new issue Copy permalink