8 commits

Author	SHA1	Message	Date
jl7719	c31344c55f	More testcases, testing, debugging	2020-12-13 01:25:36 +09:00
jl7719	14ad7fa0ce	Update program counter ... Logic for instructions with linking not implemented. Can do basic branch delay slots. More left to do with return register	2020-12-12 15:59:14 +09:00
jl7719	3594365a25	Create branch jl7719 ... Can test for normal pc incrementing instr	2020-12-11 19:45:13 +09:00
jl7719	c93473a54d	Update test_mips_cpu_harvard.sh ... Outputs Pass/Fail by comparing to INSTR.ref.txt files (need to add these per instr)	2020-12-10 17:24:40 +09:00
jl7719	c5aed43ab4	Update to test each instruction with a small memory	2020-12-09 16:47:58 +09:00
jl7719	c5167645e7	Fix overall w.r.t iverilog compiler error	2020-12-06 15:44:58 +09:00
jl7719	411f89110f	Add testbench related files	2020-12-04 23:44:48 +09:00
jl7719	e6e4f17afe	Add initial coursework deliverables	2020-11-24 14:20:29 +09:00