supleed2/ELEC50010-IAC-CW
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46 commits

Author SHA1 Message Date
Ibrahim 48e0cdfbb6 added edge cases these don't pass - please check 2020-12-18 08:48:51 +00:00
Aadi Desai 1be11d6c19 Add second store halfword testcase 
Checks that only half the word is written using load word after store halfword
 2020-12-17 10:00:18 -08:00
Aadi Desai c8344184b2 Fix sb, sh testcases 
Tried to write to instr mem + typo
 2020-12-17 09:41:55 -08:00
theexecutor13 6c400f3567 uploading log.txt weirdness testcase 2020-12-17 14:31:33 +00:00
theexecutor13 7fcc2486cb cleanup 2020-12-17 13:37:00 +00:00
theexecutor13 ab13c84ef5 testing branch delay slot 2020-12-17 12:03:30 +00:00
jl7719 697b6e0a9e Update some testcases for branch delay slots 2020-12-16 17:13:39 +00:00
Aadi Desai 252f630162 Cleanup 2020-12-16 15:40:21 +00:00
Aadi Desai 1a413d9686 Merge branch 'main' into jl7719 2020-12-16 15:40:07 +00:00
jl7719 ebe33ce56a Passes all tests 2020-12-16 15:29:04 +00:00
Jeevaha Coelho 7185f7e7e6 Fixed BGEZAL 2020-12-16 07:00:46 -08:00
Jeevaha Coelho 2673e23137 FIxed PC! 2020-12-16 05:21:57 -08:00
jl7719 ad68ab0974 Debugging and debugging 
PC, Jump instr, branches
 2020-12-16 12:29:22 +00:00
jl7719 0891f7e653 Debug mult/div to work 
it works now
 2020-12-16 08:38:46 +00:00
yhp19 07d32e9baf fixed input file plz document ur change in reference.txt 2020-12-16 12:27:48 +08:00
yhp19 cc5d2bbeab changes to input files 2020-12-16 00:57:46 +08:00
jl7719 b812399844 Fix to allow multiple testcases for each instruction 2020-12-15 15:06:04 +00:00
Ibrahim adb4b5d6fd created seperate division testcases, fived srlv, sllu, srav & added sh (forgot this instruction previously) 2020-12-15 13:42:09 +00:00
Ibrahim 26ccff5057 Merge branch 'jl7719' of https://github.com/supleed2/AM04_CPU into main 2020-12-15 13:38:04 +00:00
ppuk 2030a186cc changed bltzal input txt 2020-12-15 08:56:23 +00:00
jl7719 63abcf671a Tidy up and change bash to ./ 2020-12-14 17:49:30 +00:00
theexecutor13 6519be9a9e
Update reference.txt 2020-12-14 23:59:08 +08:00
theexecutor13 d72676c30c
Update bltzal.txt 2020-12-14 23:58:08 +08:00
jl7719 f882d1e361 Test different inputs for lb, lbu 
it works
 2020-12-13 15:16:53 +09:00
jl7719 943745a1e0 Tested all that can be tested for now 
Mult/Div, Branch/Jump Linking, J needs implementation before testing and store to be tested when switched to bus
 2020-12-13 14:40:16 +09:00
jl7719 c31344c55f More testcases, testing, debugging 2020-12-13 01:25:36 +09:00
yhp19 276f7f8216 Added ref files for j and load instructions 2020-12-12 23:59:04 +08:00
yhp19 ab27fcaed3 Reference txt now in reference folders 2020-12-12 23:46:42 +08:00
yhp19 69cd711cfc Added load instruction txt and data.txt 2020-12-12 23:39:00 +08:00
jl7719 14ad7fa0ce Update program counter 
Logic for instructions with linking not implemented. Can do basic branch delay slots. More left to do with return register
 2020-12-12 15:59:14 +09:00
jl7719 3594365a25 Create branch jl7719 
Can test for normal pc incrementing instr
 2020-12-11 19:45:13 +09:00
yhp19 2c5b3ad604 Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main 2020-12-11 15:54:45 +08:00
yhp19 47e0f42f92 added load instructions 2020-12-11 15:54:23 +08:00
jl7719 7ffd8fb400 Add testcases and ref outputs for addiu, and, andi 2020-12-11 15:17:43 +09:00
Ibrahim 1bf7b5d40e All instructions except load finished - some test cases may need changing upon review 2020-12-10 19:39:04 +00:00
jl7719 c93473a54d Update test_mips_cpu_harvard.sh 
Outputs Pass/Fail by comparing to INSTR.ref.txt files (need to add these per instr)
 2020-12-10 17:24:40 +09:00
yhp19 db344b3150 added div and instruction testcase and minor adjustment on bl instructions 2020-12-10 13:51:54 +08:00
Ibrahim 0be5617371 75% done - need to redo arithemtic operation to test edge cases & do certain instr by hand 2020-12-09 20:17:58 +00:00
yhp19 31ad264fac updated with .txt files 2020-12-10 00:57:31 +08:00
theexecutor13 315e5af32c
Update reference.txt 
Fixed branch instruction test case in ref.txt
 2020-12-10 00:41:19 +08:00
theexecutor13 b17158489f
Added jump type testcase in ref.txt 2020-12-10 00:10:38 +08:00
jl7719 7e6bc7c370 Update branch testcases 
Reference file is not updated
 2020-12-09 23:21:45 +09:00
jl7719 c5aed43ab4 Update to test each instruction with a small memory 2020-12-09 16:47:58 +09:00
yhp19 ff912207b8 added branch test inputs 2020-12-07 18:35:06 +08:00
jl7719 c5167645e7 Fix overall w.r.t iverilog compiler error 2020-12-06 15:44:58 +09:00
jl7719 411f89110f Add testbench related files 2020-12-04 23:44:48 +09:00