supleed2/ELEC50010-IAC-CW
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41 commits 2 branches 0 tags 9.2 MiB
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11 commits

Author SHA1 Message Date
Aadi Desai f2f8e05010 PC logic updated 
PC now has a delay into instr_mem to match MIPS32 spec and pc resets/initialises to MIPS32 reset vector
 2020-12-02 17:23:28 +00:00
Aadi Desai 2c967a910b Update mips_cpu_harvard.v 
Fix typo + immediate already fed in via alu_in2
 2020-12-02 14:24:17 +00:00
Aadi Desai bd9ae64dc2 Update hardvard.v to match ALU 2020-12-02 13:27:37 +00:00
Aadi Desai 27cccc28b8 Added partial loads to regfile 
Partial reads are handled within the ALU
 2020-12-02 01:04:57 +00:00
Aadi Desai 3433337eba Added Regfile 
Missing partial/misaligned loads
 2020-12-01 23:04:43 +00:00
Aadi Desai 5a72698fec Update mips_cpu_harvard.v 
Add registerv0 testbench line
 2020-11-30 15:36:25 +00:00
Ibrahim ba192442e4 adding immediate back 2020-11-30 14:15:36 +00:00
Ibrahim 954a5b47aa
Added shamt to the deconstruction of the instruction 2020-11-30 13:50:04 +00:00
Aadi Desai 3b183075aa Update mips_cpu_harvard.v 
Added andlink functionality?
 2020-11-29 01:16:33 +00:00
Aadi Desai b5766a15ba Update mips_cpu_harvard.v 
Initial version, connection names to be matched to individual modules
 2020-11-29 01:04:08 +00:00
jl7719 e6e4f17afe Add initial coursework deliverables 2020-11-24 14:20:29 +09:00