supleed2/ELEC50010-IAC-CW
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2 commits

Author SHA1 Message Date
Aadi Desai 7b01ae06eb Change parameter to use instr+data testcase 2020-12-20 12:08:21 +00:00
Aadi Desai 6c0554538c Rename .v to .sv for Quartus to detect as SystemVerilog 2020-12-19 08:43:20 -08:00
Renamed from testbench/mips_cpu_harvard_tb.v (Browse further)