15 commits

Author	SHA1	Message	Date
jl7719	14ad7fa0ce	Update program counter ... Logic for instructions with linking not implemented. Can do basic branch delay slots. More left to do with return register	2020-12-12 15:59:14 +09:00
jl7719	3594365a25	Create branch jl7719 ... Can test for normal pc incrementing instr	2020-12-11 19:45:13 +09:00
jl7719	7ffd8fb400	Add testcases and ref outputs for addiu, and, andi	2020-12-11 15:17:43 +09:00
Ibrahim	1bf7b5d40e	All instructions except load finished - some test cases may need changing upon review	2020-12-10 19:39:04 +00:00
jl7719	c93473a54d	Update test_mips_cpu_harvard.sh ... Outputs Pass/Fail by comparing to INSTR.ref.txt files (need to add these per instr)	2020-12-10 17:24:40 +09:00
yhp19	db344b3150	added div and instruction testcase and minor adjustment on bl instructions	2020-12-10 13:51:54 +08:00
Ibrahim	0be5617371	75% done - need to redo arithemtic operation to test edge cases & do certain instr by hand	2020-12-09 20:17:58 +00:00
yhp19	31ad264fac	updated with .txt files	2020-12-10 00:57:31 +08:00
theexecutor13	315e5af32c	Update reference.txt ... Fixed branch instruction test case in ref.txt	2020-12-10 00:41:19 +08:00
theexecutor13	b17158489f	Added jump type testcase in ref.txt	2020-12-10 00:10:38 +08:00
jl7719	7e6bc7c370	Update branch testcases ... Reference file is not updated	2020-12-09 23:21:45 +09:00
jl7719	c5aed43ab4	Update to test each instruction with a small memory	2020-12-09 16:47:58 +09:00
yhp19	ff912207b8	added branch test inputs	2020-12-07 18:35:06 +08:00
jl7719	c5167645e7	Fix overall w.r.t iverilog compiler error	2020-12-06 15:44:58 +09:00
jl7719	411f89110f	Add testbench related files	2020-12-04 23:44:48 +09:00