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Add testcase specific waveforms

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This commit is contained in:
Aadi Desai 2020-12-20 08:42:37 -08:00
parent 9003384106
commit 859020bae5
5 changed files with 12 additions and 12 deletions
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1
.gitignore vendored
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@ -8,3 +8,4 @@ mips_cpu_bus.vcd
inputs/.DS_Store inputs/.DS_Store
*.stderr.txt *.stderr.txt
*.diff.txt *.diff.txt
inputs/*/*.vcd

2
test/test_mips_cpu_bus.sh
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@ -25,6 +25,7 @@ then
-s mips_cpu_bus_tb \ -s mips_cpu_bus_tb \
-P mips_cpu_bus_tb.INSTR_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.instr.txt\" \ -P mips_cpu_bus_tb.INSTR_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.instr.txt\" \
-P mips_cpu_bus_tb.DATA_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.data.txt\" \ -P mips_cpu_bus_tb.DATA_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.data.txt\" \
-P mips_cpu_bus_tb.TESTCASE=\"inputs/${DIR}/${TESTCASE}.vcd\" \
-o exec/mips_cpu_bus_tb_${TESTCASE} testbench/mips_cpu_bus_tb.v testbench/mips_cpu_bus_memory.v \ -o exec/mips_cpu_bus_tb_${TESTCASE} testbench/mips_cpu_bus_tb.v testbench/mips_cpu_bus_memory.v \
${SRC} 2> inputs/${DIR}/${TESTCASE}.stderr.txt ${SRC} 2> inputs/${DIR}/${TESTCASE}.stderr.txt
./exec/mips_cpu_bus_tb_${TESTCASE} &> ./inputs/${DIR}/${TESTCASE}.log.txt; # log file for debugging (contains $display) ./exec/mips_cpu_bus_tb_${TESTCASE} &> ./inputs/${DIR}/${TESTCASE}.log.txt; # log file for debugging (contains $display)
@ -46,6 +47,7 @@ else
-s mips_cpu_bus_tb \ -s mips_cpu_bus_tb \
-P mips_cpu_bus_tb.INSTR_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.instr.txt\" \ -P mips_cpu_bus_tb.INSTR_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.instr.txt\" \
-P mips_cpu_bus_tb.DATA_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.data.txt\" \ -P mips_cpu_bus_tb.DATA_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.data.txt\" \
-P mips_cpu_bus_tb.TESTCASE=\"inputs/${INSTR}/${TESTCASE}.vcd\" \
-o exec/mips_cpu_bus_tb_${TESTCASE} testbench/mips_cpu_bus_tb.v testbench/mips_cpu_bus_memory.v \ -o exec/mips_cpu_bus_tb_${TESTCASE} testbench/mips_cpu_bus_tb.v testbench/mips_cpu_bus_memory.v \
${SRC} 2> inputs/${INSTR}/${TESTCASE}.stderr.txt ${SRC} 2> inputs/${INSTR}/${TESTCASE}.stderr.txt
./exec/mips_cpu_bus_tb_${TESTCASE} &> ./inputs/${INSTR}/${TESTCASE}.log.txt; # log file for debugging (contains $display) ./exec/mips_cpu_bus_tb_${TESTCASE} &> ./inputs/${INSTR}/${TESTCASE}.log.txt; # log file for debugging (contains $display)

2
test/test_mips_cpu_harvard.sh
View file

@ -25,6 +25,7 @@ then
-s mips_cpu_harvard_tb \ -s mips_cpu_harvard_tb \
-P mips_cpu_harvard_tb.INSTR_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.instr.txt\" \ -P mips_cpu_harvard_tb.INSTR_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.instr.txt\" \
-P mips_cpu_harvard_tb.DATA_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.data.txt\" \ -P mips_cpu_harvard_tb.DATA_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.data.txt\" \
-P mips_cpu_harvard_tb.TESTCASE=\"inputs/${DIR}/${TESTCASE}.vcd\" \
-o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v testbench/mips_cpu_harvard_memory.v\ -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v testbench/mips_cpu_harvard_memory.v\
${SRC} 2> inputs/${DIR}/${TESTCASE}.stderr.txt ${SRC} 2> inputs/${DIR}/${TESTCASE}.stderr.txt
./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${DIR}/${TESTCASE}.log.txt; # log file for debugging (contains $display) ./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${DIR}/${TESTCASE}.log.txt; # log file for debugging (contains $display)
@ -46,6 +47,7 @@ else
-s mips_cpu_harvard_tb \ -s mips_cpu_harvard_tb \
-P mips_cpu_harvard_tb.INSTR_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.instr.txt\" \ -P mips_cpu_harvard_tb.INSTR_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.instr.txt\" \
-P mips_cpu_harvard_tb.DATA_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.data.txt\" \ -P mips_cpu_harvard_tb.DATA_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.data.txt\" \
-P mips_cpu_harvard_tb.TESTCASE=\"inputs/${INSTR}/${TESTCASE}.vcd\" \
-o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v testbench/mips_cpu_harvard_memory.v\ -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v testbench/mips_cpu_harvard_memory.v\
${SRC} 2> inputs/${INSTR}/${TESTCASE}.stderr.txt ${SRC} 2> inputs/${INSTR}/${TESTCASE}.stderr.txt
./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${INSTR}/${TESTCASE}.log.txt; # log file for debugging (contains $display) ./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${INSTR}/${TESTCASE}.log.txt; # log file for debugging (contains $display)

10
testbench/mips_cpu_bus_tb.v
View file

@ -2,6 +2,7 @@ module mips_cpu_bus_tb;
parameter INSTR_INIT_FILE = ""; parameter INSTR_INIT_FILE = "";
parameter DATA_INIT_FILE = ""; parameter DATA_INIT_FILE = "";
parameter TESTCASE = "";
parameter TIMEOUT_CYCLES = 100; // Timeout cycles are higher to account for memory stall delays parameter TIMEOUT_CYCLES = 100; // Timeout cycles are higher to account for memory stall delays
logic clk, reset, active, write, read, waitrequest; logic clk, reset, active, write, read, waitrequest;
@ -36,7 +37,7 @@ mips_cpu_bus cpuInst(
// Setup and clock // Setup and clock
initial begin initial begin
$dumpfile("mips_cpu_bus.vcd"); $dumpfile(TESTCASE);
$dumpvars(0,mips_cpu_bus_tb); $dumpvars(0,mips_cpu_bus_tb);
clk=0; clk=0;
@ -60,14 +61,7 @@ initial begin
else $display("TB : CPU did not set active=1 after reset."); else $display("TB : CPU did not set active=1 after reset.");
while (active) begin while (active) begin
//$display("Clk: %d", clk);
@(posedge clk); @(posedge clk);
//$display("Register v0: %d", register_v0);
//$display("Reg File Write data: %d", cpuInst.in_writedata);
$display("Reg File Out Read data: %h", cpuInst.mips_cpu_harvard.out_readdata1);
$display("Reg File opcode: %b", cpuInst.mips_cpu_harvard.regfile.opcode);
//$display("ALU output: %h", cpuInst.out_ALURes);
//$display("ALU input B: %h", cpuInst.alu.B);
end end
@(posedge clk); @(posedge clk);

7
testbench/mips_cpu_harvard_tb.v
View file

@ -1,7 +1,8 @@
module mips_cpu_harvard_tb; module mips_cpu_harvard_tb;
parameter INSTR_INIT_FILE = "inputs/addiu.txt"; parameter INSTR_INIT_FILE = "";
parameter DATA_INIT_FILE = "inputs/addiu.data.txt"; parameter DATA_INIT_FILE = "";
parameter TESTCASE = "";
parameter TIMEOUT_CYCLES = 100; parameter TIMEOUT_CYCLES = 100;
logic clk, clk_enable, reset, active, data_read, data_write; logic clk, clk_enable, reset, active, data_read, data_write;
@ -34,7 +35,7 @@ module mips_cpu_harvard_tb;
// Generate clock // Generate clock
initial begin initial begin
$dumpfile("mips_cpu_harvard.vcd"); $dumpfile(TESTCASE);
$dumpvars(0,mips_cpu_harvard_tb); $dumpvars(0,mips_cpu_harvard_tb);
clk=0; clk=0;