diff --git a/.gitignore b/.gitignore
index 1ab9eb7..f5c2d27 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,4 +7,5 @@ mips_cpu_bus.vcd
 .DS_Store
 inputs/.DS_Store
 *.stderr.txt
-*.diff.txt
\ No newline at end of file
+*.diff.txt
+inputs/*/*.vcd
\ No newline at end of file
diff --git a/test/test_mips_cpu_bus.sh b/test/test_mips_cpu_bus.sh
index 117b933..6d67445 100755
--- a/test/test_mips_cpu_bus.sh
+++ b/test/test_mips_cpu_bus.sh
@@ -25,6 +25,7 @@ then
                 -s mips_cpu_bus_tb \
                 -P mips_cpu_bus_tb.INSTR_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.instr.txt\" \
                 -P mips_cpu_bus_tb.DATA_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.data.txt\" \
+                -P mips_cpu_bus_tb.TESTCASE=\"inputs/${DIR}/${TESTCASE}.vcd\" \
                 -o exec/mips_cpu_bus_tb_${TESTCASE} testbench/mips_cpu_bus_tb.v testbench/mips_cpu_bus_memory.v \
                 ${SRC} 2> inputs/${DIR}/${TESTCASE}.stderr.txt
             ./exec/mips_cpu_bus_tb_${TESTCASE} &> ./inputs/${DIR}/${TESTCASE}.log.txt;             # log file for debugging (contains $display)
@@ -46,6 +47,7 @@ else
         -s mips_cpu_bus_tb \
         -P mips_cpu_bus_tb.INSTR_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.instr.txt\" \
         -P mips_cpu_bus_tb.DATA_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.data.txt\" \
+        -P mips_cpu_bus_tb.TESTCASE=\"inputs/${INSTR}/${TESTCASE}.vcd\" \
         -o exec/mips_cpu_bus_tb_${TESTCASE} testbench/mips_cpu_bus_tb.v testbench/mips_cpu_bus_memory.v \
         ${SRC} 2> inputs/${INSTR}/${TESTCASE}.stderr.txt
         ./exec/mips_cpu_bus_tb_${TESTCASE} &> ./inputs/${INSTR}/${TESTCASE}.log.txt;             # log file for debugging (contains $display)
diff --git a/test/test_mips_cpu_harvard.sh b/test/test_mips_cpu_harvard.sh
index eabb1c1..9348002 100755
--- a/test/test_mips_cpu_harvard.sh
+++ b/test/test_mips_cpu_harvard.sh
@@ -25,6 +25,7 @@ then
                 -s mips_cpu_harvard_tb \
                 -P mips_cpu_harvard_tb.INSTR_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.instr.txt\" \
                 -P mips_cpu_harvard_tb.DATA_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.data.txt\" \
+                -P mips_cpu_harvard_tb.TESTCASE=\"inputs/${DIR}/${TESTCASE}.vcd\" \
                 -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v testbench/mips_cpu_harvard_memory.v\
                 ${SRC} 2> inputs/${DIR}/${TESTCASE}.stderr.txt
             ./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${DIR}/${TESTCASE}.log.txt;             # log file for debugging (contains $display)
@@ -46,6 +47,7 @@ else
         -s mips_cpu_harvard_tb \
         -P mips_cpu_harvard_tb.INSTR_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.instr.txt\" \
         -P mips_cpu_harvard_tb.DATA_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.data.txt\" \
+        -P mips_cpu_harvard_tb.TESTCASE=\"inputs/${INSTR}/${TESTCASE}.vcd\" \
         -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v testbench/mips_cpu_harvard_memory.v\
         ${SRC} 2> inputs/${INSTR}/${TESTCASE}.stderr.txt
         ./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${INSTR}/${TESTCASE}.log.txt;             # log file for debugging (contains $display)
diff --git a/testbench/mips_cpu_bus_tb.v b/testbench/mips_cpu_bus_tb.v
index 4bd0d89..36f0921 100644
--- a/testbench/mips_cpu_bus_tb.v
+++ b/testbench/mips_cpu_bus_tb.v
@@ -2,6 +2,7 @@ module mips_cpu_bus_tb;
 
 parameter INSTR_INIT_FILE = "";
 parameter DATA_INIT_FILE = "";
+parameter TESTCASE = "";
 parameter TIMEOUT_CYCLES = 100; // Timeout cycles are higher to account for memory stall delays
 
 logic clk, reset, active, write, read, waitrequest;
@@ -36,7 +37,7 @@ mips_cpu_bus cpuInst(
 
 // Setup and clock
 initial begin
-    $dumpfile("mips_cpu_bus.vcd");
+    $dumpfile(TESTCASE);
     $dumpvars(0,mips_cpu_bus_tb);
     clk=0;
 
@@ -60,14 +61,7 @@ initial begin
     else $display("TB : CPU did not set active=1 after reset.");
 
     while (active) begin
-        //$display("Clk: %d", clk);
         @(posedge clk);
-        //$display("Register v0: %d", register_v0);
-        //$display("Reg File Write data: %d", cpuInst.in_writedata);
-        $display("Reg File Out Read data: %h", cpuInst.mips_cpu_harvard.out_readdata1);
-        $display("Reg File opcode: %b", cpuInst.mips_cpu_harvard.regfile.opcode);
-        //$display("ALU output: %h", cpuInst.out_ALURes);
-        //$display("ALU input B: %h", cpuInst.alu.B);
     end
 
     @(posedge clk);
diff --git a/testbench/mips_cpu_harvard_tb.v b/testbench/mips_cpu_harvard_tb.v
index fba3cf7..33b8912 100644
--- a/testbench/mips_cpu_harvard_tb.v
+++ b/testbench/mips_cpu_harvard_tb.v
@@ -1,7 +1,8 @@
 module mips_cpu_harvard_tb;
 
-    parameter INSTR_INIT_FILE = "inputs/addiu.txt";
-    parameter DATA_INIT_FILE = "inputs/addiu.data.txt";
+    parameter INSTR_INIT_FILE = "";
+    parameter DATA_INIT_FILE = "";
+    parameter TESTCASE = "";
     parameter TIMEOUT_CYCLES = 100;
 
     logic clk, clk_enable, reset, active, data_read, data_write;
@@ -34,7 +35,7 @@ module mips_cpu_harvard_tb;
 
     // Generate clock
     initial begin
-        $dumpfile("mips_cpu_harvard.vcd");
+        $dumpfile(TESTCASE);
         $dumpvars(0,mips_cpu_harvard_tb);
         clk=0;