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Update files to remove random Quartus errors

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This commit is contained in:
Aadi Desai 2020-12-20 12:43:19 +00:00
parent 7b01ae06eb
commit 711d0df54e
5 changed files with 83 additions and 70 deletions
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4
rtl/mips_cpu_alu.sv
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@ -222,7 +222,9 @@ end
5'd25: begin 5'd25: begin
temp_Lo = Lo_in; temp_Lo = Lo_in;
end end
default: begin
end
endcase endcase
end end

12
rtl/mips_cpu_cpc.sv
View file

@ -19,12 +19,12 @@ always_comb begin
is_active = 1; is_active = 1;
end else begin end else begin
cpc_curr = cpc_in; cpc_curr = cpc_in;
end if(cpc_in == 32'd0)begin
is_active = 0;
if(cpc_in == 32'd0)begin end else begin
is_active = 0; is_active = 1;
end end
end
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin

6
rtl/mips_cpu_harvard.sv
View file

@ -50,6 +50,9 @@ always @(*) begin
2'd2: begin 2'd2: begin
in_writereg = 5'd31;//Link Register 31. in_writereg = 5'd31;//Link Register 31.
end end
default: begin
in_writereg = 5'bxxxxx;
end
endcase endcase
//Picking which output should be written to regfile. //Picking which output should be written to regfile.
@ -69,6 +72,9 @@ always @(*) begin
3'd4:begin 3'd4:begin
in_writedata = (out_ALULo); in_writedata = (out_ALULo);
end end
default: begin
in_writedata = 32'hxxxxxxxx;
end
endcase endcase
//Picking which output should be taken as the second operand for ALU. //Picking which output should be taken as the second operand for ALU.

122
rtl/mips_cpu_regfile.sv
View file

@ -13,7 +13,7 @@ input logic[1:0] vaddr, //partial read offset from ALUout
output logic[31:0] regv0 //debug output of $v0 or $2 (third register in file/ first register for returning function results) output logic[31:0] regv0 //debug output of $v0 or $2 (third register in file/ first register for returning function results)
); );
reg[31:0] memory [31:0]; //32 register slots, 32-bits wide logic[31:0] memory [0:31]; //32 register slots, 32-bits wide
initial begin initial begin
integer i; //Initialise to zero by default integer i; //Initialise to zero by default
@ -27,66 +27,66 @@ assign regv0 = memory[2]; //assigning debug $v0 line to $2 of memory
assign readdata1 = memory[readreg1]; //combinatorially output register value based on read port 1 selector assign readdata1 = memory[readreg1]; //combinatorially output register value based on read port 1 selector
assign readdata2 = memory[readreg2]; //combinatorially output register value based on read port 2 selector assign readdata2 = memory[readreg2]; //combinatorially output register value based on read port 2 selector
always_ff @(posedge rst) begin always_ff @(posedge rst or negedge clk) begin
integer i; //Initialise to zero when reset if(rst) begin
for (i = 0; i < 32; i++) begin integer i; //Initialise to zero when reset
memory[i] = 0; for (i = 0; i < 32; i++) begin
end memory[i] = 0;
end end
end else begin
always_ff @(negedge clk) begin if (writereg == 5'b00000) begin
if (writereg == 5'b00000) begin // skip writing if rd is $0
// skip writing if rd is $0 end else if (regwrite) begin
end else if (regwrite) begin case (opcode)
case (opcode) 6'b100000: begin //lb, load byte
6'b100000: begin //lb, load byte case (vaddr)
case (vaddr) 2'b00: memory[writereg] <= {{24{writedata[7]}}, writedata[7:0]};
2'b00: memory[writereg] <= {{24{writedata[7]}}, writedata[7:0]}; 2'b01: memory[writereg] <= {{24{writedata[15]}}, writedata[15:8]};
2'b01: memory[writereg] <= {{24{writedata[15]}}, writedata[15:8]}; 2'b10: memory[writereg] <= {{24{writedata[23]}}, writedata[23:16]};
2'b10: memory[writereg] <= {{24{writedata[23]}}, writedata[23:16]}; 2'b11: memory[writereg] <= {{24{writedata[31]}}, writedata[31:24]};
2'b11: memory[writereg] <= {{24{writedata[31]}}, writedata[31:24]}; endcase // readdata1[1:0]
endcase // readdata1[1:0] end
end 6'b100100: begin //lbu, load byte unsigned
6'b100100: begin //lbu, load byte unsigned case (vaddr)
case (vaddr) 2'b00: memory[writereg] <= {{24{1'b0}}, writedata[7:0]};
2'b00: memory[writereg] <= {{24{1'b0}}, writedata[7:0]}; 2'b01: memory[writereg] <= {{24{1'b0}}, writedata[15:8]};
2'b01: memory[writereg] <= {{24{1'b0}}, writedata[15:8]}; 2'b10: memory[writereg] <= {{24{1'b0}}, writedata[23:16]};
2'b10: memory[writereg] <= {{24{1'b0}}, writedata[23:16]}; 2'b11: memory[writereg] <= {{24{1'b0}}, writedata[31:24]};
2'b11: memory[writereg] <= {{24{1'b0}}, writedata[31:24]}; endcase // readdata1[1:0]
endcase // readdata1[1:0] end
end 6'b100001: begin //lh, load half-word
6'b100001: begin //lh, load half-word case (vaddr) // must be half-word aligned, readdata1[0] = 0
case (vaddr) // must be half-word aligned, readdata1[0] = 0 2'b00: memory[writereg] <= {{16{writedata[15]}}, writedata[15:0]};
2'b00: memory[writereg] <= {{16{writedata[15]}}, writedata[15:0]}; 2'b10: memory[writereg] <= {{16{writedata[31]}}, writedata[31:16]};
2'b10: memory[writereg] <= {{16{writedata[31]}}, writedata[31:16]}; endcase // readdata1[1:0]
endcase // readdata1[1:0] end
end 6'b100101: begin //lhu, load half-word unsigned
6'b100101: begin //lhu, load half-word unsigned case (vaddr) // must be half-word aligned, readdata1[0] = 0
case (vaddr) // must be half-word aligned, readdata1[0] = 0 2'b00: memory[writereg] <= {{16{1'b0}}, writedata[15:0]};
2'b00: memory[writereg] <= {{16{1'b0}}, writedata[15:0]}; 2'b10: memory[writereg] <= {{16{1'b0}}, writedata[31:16]};
2'b10: memory[writereg] <= {{16{1'b0}}, writedata[31:16]}; endcase // readdata1[1:0]
endcase // readdata1[1:0] end
end 6'b100010: begin //lwl, load word left
6'b100010: begin //lwl, load word left case (vaddr)
case (vaddr) 2'b00: memory[writereg][31:24] <= writedata[7:0];
2'b00: memory[writereg][31:24] <= writedata[7:0]; 2'b01: memory[writereg][31:16] <= writedata[15:0];
2'b01: memory[writereg][31:16] <= writedata[15:0]; 2'b10: memory[writereg][31:8] <= writedata[23:0];
2'b10: memory[writereg][31:8] <= writedata[23:0]; 2'b11: memory[writereg][31:0] <= writedata[31:0];
2'b11: memory[writereg][31:0] <= writedata[31:0]; endcase // readdata1[1:0]
endcase // readdata1[1:0] end
end 6'b100110: begin //lwr, load word right
6'b100110: begin //lwr, load word right case (vaddr)
case (vaddr) 2'b00: memory[writereg][31:0] <= writedata[31:0];
2'b00: memory[writereg][31:0] <= writedata[31:0]; 2'b01: memory[writereg][23:0] <= writedata[31:8];
2'b01: memory[writereg][23:0] <= writedata[31:8]; 2'b10: memory[writereg][15:0] <= writedata[31:16];
2'b10: memory[writereg][15:0] <= writedata[31:16]; 2'b11: memory[writereg][7:0] <= writedata[31:24];
2'b11: memory[writereg][7:0] <= writedata[31:24]; endcase // readdata1[1:0]
endcase // readdata1[1:0] end
end default: begin
default: begin memory[writereg] <= writedata; //most instructions
memory[writereg] <= writedata; //most instructions end
end endcase // opcode
endcase // opcode end
end end
end end

9
testbench/mips_cpu_harvard_tb.sv
View file

@ -1,10 +1,13 @@
module mips_cpu_harvard_tb; module mips_cpu_harvard_tb(
input logic clk,
input logic reset
);
parameter INSTR_INIT_FILE = "inputs/lw/lw-1.instr.txt"; parameter INSTR_INIT_FILE = "inputs/lw/lw-1.instr.txt";
parameter DATA_INIT_FILE = "inputs/lw/lw-1.data.txt"; parameter DATA_INIT_FILE = "inputs/lw/lw-1.data.txt";
parameter TIMEOUT_CYCLES = 100; parameter TIMEOUT_CYCLES = 100;
logic clk, clk_enable, reset, active, data_read, data_write; logic clk_enable, active, data_read, data_write;
logic[31:0] register_v0, instr_address, instr_readdata, data_readdata, data_writedata, data_address; logic[31:0] register_v0, instr_address, instr_readdata, data_readdata, data_writedata, data_address;
mips_cpu_harvard_memory #(INSTR_INIT_FILE, DATA_INIT_FILE) ramInst( mips_cpu_harvard_memory #(INSTR_INIT_FILE, DATA_INIT_FILE) ramInst(
@ -33,6 +36,7 @@ module mips_cpu_harvard_tb;
); );
// Generate clock // Generate clock
/*
initial begin initial begin
$dumpfile("mips_cpu_harvard.vcd"); $dumpfile("mips_cpu_harvard.vcd");
$dumpvars(0,mips_cpu_harvard_tb); $dumpvars(0,mips_cpu_harvard_tb);
@ -68,4 +72,5 @@ module mips_cpu_harvard_tb;
$finish; $finish;
end end
*/
endmodule endmodule