From 711d0df54e17aed5d947063267a78eb1796345ba Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Sun, 20 Dec 2020 12:43:19 +0000 Subject: [PATCH] Update files to remove random Quartus errors --- rtl/mips_cpu_alu.sv | 4 +- rtl/mips_cpu_cpc.sv | 12 +-- rtl/mips_cpu_harvard.sv | 6 ++ rtl/mips_cpu_regfile.sv | 122 +++++++++++++++---------------- testbench/mips_cpu_harvard_tb.sv | 9 ++- 5 files changed, 83 insertions(+), 70 deletions(-) diff --git a/rtl/mips_cpu_alu.sv b/rtl/mips_cpu_alu.sv index 1ca8900..509c8a2 100644 --- a/rtl/mips_cpu_alu.sv +++ b/rtl/mips_cpu_alu.sv @@ -222,7 +222,9 @@ end 5'd25: begin temp_Lo = Lo_in; end - + + default: begin + end endcase end diff --git a/rtl/mips_cpu_cpc.sv b/rtl/mips_cpu_cpc.sv index 0b649df..b4a34f6 100644 --- a/rtl/mips_cpu_cpc.sv +++ b/rtl/mips_cpu_cpc.sv @@ -19,12 +19,12 @@ always_comb begin is_active = 1; end else begin cpc_curr = cpc_in; - end - - if(cpc_in == 32'd0)begin - is_active = 0; - end - + if(cpc_in == 32'd0)begin + is_active = 0; + end else begin + is_active = 1; + end + end end always_ff @(posedge clk) begin diff --git a/rtl/mips_cpu_harvard.sv b/rtl/mips_cpu_harvard.sv index 39fc962..8c2b45b 100644 --- a/rtl/mips_cpu_harvard.sv +++ b/rtl/mips_cpu_harvard.sv @@ -50,6 +50,9 @@ always @(*) begin 2'd2: begin in_writereg = 5'd31;//Link Register 31. end + default: begin + in_writereg = 5'bxxxxx; + end endcase //Picking which output should be written to regfile. @@ -69,6 +72,9 @@ always @(*) begin 3'd4:begin in_writedata = (out_ALULo); end + default: begin + in_writedata = 32'hxxxxxxxx; + end endcase //Picking which output should be taken as the second operand for ALU. diff --git a/rtl/mips_cpu_regfile.sv b/rtl/mips_cpu_regfile.sv index b789a81..b0d5d2a 100644 --- a/rtl/mips_cpu_regfile.sv +++ b/rtl/mips_cpu_regfile.sv @@ -13,7 +13,7 @@ input logic[1:0] vaddr, //partial read offset from ALUout output logic[31:0] regv0 //debug output of $v0 or $2 (third register in file/ first register for returning function results) ); -reg[31:0] memory [31:0]; //32 register slots, 32-bits wide +logic[31:0] memory [0:31]; //32 register slots, 32-bits wide initial begin integer i; //Initialise to zero by default @@ -27,66 +27,66 @@ assign regv0 = memory[2]; //assigning debug $v0 line to $2 of memory assign readdata1 = memory[readreg1]; //combinatorially output register value based on read port 1 selector assign readdata2 = memory[readreg2]; //combinatorially output register value based on read port 2 selector -always_ff @(posedge rst) begin - integer i; //Initialise to zero when reset - for (i = 0; i < 32; i++) begin - memory[i] = 0; - end -end - -always_ff @(negedge clk) begin - if (writereg == 5'b00000) begin - // skip writing if rd is $0 - end else if (regwrite) begin - case (opcode) - 6'b100000: begin //lb, load byte - case (vaddr) - 2'b00: memory[writereg] <= {{24{writedata[7]}}, writedata[7:0]}; - 2'b01: memory[writereg] <= {{24{writedata[15]}}, writedata[15:8]}; - 2'b10: memory[writereg] <= {{24{writedata[23]}}, writedata[23:16]}; - 2'b11: memory[writereg] <= {{24{writedata[31]}}, writedata[31:24]}; - endcase // readdata1[1:0] - end - 6'b100100: begin //lbu, load byte unsigned - case (vaddr) - 2'b00: memory[writereg] <= {{24{1'b0}}, writedata[7:0]}; - 2'b01: memory[writereg] <= {{24{1'b0}}, writedata[15:8]}; - 2'b10: memory[writereg] <= {{24{1'b0}}, writedata[23:16]}; - 2'b11: memory[writereg] <= {{24{1'b0}}, writedata[31:24]}; - endcase // readdata1[1:0] - end - 6'b100001: begin //lh, load half-word - case (vaddr) // must be half-word aligned, readdata1[0] = 0 - 2'b00: memory[writereg] <= {{16{writedata[15]}}, writedata[15:0]}; - 2'b10: memory[writereg] <= {{16{writedata[31]}}, writedata[31:16]}; - endcase // readdata1[1:0] - end - 6'b100101: begin //lhu, load half-word unsigned - case (vaddr) // must be half-word aligned, readdata1[0] = 0 - 2'b00: memory[writereg] <= {{16{1'b0}}, writedata[15:0]}; - 2'b10: memory[writereg] <= {{16{1'b0}}, writedata[31:16]}; - endcase // readdata1[1:0] - end - 6'b100010: begin //lwl, load word left - case (vaddr) - 2'b00: memory[writereg][31:24] <= writedata[7:0]; - 2'b01: memory[writereg][31:16] <= writedata[15:0]; - 2'b10: memory[writereg][31:8] <= writedata[23:0]; - 2'b11: memory[writereg][31:0] <= writedata[31:0]; - endcase // readdata1[1:0] - end - 6'b100110: begin //lwr, load word right - case (vaddr) - 2'b00: memory[writereg][31:0] <= writedata[31:0]; - 2'b01: memory[writereg][23:0] <= writedata[31:8]; - 2'b10: memory[writereg][15:0] <= writedata[31:16]; - 2'b11: memory[writereg][7:0] <= writedata[31:24]; - endcase // readdata1[1:0] - end - default: begin - memory[writereg] <= writedata; //most instructions - end - endcase // opcode +always_ff @(posedge rst or negedge clk) begin + if(rst) begin + integer i; //Initialise to zero when reset + for (i = 0; i < 32; i++) begin + memory[i] = 0; + end + end else begin + if (writereg == 5'b00000) begin + // skip writing if rd is $0 + end else if (regwrite) begin + case (opcode) + 6'b100000: begin //lb, load byte + case (vaddr) + 2'b00: memory[writereg] <= {{24{writedata[7]}}, writedata[7:0]}; + 2'b01: memory[writereg] <= {{24{writedata[15]}}, writedata[15:8]}; + 2'b10: memory[writereg] <= {{24{writedata[23]}}, writedata[23:16]}; + 2'b11: memory[writereg] <= {{24{writedata[31]}}, writedata[31:24]}; + endcase // readdata1[1:0] + end + 6'b100100: begin //lbu, load byte unsigned + case (vaddr) + 2'b00: memory[writereg] <= {{24{1'b0}}, writedata[7:0]}; + 2'b01: memory[writereg] <= {{24{1'b0}}, writedata[15:8]}; + 2'b10: memory[writereg] <= {{24{1'b0}}, writedata[23:16]}; + 2'b11: memory[writereg] <= {{24{1'b0}}, writedata[31:24]}; + endcase // readdata1[1:0] + end + 6'b100001: begin //lh, load half-word + case (vaddr) // must be half-word aligned, readdata1[0] = 0 + 2'b00: memory[writereg] <= {{16{writedata[15]}}, writedata[15:0]}; + 2'b10: memory[writereg] <= {{16{writedata[31]}}, writedata[31:16]}; + endcase // readdata1[1:0] + end + 6'b100101: begin //lhu, load half-word unsigned + case (vaddr) // must be half-word aligned, readdata1[0] = 0 + 2'b00: memory[writereg] <= {{16{1'b0}}, writedata[15:0]}; + 2'b10: memory[writereg] <= {{16{1'b0}}, writedata[31:16]}; + endcase // readdata1[1:0] + end + 6'b100010: begin //lwl, load word left + case (vaddr) + 2'b00: memory[writereg][31:24] <= writedata[7:0]; + 2'b01: memory[writereg][31:16] <= writedata[15:0]; + 2'b10: memory[writereg][31:8] <= writedata[23:0]; + 2'b11: memory[writereg][31:0] <= writedata[31:0]; + endcase // readdata1[1:0] + end + 6'b100110: begin //lwr, load word right + case (vaddr) + 2'b00: memory[writereg][31:0] <= writedata[31:0]; + 2'b01: memory[writereg][23:0] <= writedata[31:8]; + 2'b10: memory[writereg][15:0] <= writedata[31:16]; + 2'b11: memory[writereg][7:0] <= writedata[31:24]; + endcase // readdata1[1:0] + end + default: begin + memory[writereg] <= writedata; //most instructions + end + endcase // opcode + end end end diff --git a/testbench/mips_cpu_harvard_tb.sv b/testbench/mips_cpu_harvard_tb.sv index 3f8b6e1..3eb2a3e 100644 --- a/testbench/mips_cpu_harvard_tb.sv +++ b/testbench/mips_cpu_harvard_tb.sv @@ -1,10 +1,13 @@ -module mips_cpu_harvard_tb; +module mips_cpu_harvard_tb( +input logic clk, +input logic reset +); parameter INSTR_INIT_FILE = "inputs/lw/lw-1.instr.txt"; parameter DATA_INIT_FILE = "inputs/lw/lw-1.data.txt"; parameter TIMEOUT_CYCLES = 100; - logic clk, clk_enable, reset, active, data_read, data_write; + logic clk_enable, active, data_read, data_write; logic[31:0] register_v0, instr_address, instr_readdata, data_readdata, data_writedata, data_address; mips_cpu_harvard_memory #(INSTR_INIT_FILE, DATA_INIT_FILE) ramInst( @@ -33,6 +36,7 @@ module mips_cpu_harvard_tb; ); // Generate clock + /* initial begin $dumpfile("mips_cpu_harvard.vcd"); $dumpvars(0,mips_cpu_harvard_tb); @@ -68,4 +72,5 @@ module mips_cpu_harvard_tb; $finish; end + */ endmodule \ No newline at end of file