Update files to remove random Quartus errors

This commit is contained in:
Aadi Desai 2020-12-20 12:43:19 +00:00
parent 7b01ae06eb
commit 711d0df54e
5 changed files with 83 additions and 70 deletions

View file

@ -223,6 +223,8 @@ end
temp_Lo = Lo_in; temp_Lo = Lo_in;
end end
default: begin
end
endcase endcase
end end

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@ -19,12 +19,12 @@ always_comb begin
is_active = 1; is_active = 1;
end else begin end else begin
cpc_curr = cpc_in; cpc_curr = cpc_in;
end
if(cpc_in == 32'd0)begin if(cpc_in == 32'd0)begin
is_active = 0; is_active = 0;
end else begin
is_active = 1;
end
end end
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin

View file

@ -50,6 +50,9 @@ always @(*) begin
2'd2: begin 2'd2: begin
in_writereg = 5'd31;//Link Register 31. in_writereg = 5'd31;//Link Register 31.
end end
default: begin
in_writereg = 5'bxxxxx;
end
endcase endcase
//Picking which output should be written to regfile. //Picking which output should be written to regfile.
@ -69,6 +72,9 @@ always @(*) begin
3'd4:begin 3'd4:begin
in_writedata = (out_ALULo); in_writedata = (out_ALULo);
end end
default: begin
in_writedata = 32'hxxxxxxxx;
end
endcase endcase
//Picking which output should be taken as the second operand for ALU. //Picking which output should be taken as the second operand for ALU.

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@ -13,7 +13,7 @@ input logic[1:0] vaddr, //partial read offset from ALUout
output logic[31:0] regv0 //debug output of $v0 or $2 (third register in file/ first register for returning function results) output logic[31:0] regv0 //debug output of $v0 or $2 (third register in file/ first register for returning function results)
); );
reg[31:0] memory [31:0]; //32 register slots, 32-bits wide logic[31:0] memory [0:31]; //32 register slots, 32-bits wide
initial begin initial begin
integer i; //Initialise to zero by default integer i; //Initialise to zero by default
@ -27,14 +27,13 @@ assign regv0 = memory[2]; //assigning debug $v0 line to $2 of memory
assign readdata1 = memory[readreg1]; //combinatorially output register value based on read port 1 selector assign readdata1 = memory[readreg1]; //combinatorially output register value based on read port 1 selector
assign readdata2 = memory[readreg2]; //combinatorially output register value based on read port 2 selector assign readdata2 = memory[readreg2]; //combinatorially output register value based on read port 2 selector
always_ff @(posedge rst) begin always_ff @(posedge rst or negedge clk) begin
if(rst) begin
integer i; //Initialise to zero when reset integer i; //Initialise to zero when reset
for (i = 0; i < 32; i++) begin for (i = 0; i < 32; i++) begin
memory[i] = 0; memory[i] = 0;
end end
end end else begin
always_ff @(negedge clk) begin
if (writereg == 5'b00000) begin if (writereg == 5'b00000) begin
// skip writing if rd is $0 // skip writing if rd is $0
end else if (regwrite) begin end else if (regwrite) begin
@ -89,5 +88,6 @@ always_ff @(negedge clk) begin
endcase // opcode endcase // opcode
end end
end end
end
endmodule endmodule

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@ -1,10 +1,13 @@
module mips_cpu_harvard_tb; module mips_cpu_harvard_tb(
input logic clk,
input logic reset
);
parameter INSTR_INIT_FILE = "inputs/lw/lw-1.instr.txt"; parameter INSTR_INIT_FILE = "inputs/lw/lw-1.instr.txt";
parameter DATA_INIT_FILE = "inputs/lw/lw-1.data.txt"; parameter DATA_INIT_FILE = "inputs/lw/lw-1.data.txt";
parameter TIMEOUT_CYCLES = 100; parameter TIMEOUT_CYCLES = 100;
logic clk, clk_enable, reset, active, data_read, data_write; logic clk_enable, active, data_read, data_write;
logic[31:0] register_v0, instr_address, instr_readdata, data_readdata, data_writedata, data_address; logic[31:0] register_v0, instr_address, instr_readdata, data_readdata, data_writedata, data_address;
mips_cpu_harvard_memory #(INSTR_INIT_FILE, DATA_INIT_FILE) ramInst( mips_cpu_harvard_memory #(INSTR_INIT_FILE, DATA_INIT_FILE) ramInst(
@ -33,6 +36,7 @@ module mips_cpu_harvard_tb;
); );
// Generate clock // Generate clock
/*
initial begin initial begin
$dumpfile("mips_cpu_harvard.vcd"); $dumpfile("mips_cpu_harvard.vcd");
$dumpvars(0,mips_cpu_harvard_tb); $dumpvars(0,mips_cpu_harvard_tb);
@ -68,4 +72,5 @@ module mips_cpu_harvard_tb;
$finish; $finish;
end end
*/
endmodule endmodule