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Merge pull request #1 from supleed2/Testad3919

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Merge Testad3919 into main
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Aadi Desai 2021-06-13 18:42:15 +01:00 committed by GitHub
parent f2f1dfa80f 24bd7db3a8
commit ddea9f26ca
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61 changed files with 26258 additions and 23490 deletions
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1
Control/.gitignore vendored
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@ -3,3 +3,4 @@
.vscode/c_cpp_properties.json .vscode/c_cpp_properties.json
.vscode/launch.json .vscode/launch.json
.vscode/ipch .vscode/ipch
include/credentials.h

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<!DOCTYPE html>
<html lang='en'>
<head>
<title>Rover Control Panel</title>
<meta charset="utf-8">
<meta name="viewport" content="width=device-width, initial-scale=1">
<link rel="shortcut icon" href="/favicon.ico" type="image/x-icon">
<link rel="icon" href="/favicon.ico" type="image/x-icon">
<style>
* {
box-sizing: border-box;
}
.section_container {
float: left;
width: 50%;
padding: 10px;
}
.flex-container {
display: flex;
flex-wrap: nowrap;
}
ul {
list-style-type: none;
margin: 0;
padding: 0;
}
li {
padding: 0px;
margin-bottom: 0px;
}
:is(h1, h2, h3, h4, h5, h6, label, strong, meter) {
font-family: Arial, Helvetica, sans-serif;
}
.movement_control {
text-align: center;
}
.sensor_data {
text-align: center;
}
meter {
width: 100%;
height: 40px;
transform: translateY(-8px);
}
meter::after {
content: attr(value) attr(title);
top: -28px;
left: 0px;
position: relative;
}
.button {
display: inline-block;
padding: 15px 25px;
font-size: 24px;
cursor: pointer;
text-align: center;
text-decoration: none;
outline: none;
color: rgb(255, 255, 255);
background-color: #161616;
border: none;
border-radius: 15px;
box-shadow: 0 9px rgb(161, 161, 161);
}
.button:hover {
background-color: #585858
}
.button:active {
background-color: #107C10;
box-shadow: 0 5px rgb(161, 161, 161);
transform: translateY(4px);
}
.pressed {
background-color: #107C10;
box-shadow: 0 5px rgb(161, 161, 161);
transform: translateY(4px);
}
.clearfix::after {
content: "";
clear: both;
display: table;
}
</style>
<script>
var connection = new WebSocket('ws://' + location.hostname + ':81/');
var MVM_F_status = 0;
var MVM_L_status = 0;
var MVM_R_status = 0;
var MVM_B_status = 0;
var BTRY_VOLT = 0;
var ODO_DIST = 0;
connection.onmessage = function (event) {
var raw_data = event.data;
console.log(raw_data);
var data = JSON.parse(raw_data);
BTRY_VOLT = data.BTRY_VOLT;
ODO_DIST = data.ODO_DIST;
document.getElementById("btry_meter").value = BTRY_VOLT;
document.getElementById("Odometer").innerHTML = ODO_DIST;
}
function send_data() {
var raw_data = '{"MVM_F":' + MVM_F_status + ',"MVM_L":' + MVM_L_status + ',"MVM_R":' + MVM_R_status + ',"MVM_B":' + MVM_B_status + '}';
connection.send(raw_data);
console.log(raw_data);
}
function left_pressed() {
MVM_L_status = 1;
send_data();
}
function left_unpressed() {
MVM_L_status = 0;
send_data();
}
function up_pressed() {
MVM_F_status = 1;
send_data();
}
function up_unpressed() {
MVM_F_status = 0;
send_data();
}
function right_pressed() {
MVM_R_status = 1;
send_data();
}
function right_unpressed() {
MVM_R_status = 0;
send_data();
}
function down_pressed() {
MVM_B_status = 1;
send_data();
}
function down_unpressed() {
MVM_B_status = 0;
send_data();
}
var timer = null;
function up_mouseDown() {
timer = setInterval(up_pressed, 100);
}
function up_mouseUp() {
clearInterval(timer);
up_unpressed();
}
function down_mouseDown() {
timer = setInterval(down_pressed, 100);
}
function down_mouseUp() {
clearInterval(timer);
down_unpressed();
}
function right_mouseDown() {
timer = setInterval(right_pressed, 100);
}
function right_mouseUp() {
clearInterval(timer);
right_unpressed();
}
function left_mouseDown() {
timer = setInterval(left_pressed, 100);
}
function left_mouseUp() {
clearInterval(timer);
left_unpressed();
}
document.onkeydown = function (e) {
switch (e.keyCode) {
case 37:
document.getElementById("left_arrow").className = "button pressed";
left_pressed();
break;
case 38:
document.getElementById("up_arrow").className = "button pressed";
up_pressed();
break;
case 39:
document.getElementById("right_arrow").className = "button pressed";
right_pressed();
break;
case 40:
document.getElementById("down_arrow").className = "button pressed";
down_pressed();
break;
}
};
document.onkeyup = function (e) {
switch (e.keyCode) {
case 37:
document.getElementById("left_arrow").className = "button";
left_unpressed();
break;
case 38:
document.getElementById("up_arrow").className = "button";
up_unpressed();
break;
case 39:
document.getElementById("right_arrow").className = "button";
right_unpressed();
break;
case 40:
document.getElementById("down_arrow").className = "button";
down_unpressed();
break;
}
};
</script>
</head>
<body>
<h1 style="text-align:center;">ROVER COMMAND CENTER</h1>
<div class="clearfix">
<div class="section_container">
<div class="movement_control">
<h2>Movement Control</h2>
<div style="transform: translateY(0px);">
<button id="up_arrow" onmousedown="up_mouseDown()" onmouseup="up_mouseUp()"
class="button"><span>&#8679;</span></button>
</div>
<div style="transform: translateY(13px);">
<button id="left_arrow" onmousedown="left_mouseDown()" onmouseup="left_mouseUp()"
class="button"><span>&#8678;</span></button>
<button id="down_arrow" onmousedown="down_mouseDown()" onmouseup="down_mouseUp()"
class="button"><span>&#8681;</span></button>
<button id="right_arrow" onmousedown="right_mouseDown()" onmouseup="right_mouseUp()"
class="button"><span>&#8680;</span></button>
</div>
</div>
</div>
<div class="section_container">
<div id="bleh" class="sensor_data">
<h2>Sensor Data</h2>
<ul>
<li>
<div class="section_container">
<label>Battery Voltage</label>
</div>
<div class="section_container">
<meter id="btry_meter" min="4.0" max="6.0" low="4.5" optimum="5.0" high="4.8" value="5.8"
title="V"></meter>
</div>
</li>
<li>
<div class="section_container">
<label>Odometer</label>
</div>
<div class="section_container">
<strong id="Odometer">28</strong><strong>mm</strong>
</div>
</li>
</ul>
</div>
</div>
</div>
</body>
</html>

7
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#ifndef CREDENTIALS_H
#define CREDENTIALS_H
#define WIFI_SSID "SSID_here"
#define WIFI_PW "Password_here"
#endif

21
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#ifndef INSTRUCTION_H
#define INSTRUCTION_H
typedef enum {
INSTR_RESET = -1,
INSTR_STOP,
INSTR_MOVE,
INSTR_CHARGE
} instr_t;
typedef struct instruction
{
int id;
int instr;
int heading;
int distance;
float speed;
int charge;
} RoverInstruction;
#endif

11
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#ifndef CONTROL_STATUS_H
#define CONTROL_STATUS_H
typedef enum {
CS_ERROR = -1,
CS_IDLE,
CS_MOVING,
CS_CHARGING
} ControlStatus_t;
#endif

14
Control/lib/TickerV2/keywords.txt Normal file
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#######################################
# Datatypes (KEYWORD1)
#######################################
Ticker KEYWORD1
#######################################
# Methods and Functions (KEYWORD2)
#######################################
attach KEYWORD2
attach_ms KEYWORD2
once KEYWORD2
detach KEYWORD2

9
Control/lib/TickerV2/library.properties Normal file
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name=TickerV2
version=2.0.0
author=Bert Melis
maintainer=Hristo Gochkov <hristo@espressif.com>
sentence=Allows to call functions with a given interval.
paragraph=
category=Timing
url=
architectures=esp32

58
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/*
Ticker.cpp - esp32 library that calls functions periodically
Copyright (c) 2017 Bert Melis. All rights reserved.
Based on the original work of:
Copyright (c) 2014 Ivan Grokhotkov. All rights reserved.
The original version is part of the esp8266 core for Arduino environment.
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "TickerV2.h"
Ticker::Ticker() :
_timer(nullptr) {}
Ticker::~Ticker() {
detach();
}
void Ticker::_attach_ms(uint32_t milliseconds, bool repeat, callback_with_arg_t callback, uint32_t arg) {
esp_timer_create_args_t _timerConfig;
_timerConfig.arg = reinterpret_cast<void*>(arg);
_timerConfig.callback = callback;
_timerConfig.dispatch_method = ESP_TIMER_TASK;
_timerConfig.name = "Ticker";
if (_timer) {
esp_timer_stop(_timer);
esp_timer_delete(_timer);
}
esp_timer_create(&_timerConfig, &_timer);
if (repeat) {
esp_timer_start_periodic(_timer, milliseconds * 1000ULL);
} else {
esp_timer_start_once(_timer, milliseconds * 1000ULL);
}
}
void Ticker::detach() {
if (_timer) {
esp_timer_stop(_timer);
esp_timer_delete(_timer);
_timer = nullptr;
}
}

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Control/lib/TickerV2/src/TickerV2.h Normal file
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/*
Ticker.h - esp32 library that calls functions periodically
Copyright (c) 2017 Bert Melis. All rights reserved.
Based on the original work of:
Copyright (c) 2014 Ivan Grokhotkov. All rights reserved.
The original version is part of the esp8266 core for Arduino environment.
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef TICKERV2_H
#define TICKERV2_H
extern "C" {
#include "esp_timer.h"
}
class Ticker
{
public:
Ticker();
~Ticker();
typedef void (*callback_t)(void);
typedef void (*callback_with_arg_t)(void*);
void attach(float seconds, callback_t callback)
{
_attach_ms(seconds * 1000, true, reinterpret_cast<callback_with_arg_t>(callback), 0);
}
void attach_ms(uint32_t milliseconds, callback_t callback)
{
_attach_ms(milliseconds, true, reinterpret_cast<callback_with_arg_t>(callback), 0);
}
template<typename TArg>
void attach(float seconds, void (*callback)(TArg), TArg arg)
{
static_assert(sizeof(TArg) <= sizeof(uint32_t), "attach() callback argument size must be <= 4 bytes");
// C-cast serves two purposes:
// static_cast for smaller integer types,
// reinterpret_cast + const_cast for pointer types
uint32_t arg32 = (uint32_t)arg;
_attach_ms(seconds * 1000, true, reinterpret_cast<callback_with_arg_t>(callback), arg32);
}
template<typename TArg>
void attach_ms(uint32_t milliseconds, void (*callback)(TArg), TArg arg)
{
static_assert(sizeof(TArg) <= sizeof(uint32_t), "attach_ms() callback argument size must be <= 4 bytes");
uint32_t arg32 = (uint32_t)arg;
_attach_ms(milliseconds, true, reinterpret_cast<callback_with_arg_t>(callback), arg32);
}
void once(float seconds, callback_t callback)
{
_attach_ms(seconds * 1000, false, reinterpret_cast<callback_with_arg_t>(callback), 0);
}
void once_ms(uint32_t milliseconds, callback_t callback)
{
_attach_ms(milliseconds, false, reinterpret_cast<callback_with_arg_t>(callback), 0);
}
template<typename TArg>
void once(float seconds, void (*callback)(TArg), TArg arg)
{
static_assert(sizeof(TArg) <= sizeof(uint32_t), "attach() callback argument size must be <= 4 bytes");
uint32_t arg32 = (uint32_t)(arg);
_attach_ms(seconds * 1000, false, reinterpret_cast<callback_with_arg_t>(callback), arg32);
}
template<typename TArg>
void once_ms(uint32_t milliseconds, void (*callback)(TArg), TArg arg)
{
static_assert(sizeof(TArg) <= sizeof(uint32_t), "attach_ms() callback argument size must be <= 4 bytes");
uint32_t arg32 = (uint32_t)(arg);
_attach_ms(milliseconds, false, reinterpret_cast<callback_with_arg_t>(callback), arg32);
}
void detach();
bool active();
protected:
void _attach_ms(uint32_t milliseconds, bool repeat, callback_with_arg_t callback, uint32_t arg);
protected:
esp_timer_handle_t _timer;
};
#endif // TICKERV2_H

15
Control/platformio.ini
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@ -14,5 +14,16 @@ board = esp32dev
framework = arduino framework = arduino
monitor_speed = 115200 monitor_speed = 115200
upload_port = COM[3] upload_port = COM[3]
monitor_filters = send_on_enter monitor_filters =
lib_deps = plerup/EspSoftwareSerial@^6.12.6 send_on_enter
esp32_exception_decoder
build_flags =
-DCORE_DEBUG_LEVEL=5
-Wno-unknown-pragmas
build_type = debug
lib_deps =
plerup/EspSoftwareSerial@^6.12.6
me-no-dev/ESP Async WebServer@^1.2.3
me-no-dev/AsyncTCP@^1.1.1
links2004/WebSockets@^2.3.6
bblanchon/ArduinoJson@^6.18.0

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#include <Arduino.h>
#include <ArduinoJson.h>
#include <string>
#define WebSocket 0
int state, totalTripDistance, currentHeading, current_x, current_y, signal_strength, lastCompletedCommand_id; // Info Control ==> Command
float batteryVoltage, batteryLevel, batteryCycles; // Info Control ==> Command
int command_id, mode, reqHeading, reqDistance, reqCharge; // Info Command ==> Control
float reqSpeed; // Info Command ==> Control
void setup() {}
void loop()
{
DynamicJsonDocument rdoc(1024); // receive doc, not sure how big this needs to be
deserializeJson(rdoc, WebSocket); // Take JSON input from WebSocket
state = rdoc["st"]; // State: -1 = Error, 0 = Idle, 1 = Moving, 2 = Charging
batteryVoltage = rdoc["bV"];
batteryLevel = rdoc["bL"];
batteryCycles = rdoc["bC"];
totalTripDistance = rdoc["tD"];
currentHeading = rdoc["cH"];
current_x = rdoc["pos"][0];
current_y = rdoc["pos"][1];
signal_strength = rdoc["rssi"];
lastCompletedCommand_id = rdoc["LCCid"];
// ResetTelemetry / STOP / M 0 50 1 / C %
// [20] Heading: 0, Distance: 50, Speed: 1 / [20] Charging to: ??%
// {"Cid":20,"rH":0,}
DynamicJsonDocument tdoc(1024); // transmit doc, not sure how big this needs to be
tdoc["Cid"] = command_id;
tdoc["mode"] = mode; // Switch (mode):
// -1 = Add to queue, reset x/y/odometer (telemetry data)
// 0 = Stop immediately, clear command cache
// 1 = Normal movement command, added to end of command cache
// 2 = Normal charge command, results in no motion, added to end of command cache
tdoc["rH"] = reqHeading;
tdoc["rD"] = reqDistance;
tdoc["rS"] = reqSpeed;
tdoc["rC"] = reqCharge;
serializeJson(tdoc, WebSocket, WebSocket); // Build JSON and send on UART1
}

41
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#include <Arduino.h>
#include <ArduinoJson.h>
#include <string>
#define RXpin 0 // Define your RX pin here
#define TXpin 0 // Define your TX pin here
void setup()
{
Serial.begin(115200); // Set up hardware UART0 (Connected to USB port)
Serial1.begin(9600, SERIAL_8N1, RXpin, TXpin); // Set up hardware UART1
// Other Drive setup stuff
}
void loop()
{
DynamicJsonDocument rdoc(1024); // receive doc, not sure how big this needs to be
deserializeJson(rdoc, Serial1); // Take JSON input from UART1
int requiredHeading = rdoc["rH"]; // if -1: command in progress, returning requested heading, dist/sp to be ignored
int distance = rdoc["dist"]; // -1 for emergency stop
float speed = rdoc["sp"]; // -1 for emergency stop
int currentHeading = rdoc["cH"];
bool resetDistanceTravelled = rdoc["rstD"];
bool commandComplete = 0;
float powerUsage_mW = 0.0;
int distTravelled_mm = 0;
int current_x = 0;
int current_y = 0;
// Do Drive stuff, set the 5 values above
DynamicJsonDocument tdoc(1024); // transmit doc, not sure how big this needs to be
tdoc["comp"] = commandComplete; // If 0: command in progress, current heading requested
tdoc["mW"] = powerUsage_mW;
tdoc["mm"] = distTravelled_mm;
tdoc["pos"][0] = current_x;
tdoc["pos"][1] = current_y;
serializeJson(tdoc, Serial1); // Build JSON and send on UART1
}

37
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#include <Arduino.h>
#include <ArduinoJson.h>
#include <string>
#define RXpin 0 // Define your RX pin here
#define TXpin 0 // Define your TX pin here
void setup()
{
Serial.begin(115200); // Set up hardware UART0 (Connected to USB port)
Serial1.begin(9600, SERIAL_8N1, RXpin, TXpin); // Set up hardware UART1
// Other Drive setup stuff
}
void loop()
{
bool charge;
DynamicJsonDocument rdoc(1024); // receive doc, not sure how big this needs to be
if(Serial1.available()){
deserializeJson(rdoc, Serial1); // Take JSON input from UART1
charge = rdoc["ch"]; // {"ch":0}
}
float stateOfCharge = 0;
float batteryVoltage = 0;
float batteryCycles = 0;
// Do Drive stuff, set the 5 values above
DynamicJsonDocument tdoc(1024); // transmit doc, not sure how big this needs to be
tdoc["soc"] = stateOfCharge;
tdoc["mV"] = batteryVoltage;
tdoc["cyc"] = batteryCycles;
serializeJson(tdoc, Serial1); // Build JSON and send on UART1
}

49
Control/ref/vision.cpp Normal file
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#include <Arduino.h>
#include <ArduinoJson.h>
#include <string>
const int ARDUINO_IO[16] = {-1/*RX*/, -1/*RX*/, 23, 22, 21, 19, 18, 5, 17, 16, 14, 4, 15, 2, 13, 12}; // Expansion board mapping
#define RXpin ARDUINO_IO[11] // Define your RX pin here
#define TXpin ARDUINO_IO[10] // Define your TX pin here
FILE* SerialUART;
void setup()
{
Serial.begin(115200); // Set up hardware UART0 (Connected to USB port)
}
void loop()
{
int command = getc(SerialUART);
// command char, used for controlling exposure/focus/gain settings:
// e = increase exposure
// d = decrease exposure
// r = increase focus
// f = decrease focus
// t = increase gain
// g = decrease gain
// Bounding Box edges
int bb_left = 0;
int bb_right = 0;
int bb_top = 0;
int bb_bottom = 0;
// Weighted average of detected pixels coordinates
int centre_x = 0;
int centre_y = 0;
// Heading from DE10-Lite magnetometer
float heading = 0.0;
// Build hardcode JSON packet on DE10-Lite using fprintf() as space is minimal and library would be too large.
// fprintf(SerialUART, "{\"bb\":[%d,%d,%d,%d],\"cen\":[%d,%d],\"cH\":%d\"}", bb_left, bb_right, bb_top, bb_bottom, centre_x, centre_y, heading);
DynamicJsonDocument rdoc(1024); // receive doc, not sure how big this needs to be
deserializeJson(rdoc, SerialUART);
bb_left = rdoc["bb"][0];
bb_right = rdoc["bb"][1];
bb_top = rdoc["bb"][2];
bb_bottom = rdoc["bb"][3];
centre_x = rdoc["cen"][0];
centre_y = rdoc["cen"][1];
heading = rdoc["cH"];
}

472
Control/src/main.cpp
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@ -1,61 +1,437 @@
#pragma region Includes
#include <Arduino.h> #include <Arduino.h>
#include <string> #include <string>
#include <SoftwareSerial.h> #include <SoftwareSerial.h>
#include <AsyncTCP.h>
#include <ESPAsyncWebServer.h>
#include <ESPmDNS.h>
#include "TickerV2.h"
#include <WebSocketsServer.h>
#include "credentials.h"
#include <ArduinoJson.h>
#include <SPIFFS.h>
#include "status.h"
#include "instruction.h"
#include <queue>
#pragma endregion
#define RX1pin 14 // Pin 10 on expansion board #pragma region Enable extra debugging info for ESP32
#define TX1pin 4 // Pin 11 on expansion board #undef LOG_LOCAL_LEVEL
#define RX2pin 15 // Pin 12 on expansion board #define LOG_LOCAL_LEVEL ESP_LOG_VERBOSE
#define TX2pin 2 // Pin 13 on expansion board #include "esp_log.h"
#define RX3pin 18 // Pin 6 on expansion board #pragma endregion
#define TX3pin 5 // Pin 7 on expansion board
#define RX4pin 17 // Pin 8 on expansion board
#define TX4pin 16 // Pin 9 on expansion board
void forwardprint1() { #pragma region Definitions eg pins
if(Serial1.available()){ #define RX1pin 18 // Pin 6 on expansion board, UART1
input1 = String(Serial1.readStringUntil('\n')); #define TX1pin 5 // Pin 7 on expansion board, UART1
Serial2.println(input1); #define RX2pin 17 // Pin 8 on expansion board, UART2
} #define TX2pin 16 // Pin 9 on expansion board, UART2
} #define RX3pin 14 // Pin 10 on expansion board, UART3
void forwardprint2() { #define TX3pin 4 // Pin 11 on expansion board, UART3
if(Serial2.available()){ #pragma endregion
input2 = String(Serial2.readStringUntil('\n'));
Serial3.println(input2);
}
}
void forwardprint3() {
if(Serial3.available()){
input3 = String(Serial3.readStringUntil('\n'));
Serial4.println(input3);
}
}
void forwardprint4() {
if(Serial4.available()){
input4 = String(Serial4.readStringUntil('\n'));
Serial.println(input4);
}
}
int counter; #pragma region Function Declarations
String input, input1, input2, input3, input4; void notFound(AsyncWebServerRequest *request);
void webSocketEvent(uint8_t num, WStype_t type, uint8_t *payload, size_t length);
void queueInstruction(RoverInstruction instruction);
void sendToCommand();
void sendToDrive(RoverInstruction instruction);
void recvFromDrive();
void sendToEnergy(bool instruction);
void recvFromEnergy();
void sendToVision();
void recvFromVision();
void emergencyStop();
#pragma endregion
#pragma region Global objects
AsyncWebServer webserver(80);
WebSocketsServer websocketserver(81);
Ticker ticker;
SoftwareSerial Serial3; SoftwareSerial Serial3;
SoftwareSerial Serial4; std::queue<RoverInstruction> InstrQueue;
#pragma endregion
#pragma region Global variables
ControlStatus_t Status;
float batteryVoltage;
float batteryLevel;
float batteryCycles;
int odometer;
int heading;
int xpos, ypos;
int signalStrength;
int lastExecutedCommand, lastCompletedCommand;
bool driveCommandComplete;
int bb_left, bb_right, bb_top, bb_bottom;
int bb_centre_x, bb_centre_y;
float chargeGoal;
#pragma endregion
void setup()
{
esp_log_level_set("*", ESP_LOG_ERROR); // set all components to ERROR level
esp_log_level_set("wifi", ESP_LOG_WARN); // enable WARN logs from WiFi stack
esp_log_level_set("dhcpc", ESP_LOG_INFO); // enable INFO logs from DHCP client
void setup() {
Serial.begin(115200); // Set up hardware UART0 (Connected to USB port) Serial.begin(115200); // Set up hardware UART0 (Connected to USB port)
Serial1.begin(9600, SERIAL_8N1, RX1pin, TX1pin); // Set up hardware UART 1 Serial1.begin(9600, SERIAL_8N1, RX1pin, TX1pin); // Set up hardware UART1 (Connected to Drive)
Serial2.begin(9600, SERIAL_8N1, RX2pin, TX2pin); // Set up hardware UART 2 Serial2.begin(9600, SERIAL_8N1, RX2pin, TX2pin); // Set up hardware UART2 (Connected to Energy)
Serial3.begin(9600, SWSERIAL_8N1, RX3pin, TX3pin); // Set up software UART 3 Serial3.begin(9600, SWSERIAL_8N1, RX3pin, TX3pin); // Set up software UART3 (Connected to Vision)
Serial4.begin(9600, SWSERIAL_8N1, RX4pin, TX4pin); // Set up software UART 4
// Set global variable startup values
Status = CS_IDLE;
batteryVoltage = 0;
batteryLevel = 0;
batteryCycles = 0;
odometer = 0;
heading = 0;
xpos = 0;
ypos = 0;
signalStrength = 0;
lastExecutedCommand = 0;
lastCompletedCommand = 0;
driveCommandComplete = 1;
chargeGoal = 0;
if (!SPIFFS.begin(true)) // Mount SPIFFS
{
Serial.println("SPIFFS failed to mount");
return;
}
Serial.println("SPIFFS mounted");
WiFi.begin(WIFI_SSID, WIFI_PW);
while (WiFi.status() != WL_CONNECTED) // Wait for ESP32 to connect to AP in "credentials.h"
{
delay(500);
}
while (!MDNS.begin("rover")) // Set up mDNS cast at "rover.local/"
{
Serial.println("Error setting up mDNS, retrying in 5s");
delay(5000);
}
Serial.println("mDNS set up, access Control Panel at 'rover.local/'");
webserver.on("/", HTTP_GET, [](AsyncWebServerRequest *request)
{ request->send(SPIFFS, "/index.html", "text/html"); }); // Serve "index.html" at root page
webserver.on("/favicon.ico", HTTP_GET, [](AsyncWebServerRequest *request)
{ request->send(SPIFFS, "/favicon.ico", "image/png"); }); // Serve tab icon
webserver.onNotFound(notFound); // Set up basic 404NotFound page
webserver.begin(); // Start Asynchronous Web Server
websocketserver.begin(); // Start Websocket Server
websocketserver.onEvent(webSocketEvent); // Set up function call when event received from Command
ticker.attach(0.5, sendToCommand); // Set up recurring function to forward rover status to Command
} }
void loop() { void loop()
if(Serial.available()){ {
input = String(Serial.readStringUntil('\n')); websocketserver.loop(); // Handle incoming client connections
Serial1.println(input); recvFromDrive(); // Update stats from Drive
recvFromEnergy(); // Update stats from Energy
recvFromVision(); // Update stats from Vision
switch (Status)
{
case CS_ERROR:
{
Serial.println("Rover in error state, rebooting...");
exit(1);
} }
forwardprint1(); break;
forwardprint2(); case CS_IDLE:
forwardprint3(); {
forwardprint4(); if (!InstrQueue.empty()) // If Rover idle and InstrQueue NOT empty: Do the next command in the queue
{
RoverInstruction *instr = &InstrQueue.front(); // Get next command
switch (instr->instr) // Determine command type
{
case INSTR_RESET: // Reset telemetry values (zeroing position/distance)
{
odometer = 0;
xpos = 0;
ypos = 0;
DynamicJsonDocument tdoc(128);
tdoc["rstD"] = 1;
serializeJson(tdoc, Serial1); // Send reset odometer signal to Drive
}
break;
case INSTR_STOP: // Emergency stop
{
Status = CS_ERROR;
while (1)
{
Serial.println("Emergency Stop should not get queued, hold and print");
delay(1000);
}
}
break;
case INSTR_MOVE: // Normal movement
{
Status = CS_MOVING; // Set moving state
driveCommandComplete = 0;
sendToDrive(*instr); // Forward to Drive handler
}
break;
case INSTR_CHARGE: // Normal charge
{
Status = CS_CHARGING; // Set charging state
chargeGoal = (float)instr->charge; // Set charging goal
sendToEnergy(1); // Forward to Energy handler
}
break;
default:
{
Serial.println("Unknown instruction type in queue, skipping...");
}
break;
}
lastExecutedCommand = instr->id; // Update tracker of last processed command
}
}
break;
case CS_MOVING:
{
if (driveCommandComplete) // If movement command complete:
{
Status = CS_IDLE; // Set rover state back to idle
lastCompletedCommand = lastExecutedCommand; // Update last completed command
}
else // If movement command NOT complete:
{ // Send (up to date) current heading to Drive
DynamicJsonDocument tdoc(128);
tdoc["rH"] = -1;
tdoc["cH"] = heading;
serializeJson(tdoc, Serial1);
}
}
break;
case CS_CHARGING:
{
if (batteryLevel >= chargeGoal) // Compare batteryLevel to chargeGoal
{
Status = CS_IDLE;
lastCompletedCommand = lastExecutedCommand; // Update last completed command
sendToEnergy(0); // Stop charging if goal reached
}
// Otherwise continue charging, no change
}
break;
default:
{
Serial.println("Unknown rover state, exiting...");
exit(1);
}
break;
}
delay(500);
}
void notFound(AsyncWebServerRequest *request)
{
request->send(404, "text/plain", "Page Not found. Check URI/IP address.");
}
void webSocketEvent(uint8_t num, WStype_t type, uint8_t *payload, size_t length)
{
switch (type)
{
case WStype_DISCONNECTED:
{
Serial.printf("Client[%u] Disconnected!\n", num);
}
break;
case WStype_CONNECTED:
{
IPAddress ip = websocketserver.remoteIP(num);
Serial.printf("Client[%u] Connected from %d.%d.%d.%d url: %s\n", num, ip[0], ip[1], ip[2], ip[3], payload);
}
break;
case WStype_TEXT: // MSG received from command panel
{
Serial.printf("Client[%u] sent Text: %s\n", num, payload); // Echo received command to terminal
String command = String((char *)(payload)); // Convert received command to string type
DynamicJsonDocument rdoc(200); // Create instance of DynamicJsonDocument on heap, 200 Bytes
DeserializationError error = deserializeJson(rdoc, command); // Convert command string to JSONDocument and capture any errors
if (error)
{
Serial.print("deserializeJson() failed: ");
Serial.println(error.c_str());
return;
}
RoverInstruction instr;
int mode = rdoc["mode"];
switch (mode)
{
case -1: // Add to queue, reset x/y/odometer (telemetry data)
{
Serial.println("Reset telemetry command received");
instr.id = rdoc["Cid"];
instr.instr = INSTR_RESET;
// Ignore rdoc["rH"], rdoc["rD"], rdoc["rS"], rdoc["rC"]
queueInstruction(instr); // Put reset command in InstrQueue
}
break;
case 0: // Stop immediately, clear command cache
{
Serial.println("Emergency stop command received");
// instr.instr = INSTR_STOP; // Not needed as Emergency Stop is not queued
// Ignore rdoc["Cid"], rdoc["rH"], rdoc["rD"], rdoc["rS"], rdoc["rC"]
emergencyStop();
}
break;
case 1: // Normal movement command, added to end of command cache
{
Serial.println("Normal movement command received");
instr.id = rdoc["Cid"];
instr.instr = INSTR_MOVE;
instr.heading = rdoc["rH"];
instr.distance = rdoc["rD"];
instr.speed = rdoc["rS"];
// Ignore rdoc["rC"]
queueInstruction(instr); // Put movement command in InstrQueue
}
break;
case 2: // Normal charge command, results in no motion, added to end of command cache
{
Serial.println("Normal charge command received");
instr.id = rdoc["Cid"];
instr.instr = INSTR_CHARGE;
instr.charge = rdoc["rC"];
// Ignore rdoc["rH"], rdoc["rD"], rdoc["rS"]
queueInstruction(instr); // Put charge command in InstrQueue
}
break;
default:
{
// Default case, print and continue
Serial.println("Unknown Command type received, ignoring");
// Ignore rdoc["Cid"], rdoc["rH"], rdoc["rD"], rdoc["rS"], rdoc["rC"]
}
break;
}
}
break;
case WStype_PONG:
{
Serial.println("Websocket keep-alive PONG");
}
break;
default:
{
Serial.println(String("Websocket received invalid event type: ") + type + String(", exiting"));
exit(1);
}
break;
}
}
void queueInstruction(RoverInstruction instruction)
{
InstrQueue.push(instruction);
}
void sendToCommand()
{
DynamicJsonDocument tdoc(1024);
tdoc["st"] = Status;
tdoc["bV"] = batteryVoltage;
tdoc["bL"] = batteryLevel;
tdoc["bC"] = batteryCycles;
tdoc["tD"] = odometer;
tdoc["cH"] = heading;
tdoc["pos"][0] = xpos;
tdoc["pos"][1] = ypos;
tdoc["rssi"] = signalStrength;
tdoc["LCCid"] = lastCompletedCommand;
String JSON_Data;
serializeJson(tdoc, JSON_Data);
websocketserver.broadcastTXT(JSON_Data);
}
void sendToDrive(RoverInstruction instruction)
{
DynamicJsonDocument tdoc(1024);
tdoc["rH"] = instruction.heading;
tdoc["dist"] = instruction.distance;
tdoc["sp"] = instruction.speed;
tdoc["cH"] = heading;
serializeJson(tdoc, Serial1);
}
void recvFromDrive() // Update telemetry data and state info from Drive packet
{
if (Serial1.available()) // Check for input from UART1 (Connected to Drive)
{
DynamicJsonDocument rdoc(1024);
deserializeJson(rdoc, Serial1);
driveCommandComplete = rdoc["comp"];
odometer = rdoc["mm"];
xpos = rdoc["pos"][0];
ypos = rdoc["pos"][1];
}
}
void sendToEnergy(bool instruction)
{
DynamicJsonDocument tdoc(128);
tdoc["ch"] = instruction; // Start charging
serializeJson(tdoc, Serial2);
}
void recvFromEnergy() // Update telemetry data and state info from Energy packet
{
if (Serial2.available()) // Check for input from UART2 (Connected to Energy)
{
DynamicJsonDocument rdoc(1024);
deserializeJson(rdoc, Serial2);
batteryLevel = rdoc["soc"];
batteryVoltage = rdoc["mV"];
batteryCycles = rdoc["cyc"];
}
}
void sendToVision()
{
Serial3.print("R"); // Request new data from Vision
}
void recvFromVision() // Update bounding box and obstacle detection data from Vision packet
{
if (Serial3.available()) // Check for input from UART3 (Connected to Vision)
{
DynamicJsonDocument rdoc(1024);
deserializeJson(rdoc, Serial3);
bb_left = rdoc["bb"][0];
bb_right = rdoc["bb"][1];
bb_top = rdoc["bb"][2];
bb_bottom = rdoc["bb"][3];
bb_centre_x = rdoc["cen"][0];
bb_centre_y = rdoc["cen"][1];
heading = rdoc["cH"];
}
}
void emergencyStop()
{
DynamicJsonDocument tdoc(1024);
tdoc["rH"] = heading;
tdoc["dist"] = -1;
tdoc["sp"] = -1;
tdoc["cH"] = heading;
serializeJson(tdoc, Serial1); // Send stop signals to Drive
sendToEnergy(0); // Send stop signal to Energy
while (InstrQueue.size())
{
InstrQueue.pop(); // Clear Instruction Queue
}
Status = CS_IDLE; // Reset rover to idle state
Serial.println("Instruction Queue cleared");
} }

113
Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys.xml
View file

@ -781,7 +781,7 @@
<delegate id="delegate_CommonDockStationFactory"> <delegate id="delegate_CommonDockStationFactory">
<root>true</root> <root>true</root>
<content delegate="flap dock"> <content delegate="flap dock">
<window auto="true" direction="NORTH"/> <window auto="true" direction="SOUTH"/>
<placeholders> <placeholders>
<version>0</version> <version>0</version>
<format>dock.PlaceholderList</format> <format>dock.PlaceholderList</format>
@ -827,7 +827,7 @@
<fullscreen-action>false</fullscreen-action> <fullscreen-action>false</fullscreen-action>
<node nodeId="1372710005721" orientation="HORIZONTAL" divider="0.22181146025878004"> <node nodeId="1372710005721" orientation="HORIZONTAL" divider="0.22181146025878004">
<node nodeId="1375985011088" orientation="VERTICAL" divider="0.504054054054054"> <node nodeId="1375985011088" orientation="VERTICAL" divider="0.504054054054054">
<leaf id="2" nodeId="1375985003630"> <leaf id="1" nodeId="1375985003630">
<placeholders> <placeholders>
<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder> <placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
<placeholder>dock.single.IP\ Catalog</placeholder> <placeholder>dock.single.IP\ Catalog</placeholder>
@ -853,7 +853,7 @@
</entry> </entry>
</placeholder-map> </placeholder-map>
</leaf> </leaf>
<leaf id="1" nodeId="1375985011087"> <leaf id="0" nodeId="1375985011087">
<placeholders> <placeholders>
<placeholder>dock.single.Hierarchy</placeholder> <placeholder>dock.single.Hierarchy</placeholder>
</placeholders> </placeholders>
@ -878,9 +878,9 @@
</leaf> </leaf>
</node> </node>
<node nodeId="1372710005725" orientation="VERTICAL" divider="0.8051001821493625"> <node nodeId="1372710005725" orientation="VERTICAL" divider="0.8051001821493625">
<node nodeId="1372710005727" orientation="HORIZONTAL" divider="0.8413566475001963"> <node nodeId="1372710005727" orientation="HORIZONTAL" divider="0.7178845934919044">
<node nodeId="1372710005733" orientation="VERTICAL" divider="0.75"> <node nodeId="1372710005733" orientation="VERTICAL" divider="0.75">
<leaf id="3" nodeId="1372710005735"> <leaf id="2" nodeId="1372710005735">
<placeholders> <placeholders>
<placeholder>dock.single.Connections</placeholder> <placeholder>dock.single.Connections</placeholder>
<placeholder>dock.single.System\ Contents</placeholder> <placeholder>dock.single.System\ Contents</placeholder>
@ -897,12 +897,18 @@
<placeholder>dock.single.Interconnect\ Requirements</placeholder> <placeholder>dock.single.Interconnect\ Requirements</placeholder>
<placeholder>dock.single.Instrumentation</placeholder> <placeholder>dock.single.Instrumentation</placeholder>
<placeholder>dock.single.Instance\ Parameters</placeholder> <placeholder>dock.single.Instance\ Parameters</placeholder>
<placeholder>dock.single.Address\ Map</placeholder>
<placeholder>dock.single.Domains</placeholder> <placeholder>dock.single.Domains</placeholder>
</placeholders> </placeholders>
<placeholder-map> <placeholder-map>
<version>0</version> <version>0</version>
<format>dock.PlaceholderList</format> <format>dock.PlaceholderList</format>
<entry>
<key shared="false">
<placeholder>dock.single.System\ Contents</placeholder>
</key>
<item key="convert" type="b">true</item>
<item key="convert-keys" type="a"/>
</entry>
<entry> <entry>
<key shared="false"> <key shared="false">
<placeholder>dock.single.Address\ Map</placeholder> <placeholder>dock.single.Address\ Map</placeholder>
@ -965,7 +971,7 @@
</leaf> </leaf>
</node> </node>
</node> </node>
<leaf id="0" nodeId="1372710005745"> <leaf id="3" nodeId="1372710005745">
<placeholders> <placeholders>
<placeholder>dock.single.Messages</placeholder> <placeholder>dock.single.Messages</placeholder>
<placeholder>dock.single.Generation\ Messages</placeholder> <placeholder>dock.single.Generation\ Messages</placeholder>
@ -996,16 +1002,6 @@
</layout> </layout>
</adjacent> </adjacent>
<children ignore="false"> <children ignore="false">
<child>
<layout factory="predefined" placeholder="dock.single.Messages">
<replacement id="dockablesingle Messages"/>
<delegate id="delegate_ccontrol backup factory id">
<id>Messages</id>
<area/>
</delegate>
</layout>
<children ignore="false"/>
</child>
<child> <child>
<layout factory="delegate_StackDockStationFactory"> <layout factory="delegate_StackDockStationFactory">
<selected>0</selected> <selected>0</selected>
@ -1183,6 +1179,16 @@
</child> </child>
</children> </children>
</child> </child>
<child>
<layout factory="predefined" placeholder="dock.single.Messages">
<replacement id="dockablesingle Messages"/>
<delegate id="delegate_ccontrol backup factory id">
<id>Messages</id>
<area/>
</delegate>
</layout>
<children ignore="false"/>
</child>
<child> <child>
<layout factory="predefined" placeholder="dock.single.Parameters"> <layout factory="predefined" placeholder="dock.single.Parameters">
<replacement id="dockablesingle Parameters"/> <replacement id="dockablesingle Parameters"/>
@ -1611,21 +1617,9 @@
</entry> </entry>
<entry id="single Address Map" current="dock.mode.normal"> <entry id="single Address Map" current="dock.mode.normal">
<history> <history>
<mode>dock.mode.maximized</mode>
<mode>dock.mode.normal</mode> <mode>dock.mode.normal</mode>
</history> </history>
<properties> <properties>
<property id="dock.mode.maximized">
<mode>dock.mode.maximized</mode>
<root>ccontrol center</root>
<location>
<property factory="SplitDockFullScreenPropertyFactory"/>
<property factory="StackDockPropertyFactory">
<index>1</index>
<placeholder>dock.single.Address\ Map</placeholder>
</property>
</location>
</property>
<property id="dock.mode.normal"> <property id="dock.mode.normal">
<mode>dock.mode.normal</mode> <mode>dock.mode.normal</mode>
<root>ccontrol center</root> <root>ccontrol center</root>
@ -1633,9 +1627,10 @@
<property factory="SplitDockPlaceholderProperty"> <property factory="SplitDockPlaceholderProperty">
<placeholder>dock.single.Address\ Map</placeholder> <placeholder>dock.single.Address\ Map</placeholder>
<backup-path> <backup-path>
<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/> <node location="RIGHT" size="0.8" id="1372710005721"/>
<node location="TOP" size="0.8051001821493625" id="1372710005725"/> <node location="TOP" size="0.75" id="1372710005725"/>
<node location="LEFT" size="0.8413566475001963" id="1372710005727"/> <node location="LEFT" size="0.75" id="1372710005727"/>
<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
<node location="TOP" size="0.75" id="1372710005733"/> <node location="TOP" size="0.75" id="1372710005733"/>
<leaf id="1372710005735"/> <leaf id="1372710005735"/>
</backup-path> </backup-path>
@ -1852,21 +1847,9 @@
</entry> </entry>
<entry id="single System Contents" current="dock.mode.normal"> <entry id="single System Contents" current="dock.mode.normal">
<history> <history>
<mode>dock.mode.maximized</mode>
<mode>dock.mode.normal</mode> <mode>dock.mode.normal</mode>
</history> </history>
<properties> <properties>
<property id="dock.mode.maximized">
<mode>dock.mode.maximized</mode>
<root>ccontrol center</root>
<location>
<property factory="SplitDockFullScreenPropertyFactory"/>
<property factory="StackDockPropertyFactory">
<index>0</index>
<placeholder>dock.single.System\ Contents</placeholder>
</property>
</location>
</property>
<property id="dock.mode.normal"> <property id="dock.mode.normal">
<mode>dock.mode.normal</mode> <mode>dock.mode.normal</mode>
<root>ccontrol center</root> <root>ccontrol center</root>
@ -1874,9 +1857,10 @@
<property factory="SplitDockPlaceholderProperty"> <property factory="SplitDockPlaceholderProperty">
<placeholder>dock.single.System\ Contents</placeholder> <placeholder>dock.single.System\ Contents</placeholder>
<backup-path> <backup-path>
<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/> <node location="RIGHT" size="0.8" id="1372710005721"/>
<node location="TOP" size="0.8051001821493625" id="1372710005725"/> <node location="TOP" size="0.75" id="1372710005725"/>
<node location="LEFT" size="0.8413566475001963" id="1372710005727"/> <node location="LEFT" size="0.75" id="1372710005727"/>
<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
<node location="TOP" size="0.75" id="1372710005733"/> <node location="TOP" size="0.75" id="1372710005733"/>
<leaf id="1372710005735"/> <leaf id="1372710005735"/>
</backup-path> </backup-path>
@ -1892,21 +1876,9 @@
<entry id="single Interconnect Requirements" current="dock.mode.normal"> <entry id="single Interconnect Requirements" current="dock.mode.normal">
<history> <history>
<mode>dock.mode.minimized</mode> <mode>dock.mode.minimized</mode>
<mode>dock.mode.maximized</mode>
<mode>dock.mode.normal</mode> <mode>dock.mode.normal</mode>
</history> </history>
<properties> <properties>
<property id="dock.mode.maximized">
<mode>dock.mode.maximized</mode>
<root>ccontrol center</root>
<location>
<property factory="SplitDockFullScreenPropertyFactory"/>
<property factory="StackDockPropertyFactory">
<index>2</index>
<placeholder>dock.single.Interconnect\ Requirements</placeholder>
</property>
</location>
</property>
<property id="dock.mode.minimized"> <property id="dock.mode.minimized">
<mode>dock.mode.minimized</mode> <mode>dock.mode.minimized</mode>
<root>ccontrol north</root> <root>ccontrol north</root>
@ -1927,8 +1899,8 @@
<placeholder>dock.single.Interconnect\ Requirements</placeholder> <placeholder>dock.single.Interconnect\ Requirements</placeholder>
<backup-path> <backup-path>
<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/> <node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
<node location="TOP" size="0.8051001821493625" id="1372710005725"/> <node location="TOP" size="0.75" id="1372710005725"/>
<node location="LEFT" size="0.8413566475001963" id="1372710005727"/> <node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
<node location="TOP" size="0.75" id="1372710005733"/> <node location="TOP" size="0.75" id="1372710005733"/>
<leaf id="1372710005735"/> <leaf id="1372710005735"/>
</backup-path> </backup-path>
@ -2168,7 +2140,24 @@
</entry> </entry>
</dockables> </dockables>
<modes> <modes>
<entry id="dock.mode.maximized"/> <entry id="dock.mode.maximized">
<maximized>
<item id="ccontrol center">
<mode>dock.mode.normal</mode>
<location>
<mode>dock.mode.normal</mode>
<root>ccontrol center</root>
<location>
<property factory="SplitDockPathProperty">
<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
<node location="TOP" size="0.504054054054054" id="1375985011088"/>
<leaf id="1375985003630"/>
</property>
</location>
</location>
</item>
</maximized>
</entry>
</modes> </modes>
</modes> </modes>
</current> </current>

58
Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys_schematic.nlv
View file

@ -15,45 +15,45 @@ preplace inst Qsys.TERASIC_CAMERA_0 -pg 1 -lvl 4 -y 740
preplace inst Qsys.mipi_reset_n -pg 1 -lvl 8 -y 1190 preplace inst Qsys.mipi_reset_n -pg 1 -lvl 8 -y 1190
preplace inst Qsys.alt_vip_vfb_0 -pg 1 -lvl 5 -y 620 preplace inst Qsys.alt_vip_vfb_0 -pg 1 -lvl 5 -y 620
preplace inst Qsys -pg 1 -lvl 1 -y 40 -regy -20 preplace inst Qsys -pg 1 -lvl 1 -y 40 -regy -20
preplace inst Qsys.uart_interface_0 -pg 1 -lvl 2 -y 330 preplace inst Qsys.EEE_IMGPROC_0 -pg 1 -lvl 7 -y 700
preplace inst Qsys.EEE_IMGPROC_0 -pg 1 -lvl 7 -y 600
preplace inst Qsys.timer -pg 1 -lvl 8 -y 440 preplace inst Qsys.timer -pg 1 -lvl 8 -y 440
preplace inst Qsys.mipi_pwdn_n -pg 1 -lvl 8 -y 1090 preplace inst Qsys.mipi_pwdn_n -pg 1 -lvl 8 -y 1090
preplace inst Qsys.key -pg 1 -lvl 8 -y 620 preplace inst Qsys.key -pg 1 -lvl 8 -y 620
preplace inst Qsys.uart_0 -pg 1 -lvl 3 -y 720
preplace inst Qsys.sw -pg 1 -lvl 8 -y 1290 preplace inst Qsys.sw -pg 1 -lvl 8 -y 1290
preplace inst Qsys.TERASIC_AUTO_FOCUS_0 -pg 1 -lvl 6 -y 560 preplace inst Qsys.TERASIC_AUTO_FOCUS_0 -pg 1 -lvl 6 -y 560
preplace inst Qsys.nios2_gen2.cpu -pg 1 preplace inst Qsys.nios2_gen2.cpu -pg 1
preplace inst Qsys.nios2_gen2 -pg 1 -lvl 2 -y 520 preplace inst Qsys.nios2_gen2 -pg 1 -lvl 2 -y 550
preplace inst Qsys.i2c_opencores_mipi -pg 1 -lvl 8 -y 170 preplace inst Qsys.i2c_opencores_mipi -pg 1 -lvl 8 -y 170
preplace netloc EXPORT<net_container>Qsys</net_container>(MASTER)altpll_0.c1,(MASTER)Qsys.clk_sdram) 1 3 6 NJ 280 NJ 280 NJ 280 NJ 280 NJ 300 NJ preplace netloc INTERCONNECT<net_container>Qsys</net_container>(SLAVE)sysid_qsys.reset,(SLAVE)onchip_memory2_0.reset1,(SLAVE)timer.reset,(SLAVE)key.reset,(SLAVE)sw.reset,(SLAVE)altpll_0.inclk_interface_reset,(SLAVE)i2c_opencores_camera.clock_reset,(SLAVE)TERASIC_AUTO_FOCUS_0.reset,(SLAVE)i2c_opencores_mipi.clock_reset,(SLAVE)mipi_reset_n.reset,(SLAVE)jtag_uart.reset,(SLAVE)alt_vip_itc_0.is_clk_rst_reset,(SLAVE)sdram.reset,(SLAVE)led.reset,(SLAVE)TERASIC_CAMERA_0.clock_reset_reset,(SLAVE)nios2_gen2.reset,(SLAVE)alt_vip_vfb_0.reset,(SLAVE)EEE_IMGPROC_0.reset,(MASTER)nios2_gen2.debug_reset_request,(SLAVE)mipi_pwdn_n.reset,(SLAVE)uart_0.reset,(MASTER)clk_50.clk_reset) 1 1 7 430 750 830 850 1190 830 1670 730 1890 770 2110 910 2700
preplace netloc INTERCONNECT<net_container>Qsys</net_container>(SLAVE)sysid_qsys.control_slave,(SLAVE)timer.s1,(MASTER)nios2_gen2.instruction_master,(SLAVE)jtag_uart.avalon_jtag_slave,(SLAVE)altpll_0.pll_slave,(SLAVE)nios2_gen2.debug_mem_slave,(SLAVE)led.s1,(SLAVE)EEE_IMGPROC_0.s1,(SLAVE)mipi_pwdn_n.s1,(SLAVE)i2c_opencores_mipi.avalon_slave_0,(MASTER)nios2_gen2.data_master,(SLAVE)TERASIC_AUTO_FOCUS_0.mm_ctrl,(SLAVE)sw.s1,(SLAVE)i2c_opencores_camera.avalon_slave_0,(SLAVE)onchip_memory2_0.s1,(SLAVE)mipi_reset_n.s1,(SLAVE)key.s1) 1 1 7 450 420 850 810 NJ 710 NJ 710 1910 730 2190 770 2580 preplace netloc FAN_OUT<net_container>Qsys</net_container>(SLAVE)key.clk,(SLAVE)i2c_opencores_camera.clock,(SLAVE)nios2_gen2.clk,(SLAVE)uart_0.clk,(MASTER)clk_50.clk,(SLAVE)jtag_uart.clk,(SLAVE)onchip_memory2_0.clk1,(SLAVE)altpll_0.inclk_interface,(SLAVE)i2c_opencores_mipi.clock,(SLAVE)sw.clk,(SLAVE)mipi_reset_n.clk,(SLAVE)sysid_qsys.clk,(SLAVE)led.clk,(SLAVE)mipi_pwdn_n.clk,(SLAVE)timer.clk) 1 1 7 410 450 930 400 NJ 400 NJ 400 NJ 400 NJ 400 2660
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)i2c_opencores_camera.export,(SLAVE)Qsys.i2c_opencores_camera_export) 1 0 8 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)i2c_opencores_camera.export,(SLAVE)Qsys.i2c_opencores_camera_export) 1 0 8 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)led.external_connection,(SLAVE)Qsys.led_external_connection) 1 0 8 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)sdram.wire,(SLAVE)Qsys.sdram_wire) 1 0 8 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.eee_imgproc_0_conduit_mode,(SLAVE)EEE_IMGPROC_0.conduit_mode) 1 0 7 NJ 300 NJ 300 NJ 410 NJ 410 NJ 410 NJ 410 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.eee_imgproc_0_conduit_mode,(SLAVE)EEE_IMGPROC_0.conduit_mode) 1 0 7 NJ 490 NJ 490 NJ 550 NJ 550 NJ 550 NJ 550 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.altpll_0_locked_conduit,(SLAVE)altpll_0.locked_conduit) 1 0 3 NJ 280 NJ 280 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(MASTER)Qsys.clk_sdram,(MASTER)altpll_0.c1) 1 3 6 NJ 220 NJ 220 NJ 220 NJ 220 NJ 160 NJ
preplace netloc FAN_OUT<net_container>Qsys</net_container>(SLAVE)mipi_pwdn_n.clk,(SLAVE)i2c_opencores_camera.clock,(SLAVE)key.clk,(SLAVE)onchip_memory2_0.clk1,(MASTER)clk_50.clk,(SLAVE)jtag_uart.clk,(SLAVE)mipi_reset_n.clk,(SLAVE)nios2_gen2.clk,(SLAVE)sysid_qsys.clk,(SLAVE)altpll_0.inclk_interface,(SLAVE)i2c_opencores_mipi.clock,(SLAVE)led.clk,(SLAVE)sw.clk,(SLAVE)timer.clk,(SLAVE)uart_interface_0.clock) 1 1 7 410 320 950 380 NJ 340 NJ 300 NJ 300 NJ 300 2640 preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)TERASIC_CAMERA_0.conduit_end,(SLAVE)Qsys.terasic_camera_0_conduit_end) 1 0 4 NJ 430 NJ 430 NJ 470 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.sdram_wire,(SLAVE)sdram.wire) 1 0 8 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)mipi_pwdn_n.external_connection,(SLAVE)Qsys.mipi_pwdn_n_external_connection) 1 0 8 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)mipi_pwdn_n.external_connection,(SLAVE)Qsys.mipi_pwdn_n_external_connection) 1 0 8 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ
preplace netloc FAN_OUT<net_container>Qsys</net_container>(SLAVE)sdram.clk,(SLAVE)alt_vip_itc_0.is_clk_rst,(MASTER)altpll_0.c2,(SLAVE)TERASIC_CAMERA_0.clock_reset,(SLAVE)TERASIC_AUTO_FOCUS_0.clock,(SLAVE)EEE_IMGPROC_0.clock,(SLAVE)alt_vip_vfb_0.clock) 1 3 5 1250 300 1670 730 1870 690 2150 860 2600 preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.clk,(SLAVE)clk_50.clk_in) 1 0 1 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.uart_interface_0_conduit_end,(SLAVE)uart_interface_0.conduit_end) 1 0 2 NJ 360 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)altpll_0.areset_conduit,(SLAVE)Qsys.altpll_0_areset_conduit) 1 0 3 NJ 260 NJ 260 NJ
preplace netloc POINT_TO_POINT<net_container>Qsys</net_container>(MASTER)EEE_IMGPROC_0.avalon_streaming_source,(SLAVE)alt_vip_itc_0.din) 1 7 1 2600 preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.key_external_connection,(SLAVE)key.external_connection) 1 0 8 NJ 370 NJ 370 NJ 450 NJ 450 NJ 450 NJ 450 NJ 650 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.terasic_auto_focus_0_conduit,(SLAVE)TERASIC_AUTO_FOCUS_0.Conduit) 1 0 6 NJ 460 NJ 460 NJ 570 NJ 570 NJ 570 NJ preplace netloc POINT_TO_POINT<net_container>Qsys</net_container>(MASTER)EEE_IMGPROC_0.avalon_streaming_source,(SLAVE)alt_vip_itc_0.din) 1 7 1 2620
preplace netloc FAN_OUT<net_container>Qsys</net_container>(SLAVE)i2c_opencores_mipi.interrupt_sender,(SLAVE)i2c_opencores_camera.interrupt_sender,(SLAVE)jtag_uart.irq,(MASTER)nios2_gen2.irq,(SLAVE)timer.irq) 1 2 6 NJ 870 NJ 870 NJ 790 NJ 790 NJ 790 2620 preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.led_external_connection,(SLAVE)led.external_connection) 1 0 8 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)key.external_connection,(SLAVE)Qsys.key_external_connection) 1 0 8 NJ 710 NJ 710 NJ 830 NJ 730 NJ 770 NJ 750 NJ 750 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.uart_0_rx_tx,(SLAVE)uart_0.external_connection) 1 0 3 NJ 510 NJ 510 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.terasic_auto_focus_0_conduit,(SLAVE)TERASIC_AUTO_FOCUS_0.Conduit) 1 0 6 NJ 690 NJ 690 NJ 690 NJ 690 NJ 570 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.i2c_opencores_mipi_export,(SLAVE)i2c_opencores_mipi.export) 1 0 8 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.i2c_opencores_mipi_export,(SLAVE)i2c_opencores_mipi.export) 1 0 8 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.alt_vip_itc_0_clocked_video,(SLAVE)alt_vip_itc_0.clocked_video) 1 0 8 NJ 890 NJ 890 NJ 890 NJ 890 NJ 820 NJ 820 NJ 820 NJ preplace netloc FAN_OUT<net_container>Qsys</net_container>(MASTER)nios2_gen2.irq,(SLAVE)jtag_uart.irq,(SLAVE)i2c_opencores_mipi.interrupt_sender,(SLAVE)uart_0.irq,(SLAVE)timer.irq,(SLAVE)i2c_opencores_camera.interrupt_sender) 1 2 6 950 530 NJ 530 NJ 530 NJ 530 NJ 670 2620
preplace netloc POINT_TO_POINT<net_container>Qsys</net_container>(SLAVE)TERASIC_AUTO_FOCUS_0.din,(MASTER)alt_vip_vfb_0.dout) 1 5 1 1890 preplace netloc FAN_OUT<net_container>Qsys</net_container>(MASTER)altpll_0.c2,(SLAVE)EEE_IMGPROC_0.clock,(SLAVE)sdram.clk,(SLAVE)TERASIC_CAMERA_0.clock_reset,(SLAVE)alt_vip_itc_0.is_clk_rst,(SLAVE)TERASIC_AUTO_FOCUS_0.clock,(SLAVE)alt_vip_vfb_0.clock) 1 3 5 1190 730 1630 710 1910 730 2150 890 2680
preplace netloc FAN_IN<net_container>Qsys</net_container>(SLAVE)sdram.s1,(MASTER)alt_vip_vfb_0.write_master,(MASTER)alt_vip_vfb_0.read_master) 1 5 3 1890 960 NJ 960 NJ preplace netloc POINT_TO_POINT<net_container>Qsys</net_container>(SLAVE)EEE_IMGPROC_0.avalon_streaming_sink,(MASTER)TERASIC_AUTO_FOCUS_0.dout) 1 6 1 2110
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)clk_50.clk_in,(SLAVE)Qsys.clk) 1 0 1 NJ preplace netloc INTERCONNECT<net_container>Qsys</net_container>(SLAVE)i2c_opencores_mipi.avalon_slave_0,(SLAVE)nios2_gen2.debug_mem_slave,(SLAVE)jtag_uart.avalon_jtag_slave,(SLAVE)led.s1,(MASTER)nios2_gen2.instruction_master,(SLAVE)mipi_reset_n.s1,(SLAVE)onchip_memory2_0.s1,(SLAVE)uart_0.s1,(SLAVE)sysid_qsys.control_slave,(SLAVE)sw.s1,(SLAVE)altpll_0.pll_slave,(SLAVE)mipi_pwdn_n.s1,(SLAVE)TERASIC_AUTO_FOCUS_0.mm_ctrl,(SLAVE)timer.s1,(SLAVE)i2c_opencores_camera.avalon_slave_0,(SLAVE)key.s1,(MASTER)nios2_gen2.data_master,(SLAVE)EEE_IMGPROC_0.s1) 1 1 7 430 470 890 710 NJ 710 NJ 610 1870 790 2170 690 2580
preplace netloc POINT_TO_POINT<net_container>Qsys</net_container>(SLAVE)EEE_IMGPROC_0.avalon_streaming_sink,(MASTER)TERASIC_AUTO_FOCUS_0.dout) 1 6 1 N
preplace netloc POINT_TO_POINT<net_container>Qsys</net_container>(SLAVE)alt_vip_vfb_0.din,(MASTER)TERASIC_CAMERA_0.avalon_streaming_source) 1 4 1 1630
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)sw.external_connection,(SLAVE)Qsys.sw_external_connection) 1 0 8 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)sw.external_connection,(SLAVE)Qsys.sw_external_connection) 1 0 8 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.mipi_reset_n_external_connection,(SLAVE)mipi_reset_n.external_connection) 1 0 8 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.mipi_reset_n_external_connection,(SLAVE)mipi_reset_n.external_connection) 1 0 8 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(MASTER)altpll_0.c3,(MASTER)Qsys.clk_vga) 1 3 6 NJ 320 NJ 320 NJ 320 NJ 320 NJ 320 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(MASTER)altpll_0.c4,(MASTER)Qsys.d8m_xclkin) 1 3 6 NJ 380 NJ 380 NJ 380 NJ 280 NJ 320 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.altpll_0_areset_conduit,(SLAVE)altpll_0.areset_conduit) 1 0 3 NJ 260 NJ 260 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(MASTER)altpll_0.c3,(MASTER)Qsys.clk_vga) 1 3 6 NJ 320 NJ 320 NJ 320 NJ 260 NJ 300 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(MASTER)Qsys.d8m_xclkin,(MASTER)altpll_0.c4) 1 3 6 NJ 220 NJ 220 NJ 220 NJ 220 NJ 160 NJ preplace netloc POINT_TO_POINT<net_container>Qsys</net_container>(MASTER)TERASIC_CAMERA_0.avalon_streaming_source,(SLAVE)alt_vip_vfb_0.din) 1 4 1 1650
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.terasic_camera_0_conduit_end,(SLAVE)TERASIC_CAMERA_0.conduit_end) 1 0 4 NJ 480 NJ 480 NJ 790 NJ preplace netloc POINT_TO_POINT<net_container>Qsys</net_container>(MASTER)alt_vip_vfb_0.dout,(SLAVE)TERASIC_AUTO_FOCUS_0.din) 1 5 1 1890
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.reset,(SLAVE)clk_50.clk_in_reset) 1 0 1 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.reset,(SLAVE)clk_50.clk_in_reset) 1 0 1 NJ
preplace netloc INTERCONNECT<net_container>Qsys</net_container>(SLAVE)sw.reset,(SLAVE)timer.reset,(SLAVE)onchip_memory2_0.reset1,(SLAVE)key.reset,(SLAVE)alt_vip_vfb_0.reset,(SLAVE)uart_interface_0.reset,(SLAVE)mipi_pwdn_n.reset,(SLAVE)i2c_opencores_camera.clock_reset,(SLAVE)led.reset,(SLAVE)TERASIC_AUTO_FOCUS_0.reset,(SLAVE)TERASIC_CAMERA_0.clock_reset_reset,(MASTER)clk_50.clk_reset,(SLAVE)jtag_uart.reset,(MASTER)nios2_gen2.debug_reset_request,(SLAVE)EEE_IMGPROC_0.reset,(SLAVE)sysid_qsys.reset,(SLAVE)alt_vip_itc_0.is_clk_rst_reset,(SLAVE)sdram.reset,(SLAVE)nios2_gen2.reset,(SLAVE)i2c_opencores_mipi.clock_reset,(SLAVE)altpll_0.inclk_interface_reset,(SLAVE)mipi_reset_n.reset) 1 1 7 430 440 910 850 1290 690 1690 750 1930 710 2170 880 2680 preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)altpll_0.locked_conduit,(SLAVE)Qsys.altpll_0_locked_conduit) 1 0 3 NJ 320 NJ 320 NJ
levelinfo -pg 1 0 200 3000 preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)alt_vip_itc_0.clocked_video,(SLAVE)Qsys.alt_vip_itc_0_clocked_video) 1 0 8 NJ 870 NJ 870 NJ 870 NJ 870 NJ 870 NJ 870 NJ 870 NJ
levelinfo -hier Qsys 210 240 590 1020 1340 1720 2020 2320 2750 2900 preplace netloc FAN_IN<net_container>Qsys</net_container>(MASTER)alt_vip_vfb_0.write_master,(MASTER)alt_vip_vfb_0.read_master,(SLAVE)sdram.s1) 1 5 3 1850 960 NJ 960 NJ
levelinfo -pg 1 0 200 3040
levelinfo -hier Qsys 210 240 590 980 1300 1700 1980 2320 2790 2940

7
Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/preferences.xml
View file

@ -3,12 +3,13 @@
<debug showDebugMenu="0" /> <debug showDebugMenu="0" />
<systemtable filter="All Interfaces"> <systemtable filter="All Interfaces">
<columns> <columns>
<connections preferredWidth="319" /> <connections preferredWidth="143" />
<irq preferredWidth="34" /> <irq preferredWidth="34" />
<name preferredWidth="201" /> <name preferredWidth="201" />
<export preferredWidth="267" /> <export preferredWidth="267" />
</columns> </columns>
</systemtable> </systemtable>
<library expandedCategories="Library,Project" /> <library
<window width="1694" height="929" x="136" y="110" /> expandedCategories="Project,Library/Interface Protocols,Library,Library/Interface Protocols/Serial" />
<window width="1936" height="1063" x="0" y="0" />
</preferences> </preferences>

BIN
Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.qws
View file

Binary file not shown.

10
Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.v
View file

@ -178,14 +178,8 @@ Qsys u0 (
.eee_imgproc_0_conduit_mode_new_signal (SW[0]), .eee_imgproc_0_conduit_mode_new_signal (SW[0]),
// .uart_interface_0_conduit_end_rx (ARDUINO_IO[13]), // input from ESP32 RX2pin .uart_0_rx_tx_rxd (ARDUINO_IO[1]), // uart_0_rx_tx.rxd
// .uart_interface_0_conduit_end_rx_data (), // output [7:0] .uart_0_rx_tx_txd (ARDUINO_IO[0]) //
// .uart_interface_0_conduit_end_rx_valid (), // output
//
// .uart_interface_0_conduit_end_tx (ARDUINO_IO[12]), // output to ESP32 TX2pin
// .uart_interface_0_conduit_end_tx_data (), // input [7:0]
// .uart_interface_0_conduit_end_tx_transmit (), // input
// .uart_interface_0_conduit_end_tx_ready () // output
); );
FpsMonitor uFps( FpsMonitor uFps(

13
Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP_time_limited.cdf
View file

@ -1,13 +0,0 @@
/* Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(10M50DAF484) Path("C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/") File("DE10_LITE_D8M_VIP_time_limited.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

BIN
Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP_time_limited.sof
View file

Binary file not shown.

131
Vision/DE10_LITE_D8M_VIP_16/Qsys.qsys
View file

@ -13,9 +13,14 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "19"; value = "18";
type = "int"; type = "int";
} }
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
} }
element Qsys element Qsys
{ {
@ -45,9 +50,14 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "16"; value = "17";
type = "int"; type = "int";
} }
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
} }
element TERASIC_AUTO_FOCUS_0.mm_ctrl element TERASIC_AUTO_FOCUS_0.mm_ctrl
{ {
@ -61,38 +71,58 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "13"; value = "14";
type = "int"; type = "int";
} }
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
} }
element alt_vip_itc_0 element alt_vip_itc_0
{ {
datum _sortIndex datum _sortIndex
{ {
value = "17"; value = "19";
type = "int"; type = "int";
} }
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
} }
element alt_vip_vfb_0 element alt_vip_vfb_0
{ {
datum _sortIndex datum _sortIndex
{ {
value = "14"; value = "16";
type = "int"; type = "int";
} }
datum megawizard_uipreferences datum megawizard_uipreferences
{ {
value = "{output_directory=F:\\Board_Proj\\D8M\\DE10_LITE_D8M_VIP, output_language=VERILOG}"; value = "{output_directory=F:\\Ed\\Stuff\\EEE2Rover\\DE10_LITE_D8M_VIP_16, output_language=VERILOG}";
type = "String"; type = "String";
} }
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
} }
element altpll_0 element altpll_0
{ {
datum _sortIndex datum _sortIndex
{ {
value = "18"; value = "20";
type = "int"; type = "int";
} }
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
} }
element altpll_0.pll_slave element altpll_0.pll_slave
{ {
@ -114,7 +144,7 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "5"; value = "6";
type = "int"; type = "int";
} }
} }
@ -130,7 +160,7 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "4"; value = "5";
type = "int"; type = "int";
} }
} }
@ -162,7 +192,7 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "8"; value = "9";
type = "int"; type = "int";
} }
} }
@ -178,7 +208,7 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "6"; value = "7";
type = "int"; type = "int";
} }
} }
@ -194,7 +224,7 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "10"; value = "11";
type = "int"; type = "int";
} }
} }
@ -210,7 +240,7 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "9"; value = "10";
type = "int"; type = "int";
} }
} }
@ -261,6 +291,11 @@
value = "15"; value = "15";
type = "int"; type = "int";
} }
datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
} }
element sdram.s1 element sdram.s1
{ {
@ -274,7 +309,7 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "7"; value = "8";
type = "int"; type = "int";
} }
} }
@ -290,7 +325,7 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "11"; value = "12";
type = "int"; type = "int";
} }
} }
@ -306,7 +341,7 @@
{ {
datum _sortIndex datum _sortIndex
{ {
value = "12"; value = "13";
type = "int"; type = "int";
} }
} }
@ -318,6 +353,14 @@
type = "String"; type = "String";
} }
} }
element uart_0
{
datum _sortIndex
{
value = "4";
type = "int";
}
}
} }
]]></parameter> ]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" /> <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
@ -424,6 +467,11 @@
internal="TERASIC_CAMERA_0.conduit_end" internal="TERASIC_CAMERA_0.conduit_end"
type="conduit" type="conduit"
dir="end" /> dir="end" />
<interface
name="uart_0_rx_tx"
internal="uart_0.external_connection"
type="conduit"
dir="end" />
<module name="EEE_IMGPROC_0" kind="EEE_IMGPROC" version="1.0" enabled="1" /> <module name="EEE_IMGPROC_0" kind="EEE_IMGPROC" version="1.0" enabled="1" />
<module <module
name="TERASIC_AUTO_FOCUS_0" name="TERASIC_AUTO_FOCUS_0"
@ -767,7 +815,7 @@
<parameter name="dataAddrWidth" value="19" /> <parameter name="dataAddrWidth" value="19" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" /> <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" /> <parameter name="dataMasterHighPerformanceMapParam" value="" />
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='onchip_memory2_0.s1' start='0x20000' end='0x386A0' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_gen2.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='timer.s1' start='0x41000' end='0x41020' type='altera_avalon_timer.s1' /><slave name='TERASIC_AUTO_FOCUS_0.mm_ctrl' start='0x41020' end='0x41040' type='TERASIC_AUTO_FOCUS.mm_ctrl' /><slave name='i2c_opencores_camera.avalon_slave_0' start='0x41040' end='0x41060' type='i2c_opencores.avalon_slave_0' /><slave name='i2c_opencores_mipi.avalon_slave_0' start='0x41060' end='0x41080' type='i2c_opencores.avalon_slave_0' /><slave name='mipi_pwdn_n.s1' start='0x41080' end='0x41090' type='altera_avalon_pio.s1' /><slave name='mipi_reset_n.s1' start='0x41090' end='0x410A0' type='altera_avalon_pio.s1' /><slave name='key.s1' start='0x410A0' end='0x410B0' type='altera_avalon_pio.s1' /><slave name='sw.s1' start='0x410B0' end='0x410C0' type='altera_avalon_pio.s1' /><slave name='led.s1' start='0x410C0' end='0x410D0' type='altera_avalon_pio.s1' /><slave name='altpll_0.pll_slave' start='0x410D0' end='0x410E0' type='altpll.pll_slave' /><slave name='sysid_qsys.control_slave' start='0x410E0' end='0x410E8' type='altera_avalon_sysid_qsys.control_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x410E8' end='0x410F0' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='EEE_IMGPROC_0.s1' start='0x42000' end='0x42020' type='EEE_IMGPROC.s1' /></address-map>]]></parameter> <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_gen2.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='timer.s1' start='0x41000' end='0x41020' type='altera_avalon_timer.s1' /><slave name='TERASIC_AUTO_FOCUS_0.mm_ctrl' start='0x41020' end='0x41040' type='TERASIC_AUTO_FOCUS.mm_ctrl' /><slave name='i2c_opencores_camera.avalon_slave_0' start='0x41040' end='0x41060' type='i2c_opencores.avalon_slave_0' /><slave name='i2c_opencores_mipi.avalon_slave_0' start='0x41060' end='0x41080' type='i2c_opencores.avalon_slave_0' /><slave name='mipi_pwdn_n.s1' start='0x41080' end='0x41090' type='altera_avalon_pio.s1' /><slave name='mipi_reset_n.s1' start='0x41090' end='0x410A0' type='altera_avalon_pio.s1' /><slave name='key.s1' start='0x410A0' end='0x410B0' type='altera_avalon_pio.s1' /><slave name='sw.s1' start='0x410B0' end='0x410C0' type='altera_avalon_pio.s1' /><slave name='led.s1' start='0x410C0' end='0x410D0' type='altera_avalon_pio.s1' /><slave name='altpll_0.pll_slave' start='0x410D0' end='0x410E0' type='altpll.pll_slave' /><slave name='sysid_qsys.control_slave' start='0x410E0' end='0x410E8' type='altera_avalon_sysid_qsys.control_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x410E8' end='0x410F0' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='EEE_IMGPROC_0.s1' start='0x42000' end='0x42020' type='EEE_IMGPROC.s1' /><slave name='uart_0.s1' start='0x42020' end='0x42040' type='altera_avalon_uart.s1' /></address-map>]]></parameter>
<parameter name="data_master_high_performance_paddr_base" value="0" /> <parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" /> <parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" /> <parameter name="data_master_paddr_base" value="0" />
@ -806,14 +854,14 @@
<parameter name="icache_tagramBlockType" value="Automatic" /> <parameter name="icache_tagramBlockType" value="Automatic" />
<parameter name="impl" value="Fast" /> <parameter name="impl" value="Fast" />
<parameter name="instAddrWidth" value="19" /> <parameter name="instAddrWidth" value="19" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='onchip_memory2_0.s1' start='0x20000' end='0x386A0' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_gen2.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter> <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_gen2.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
<parameter name="instructionMasterHighPerformanceAddrWidth" value="1" /> <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
<parameter name="instructionMasterHighPerformanceMapParam" value="" /> <parameter name="instructionMasterHighPerformanceMapParam" value="" />
<parameter name="instruction_master_high_performance_paddr_base" value="0" /> <parameter name="instruction_master_high_performance_paddr_base" value="0" />
<parameter name="instruction_master_high_performance_paddr_size" value="0" /> <parameter name="instruction_master_high_performance_paddr_size" value="0" />
<parameter name="instruction_master_paddr_base" value="0" /> <parameter name="instruction_master_paddr_base" value="0" />
<parameter name="instruction_master_paddr_size" value="0" /> <parameter name="instruction_master_paddr_size" value="0" />
<parameter name="internalIrqMaskSystemInfo" value="15" /> <parameter name="internalIrqMaskSystemInfo" value="31" />
<parameter name="io_regionbase" value="0" /> <parameter name="io_regionbase" value="0" />
<parameter name="io_regionsize" value="0" /> <parameter name="io_regionsize" value="0" />
<parameter name="master_addr_map" value="false" /> <parameter name="master_addr_map" value="false" />
@ -945,7 +993,7 @@
<parameter name="initMemContent" value="false" /> <parameter name="initMemContent" value="false" />
<parameter name="initializationFileName" value="onchip_mem.hex" /> <parameter name="initializationFileName" value="onchip_mem.hex" />
<parameter name="instanceID" value="NONE" /> <parameter name="instanceID" value="NONE" />
<parameter name="memorySize" value="100000" /> <parameter name="memorySize" value="131072" />
<parameter name="readDuringWriteMode" value="DONT_CARE" /> <parameter name="readDuringWriteMode" value="DONT_CARE" />
<parameter name="resetrequest_enabled" value="true" /> <parameter name="resetrequest_enabled" value="true" />
<parameter name="simAllowMRAMContentsFile" value="false" /> <parameter name="simAllowMRAMContentsFile" value="false" />
@ -1019,6 +1067,22 @@
<parameter name="timeoutPulseOutput" value="false" /> <parameter name="timeoutPulseOutput" value="false" />
<parameter name="watchdogPulse" value="2" /> <parameter name="watchdogPulse" value="2" />
</module> </module>
<module name="uart_0" kind="altera_avalon_uart" version="16.1" enabled="1">
<parameter name="baud" value="115200" />
<parameter name="clockRate" value="50000000" />
<parameter name="dataBits" value="8" />
<parameter name="fixedBaud" value="true" />
<parameter name="parity" value="NONE" />
<parameter name="simCharStream" value="" />
<parameter name="simInteractiveInputEnable" value="false" />
<parameter name="simInteractiveOutputEnable" value="false" />
<parameter name="simTrueBaud" value="false" />
<parameter name="stopBits" value="1" />
<parameter name="syncRegDepth" value="2" />
<parameter name="useCtsRts" value="false" />
<parameter name="useEopRegister" value="false" />
<parameter name="useRelativePathForSimFile" value="false" />
</module>
<connection <connection
kind="avalon" kind="avalon"
version="16.1" version="16.1"
@ -1154,6 +1218,15 @@
<parameter name="baseAddress" value="0x00042000" /> <parameter name="baseAddress" value="0x00042000" />
<parameter name="defaultConnection" value="false" /> <parameter name="defaultConnection" value="false" />
</connection> </connection>
<connection
kind="avalon"
version="16.1"
start="nios2_gen2.data_master"
end="uart_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00042020" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection <connection
kind="avalon" kind="avalon"
version="16.1" version="16.1"
@ -1245,6 +1318,7 @@
<connection kind="clock" version="16.1" start="clk_50.clk" end="mipi_reset_n.clk" /> <connection kind="clock" version="16.1" start="clk_50.clk" end="mipi_reset_n.clk" />
<connection kind="clock" version="16.1" start="clk_50.clk" end="mipi_pwdn_n.clk" /> <connection kind="clock" version="16.1" start="clk_50.clk" end="mipi_pwdn_n.clk" />
<connection kind="clock" version="16.1" start="clk_50.clk" end="nios2_gen2.clk" /> <connection kind="clock" version="16.1" start="clk_50.clk" end="nios2_gen2.clk" />
<connection kind="clock" version="16.1" start="clk_50.clk" end="uart_0.clk" />
<connection <connection
kind="clock" kind="clock"
version="16.1" version="16.1"
@ -1293,6 +1367,13 @@
end="timer.irq"> end="timer.irq">
<parameter name="irqNumber" value="3" /> <parameter name="irqNumber" value="3" />
</connection> </connection>
<connection
kind="interrupt"
version="16.1"
start="nios2_gen2.irq"
end="uart_0.irq">
<parameter name="irqNumber" value="4" />
</connection>
<connection <connection
kind="reset" kind="reset"
version="16.1" version="16.1"
@ -1371,6 +1452,11 @@
version="16.1" version="16.1"
start="clk_50.clk_reset" start="clk_50.clk_reset"
end="EEE_IMGPROC_0.reset" /> end="EEE_IMGPROC_0.reset" />
<connection
kind="reset"
version="16.1"
start="clk_50.clk_reset"
end="uart_0.reset" />
<connection <connection
kind="reset" kind="reset"
version="16.1" version="16.1"
@ -1461,6 +1547,11 @@
version="16.1" version="16.1"
start="nios2_gen2.debug_reset_request" start="nios2_gen2.debug_reset_request"
end="EEE_IMGPROC_0.reset" /> end="EEE_IMGPROC_0.reset" />
<connection
kind="reset"
version="16.1"
start="nios2_gen2.debug_reset_request"
end="uart_0.reset" />
<connection <connection
kind="reset" kind="reset"
version="16.1" version="16.1"

1071
Vision/DE10_LITE_D8M_VIP_16/Qsys.sopcinfo
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File diff suppressed because it is too large Load diff

37
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.bsf
View file

@ -21,9 +21,9 @@ agreement for further details.
*/ */
(header "symbol" (version "1.1")) (header "symbol" (version "1.1"))
(symbol (symbol
(rect 0 0 576 1072) (rect 0 0 576 1128)
(text "Qsys" (rect 273 -1 295 11)(font "Arial" (font_size 10))) (text "Qsys" (rect 273 -1 295 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 1056 20 1068)(font "Arial" )) (text "inst" (rect 8 1112 20 1124)(font "Arial" ))
(port (port
(pt 0 72) (pt 0 72)
(input) (input)
@ -108,6 +108,13 @@ agreement for further details.
(text "terasic_camera_0_conduit_end_PIXCLK" (rect 4 1029 214 1040)(font "Arial" (font_size 8))) (text "terasic_camera_0_conduit_end_PIXCLK" (rect 4 1029 214 1040)(font "Arial" (font_size 8)))
(line (pt 0 1040)(pt 240 1040)(line_width 1)) (line (pt 0 1040)(pt 240 1040)(line_width 1))
) )
(port
(pt 0 1080)
(input)
(text "uart_0_rx_tx_rxd" (rect 0 0 71 12)(font "Arial" (font_size 8)))
(text "uart_0_rx_tx_rxd" (rect 4 1069 100 1080)(font "Arial" (font_size 8)))
(line (pt 0 1080)(pt 240 1080)(line_width 1))
)
(port (port
(pt 0 88) (pt 0 88)
(output) (output)
@ -269,6 +276,13 @@ agreement for further details.
(text "sdram_wire_we_n" (rect 4 829 94 840)(font "Arial" (font_size 8))) (text "sdram_wire_we_n" (rect 4 829 94 840)(font "Arial" (font_size 8)))
(line (pt 0 840)(pt 240 840)(line_width 1)) (line (pt 0 840)(pt 240 840)(line_width 1))
) )
(port
(pt 0 1096)
(output)
(text "uart_0_rx_tx_txd" (rect 0 0 70 12)(font "Arial" (font_size 8)))
(text "uart_0_rx_tx_txd" (rect 4 1085 100 1096)(font "Arial" (font_size 8)))
(line (pt 0 1096)(pt 240 1096)(line_width 1))
)
(port (port
(pt 0 400) (pt 0 400)
(bidir) (bidir)
@ -380,11 +394,14 @@ agreement for further details.
(text "FVAL" (rect 245 1003 514 2016)(font "Arial" (color 0 0 0))) (text "FVAL" (rect 245 1003 514 2016)(font "Arial" (color 0 0 0)))
(text "LVAL" (rect 245 1019 514 2048)(font "Arial" (color 0 0 0))) (text "LVAL" (rect 245 1019 514 2048)(font "Arial" (color 0 0 0)))
(text "PIXCLK" (rect 245 1035 526 2080)(font "Arial" (color 0 0 0))) (text "PIXCLK" (rect 245 1035 526 2080)(font "Arial" (color 0 0 0)))
(text " Qsys " (rect 550 1056 1136 2122)(font "Arial" )) (text "uart_0_rx_tx" (rect 166 1051 404 2115)(font "Arial" (color 128 0 0)(font_size 9)))
(text "rxd" (rect 245 1075 508 2160)(font "Arial" (color 0 0 0)))
(text "txd" (rect 245 1091 508 2192)(font "Arial" (color 0 0 0)))
(text " Qsys " (rect 550 1112 1136 2234)(font "Arial" ))
(line (pt 240 32)(pt 336 32)(line_width 1)) (line (pt 240 32)(pt 336 32)(line_width 1))
(line (pt 336 32)(pt 336 1056)(line_width 1)) (line (pt 336 32)(pt 336 1112)(line_width 1))
(line (pt 240 1056)(pt 336 1056)(line_width 1)) (line (pt 240 1112)(pt 336 1112)(line_width 1))
(line (pt 240 32)(pt 240 1056)(line_width 1)) (line (pt 240 32)(pt 240 1112)(line_width 1))
(line (pt 241 52)(pt 241 204)(line_width 1)) (line (pt 241 52)(pt 241 204)(line_width 1))
(line (pt 242 52)(pt 242 204)(line_width 1)) (line (pt 242 52)(pt 242 204)(line_width 1))
(line (pt 241 220)(pt 241 244)(line_width 1)) (line (pt 241 220)(pt 241 244)(line_width 1))
@ -423,9 +440,11 @@ agreement for further details.
(line (pt 242 900)(pt 242 956)(line_width 1)) (line (pt 242 900)(pt 242 956)(line_width 1))
(line (pt 241 972)(pt 241 1044)(line_width 1)) (line (pt 241 972)(pt 241 1044)(line_width 1))
(line (pt 242 972)(pt 242 1044)(line_width 1)) (line (pt 242 972)(pt 242 1044)(line_width 1))
(line (pt 241 1060)(pt 241 1100)(line_width 1))
(line (pt 242 1060)(pt 242 1100)(line_width 1))
(line (pt 0 0)(pt 576 0)(line_width 1)) (line (pt 0 0)(pt 576 0)(line_width 1))
(line (pt 576 0)(pt 576 1072)(line_width 1)) (line (pt 576 0)(pt 576 1128)(line_width 1))
(line (pt 0 1072)(pt 576 1072)(line_width 1)) (line (pt 0 1128)(pt 576 1128)(line_width 1))
(line (pt 0 0)(pt 0 1072)(line_width 1)) (line (pt 0 0)(pt 0 1128)(line_width 1))
) )
) )

4
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.cmp
View file

@ -41,7 +41,9 @@
terasic_camera_0_conduit_end_D : in std_logic_vector(11 downto 0) := (others => 'X'); -- D terasic_camera_0_conduit_end_D : in std_logic_vector(11 downto 0) := (others => 'X'); -- D
terasic_camera_0_conduit_end_FVAL : in std_logic := 'X'; -- FVAL terasic_camera_0_conduit_end_FVAL : in std_logic := 'X'; -- FVAL
terasic_camera_0_conduit_end_LVAL : in std_logic := 'X'; -- LVAL terasic_camera_0_conduit_end_LVAL : in std_logic := 'X'; -- LVAL
terasic_camera_0_conduit_end_PIXCLK : in std_logic := 'X' -- PIXCLK terasic_camera_0_conduit_end_PIXCLK : in std_logic := 'X'; -- PIXCLK
uart_0_rx_tx_rxd : in std_logic := 'X'; -- rxd
uart_0_rx_tx_txd : out std_logic -- txd
); );
end component Qsys; end component Qsys;

266
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.html
View file

@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table> </table>
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">2021.05.27.17:50:16</td> <td class="l">2021.06.03.15:09:34</td>
<td class="r">Datasheet</td> <td class="r">Datasheet</td>
</tr> </tr>
</table> </table>
@ -137,7 +137,10 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</a> altera_avalon_sysid_qsys 16.1 </a> altera_avalon_sysid_qsys 16.1
<br/>&#160;&#160; <br/>&#160;&#160;
<a href="#module_timer"><b>timer</b> <a href="#module_timer"><b>timer</b>
</a> altera_avalon_timer 16.1</span> </a> altera_avalon_timer 16.1
<br/>&#160;&#160;
<a href="#module_uart_0"><b>uart_0</b>
</a> altera_avalon_uart 16.1</span>
</div> </div>
</div> </div>
<div style="width:100% ; height:10px"> </div> <div style="width:100% ; height:10px"> </div>
@ -432,6 +435,23 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<td class="addr"><span style="color:#989898">0x</span>00041000</td> <td class="addr"><span style="color:#989898">0x</span>00041000</td>
<td class="empty"></td> <td class="empty"></td>
</tr> </tr>
<tr>
<td class="slavemodule">&#160;
<a href="#module_uart_0"><b>uart_0</b>
</a>
</td>
<td class="empty"></td>
<td class="empty"></td>
<td class="empty"></td>
<td class="empty"></td>
</tr>
<tr>
<td class="slaveb">s1&#160;</td>
<td class="empty"></td>
<td class="empty"></td>
<td class="addr"><span style="color:#989898">0x</span>00042020</td>
<td class="empty"></td>
</tr>
</table> </table>
<a name="module_EEE_IMGPROC_0"> </a> <a name="module_EEE_IMGPROC_0"> </a>
<div> <div>
@ -3115,7 +3135,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<a href="#module_clk_50">clk_50</a> <a href="#module_clk_50">clk_50</a>
</td> </td>
<td class="from">clk&#160;&#160;</td> <td class="from">clk&#160;&#160;</td>
<td class="main" rowspan="93">nios2_gen2</td> <td class="main" rowspan="100">nios2_gen2</td>
</tr> </tr>
<tr> <tr>
<td class="to">&#160;&#160;clk</td> <td class="to">&#160;&#160;clk</td>
@ -3530,6 +3550,42 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<tr style="height:6px"> <tr style="height:6px">
<td></td> <td></td>
</tr> </tr>
<tr>
<td></td>
<td></td>
<td class="from">data_master&#160;&#160;</td>
<td class="neighbor" rowspan="6">
<a href="#module_uart_0">uart_0</a>
</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">&#160;&#160;s1</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">irq&#160;&#160;</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">&#160;&#160;irq</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">debug_reset_request&#160;&#160;</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">&#160;&#160;reset</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
<tr> <tr>
<td></td> <td></td>
<td></td> <td></td>
@ -4282,7 +4338,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">instSlaveMapParam</td> <td class="parametername">instSlaveMapParam</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x386A0' type='altera_avalon_onchip_memory2.s1' /&gt;&lt;slave name='nios2_gen2.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;/address-map&gt;</td> <td class="parametervalue">&lt;address-map&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' type='altera_avalon_onchip_memory2.s1' /&gt;&lt;slave name='nios2_gen2.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;/address-map&gt;</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">faSlaveMapParam</td> <td class="parametername">faSlaveMapParam</td>
@ -4290,7 +4346,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">dataSlaveMapParam</td> <td class="parametername">dataSlaveMapParam</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x386A0' type='altera_avalon_onchip_memory2.s1' /&gt;&lt;slave name='nios2_gen2.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='timer.s1' start='0x41000' end='0x41020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='TERASIC_AUTO_FOCUS_0.mm_ctrl' start='0x41020' end='0x41040' type='TERASIC_AUTO_FOCUS.mm_ctrl' /&gt;&lt;slave name='i2c_opencores_camera.avalon_slave_0' start='0x41040' end='0x41060' type='i2c_opencores.avalon_slave_0' /&gt;&lt;slave name='i2c_opencores_mipi.avalon_slave_0' start='0x41060' end='0x41080' type='i2c_opencores.avalon_slave_0' /&gt;&lt;slave name='mipi_pwdn_n.s1' start='0x41080' end='0x41090' type='altera_avalon_pio.s1' /&gt;&lt;slave name='mipi_reset_n.s1' start='0x41090' end='0x410A0' type='altera_avalon_pio.s1' /&gt;&lt;slave name='key.s1' start='0x410A0' end='0x410B0' type='altera_avalon_pio.s1' /&gt;&lt;slave name='sw.s1' start='0x410B0' end='0x410C0' type='altera_avalon_pio.s1' /&gt;&lt;slave name='led.s1' start='0x410C0' end='0x410D0' type='altera_avalon_pio.s1' /&gt;&lt;slave name='altpll_0.pll_slave' start='0x410D0' end='0x410E0' type='altpll.pll_slave' /&gt;&lt;slave name='sysid_qsys.control_slave' start='0x410E0' end='0x410E8' type='altera_avalon_sysid_qsys.control_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x410E8' end='0x410F0' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;slave name='EEE_IMGPROC_0.s1' start='0x42000' end='0x42020' type='EEE_IMGPROC.s1' /&gt;&lt;/address-map&gt;</td> <td class="parametervalue">&lt;address-map&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' type='altera_avalon_onchip_memory2.s1' /&gt;&lt;slave name='nios2_gen2.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='timer.s1' start='0x41000' end='0x41020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='TERASIC_AUTO_FOCUS_0.mm_ctrl' start='0x41020' end='0x41040' type='TERASIC_AUTO_FOCUS.mm_ctrl' /&gt;&lt;slave name='i2c_opencores_camera.avalon_slave_0' start='0x41040' end='0x41060' type='i2c_opencores.avalon_slave_0' /&gt;&lt;slave name='i2c_opencores_mipi.avalon_slave_0' start='0x41060' end='0x41080' type='i2c_opencores.avalon_slave_0' /&gt;&lt;slave name='mipi_pwdn_n.s1' start='0x41080' end='0x41090' type='altera_avalon_pio.s1' /&gt;&lt;slave name='mipi_reset_n.s1' start='0x41090' end='0x410A0' type='altera_avalon_pio.s1' /&gt;&lt;slave name='key.s1' start='0x410A0' end='0x410B0' type='altera_avalon_pio.s1' /&gt;&lt;slave name='sw.s1' start='0x410B0' end='0x410C0' type='altera_avalon_pio.s1' /&gt;&lt;slave name='led.s1' start='0x410C0' end='0x410D0' type='altera_avalon_pio.s1' /&gt;&lt;slave name='altpll_0.pll_slave' start='0x410D0' end='0x410E0' type='altpll.pll_slave' /&gt;&lt;slave name='sysid_qsys.control_slave' start='0x410E0' end='0x410E8' type='altera_avalon_sysid_qsys.control_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x410E8' end='0x410F0' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;slave name='EEE_IMGPROC_0.s1' start='0x42000' end='0x42020' type='EEE_IMGPROC.s1' /&gt;&lt;slave name='uart_0.s1' start='0x42020' end='0x42040' type='altera_avalon_uart.s1' /&gt;&lt;/address-map&gt;</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">tightlyCoupledDataMaster0MapParam</td> <td class="parametername">tightlyCoupledDataMaster0MapParam</td>
@ -4342,7 +4398,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">internalIrqMaskSystemInfo</td> <td class="parametername">internalIrqMaskSystemInfo</td>
<td class="parametervalue">15</td> <td class="parametervalue">31</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">customInstSlavesSystemInfo</td> <td class="parametername">customInstSlavesSystemInfo</td>
@ -4632,7 +4688,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">memorySize</td> <td class="parametername">memorySize</td>
<td class="parametervalue">100000</td> <td class="parametervalue">131072</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">readDuringWriteMode</td> <td class="parametername">readDuringWriteMode</td>
@ -4793,7 +4849,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">SIZE_VALUE</td> <td class="parametername">SIZE_VALUE</td>
<td class="parametervalue">100000</td> <td class="parametervalue">131072</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">WRITABLE</td> <td class="parametername">WRITABLE</td>
@ -5358,7 +5414,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">timestamp</td> <td class="parametername">timestamp</td>
<td class="parametervalue">1622134216</td> <td class="parametervalue">1622729373</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">deviceFamily</td> <td class="parametername">deviceFamily</td>
@ -5383,7 +5439,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">TIMESTAMP</td> <td class="parametername">TIMESTAMP</td>
<td class="parametervalue">1622134216</td> <td class="parametervalue">1622729373</td>
</tr> </tr>
</table> </table>
</td> </td>
@ -5584,10 +5640,196 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
</table> </table>
</div> </div>
<a name="module_uart_0"> </a>
<div>
<hr/>
<h2>uart_0</h2>altera_avalon_uart v16.1
<br/>
<div class="greydiv">
<table class="connectionboxes">
<tr>
<td class="neighbor" rowspan="6">
<a href="#module_nios2_gen2">nios2_gen2</a>
</td>
<td class="from">data_master&#160;&#160;</td>
<td class="main" rowspan="11">uart_0</td>
</tr>
<tr>
<td class="to">&#160;&#160;s1</td>
</tr>
<tr>
<td class="from">irq&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;irq</td>
</tr>
<tr>
<td class="from">debug_reset_request&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;reset</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
<tr>
<td class="neighbor" rowspan="4">
<a href="#module_clk_50">clk_50</a>
</td>
<td class="from">clk&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;clk</td>
</tr>
<tr>
<td class="from">clk_reset&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;reset</td>
</tr>
</table>
</div>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">baud</td>
<td class="parametervalue">115200</td>
</tr>
<tr>
<td class="parametername">dataBits</td>
<td class="parametervalue">8</td>
</tr>
<tr>
<td class="parametername">fixedBaud</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">parity</td>
<td class="parametervalue">NONE</td>
</tr>
<tr>
<td class="parametername">simCharStream</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">simInteractiveInputEnable</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">simInteractiveOutputEnable</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">simTrueBaud</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">stopBits</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">syncRegDepth</td>
<td class="parametervalue">2</td>
</tr>
<tr>
<td class="parametername">useCtsRts</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">useEopRegister</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">useRelativePathForSimFile</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">clockRate</td>
<td class="parametervalue">50000000</td>
</tr>
<tr>
<td class="parametername">baudError</td>
<td class="parametervalue">0.01</td>
</tr>
<tr>
<td class="parametername">parityFisrtChar</td>
<td class="parametervalue">N</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">UNKNOWN</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>&#160;&#160;
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>
<table>
<tr>
<td class="parametername">BAUD</td>
<td class="parametervalue">115200</td>
</tr>
<tr>
<td class="parametername">DATA_BITS</td>
<td class="parametervalue">8</td>
</tr>
<tr>
<td class="parametername">FIXED_BAUD</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">FREQ</td>
<td class="parametervalue">50000000</td>
</tr>
<tr>
<td class="parametername">PARITY</td>
<td class="parametervalue">'N'</td>
</tr>
<tr>
<td class="parametername">SIM_CHAR_STREAM</td>
<td class="parametervalue">""</td>
</tr>
<tr>
<td class="parametername">SIM_TRUE_BAUD</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">STOP_BITS</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">SYNC_REG_DEPTH</td>
<td class="parametervalue">2</td>
</tr>
<tr>
<td class="parametername">USE_CTS_RTS</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">USE_EOP_REGISTER</td>
<td class="parametervalue">0</td>
</tr>
</table>
</td>
</tr>
</table>
</div>
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">generation took 0.01 seconds</td> <td class="l">generation took 0.00 seconds</td>
<td class="r">rendering took 0.08 seconds</td> <td class="r">rendering took 0.03 seconds</td>
</tr> </tr>
</table> </table>
</body> </body>

4763
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.xml
View file

File diff suppressed because one or more lines are too long

6
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_bb.v
View file

@ -41,7 +41,9 @@ module Qsys (
terasic_camera_0_conduit_end_D, terasic_camera_0_conduit_end_D,
terasic_camera_0_conduit_end_FVAL, terasic_camera_0_conduit_end_FVAL,
terasic_camera_0_conduit_end_LVAL, terasic_camera_0_conduit_end_LVAL,
terasic_camera_0_conduit_end_PIXCLK); terasic_camera_0_conduit_end_PIXCLK,
uart_0_rx_tx_rxd,
uart_0_rx_tx_txd);
input alt_vip_itc_0_clocked_video_vid_clk; input alt_vip_itc_0_clocked_video_vid_clk;
output [23:0] alt_vip_itc_0_clocked_video_vid_data; output [23:0] alt_vip_itc_0_clocked_video_vid_data;
@ -85,4 +87,6 @@ module Qsys (
input terasic_camera_0_conduit_end_FVAL; input terasic_camera_0_conduit_end_FVAL;
input terasic_camera_0_conduit_end_LVAL; input terasic_camera_0_conduit_end_LVAL;
input terasic_camera_0_conduit_end_PIXCLK; input terasic_camera_0_conduit_end_PIXCLK;
input uart_0_rx_tx_rxd;
output uart_0_rx_tx_txd;
endmodule endmodule

226
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation.rpt
View file

@ -1,9 +1,7 @@
Info: Starting: Create block symbol file (.bsf) Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate "C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys.qsys" --block-symbol-file --output-directory="C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys" --family="MAX 10" --part=10M50DAF484C7G Info: qsys-generate /home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys.qsys --block-symbol-file --output-directory=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys --family="MAX 10" --part=10M50DAF484C7G
Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys
Progress: Reading input file Progress: Reading input file
Progress: Adding EEE_IMGPROC_0 [EEE_IMGPROC 1.0]
Progress: Parameterizing module EEE_IMGPROC_0
Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0] Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0]
Progress: Parameterizing module TERASIC_AUTO_FOCUS_0 Progress: Parameterizing module TERASIC_AUTO_FOCUS_0
Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0] Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0]
@ -12,35 +10,35 @@ Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0]
Progress: Parameterizing module alt_vip_itc_0 Progress: Parameterizing module alt_vip_itc_0
Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1] Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1]
Progress: Parameterizing module alt_vip_vfb_0 Progress: Parameterizing module alt_vip_vfb_0
Progress: Adding altpll_0 [altpll 16.1] Progress: Adding altpll_0 [altpll 16.0]
Progress: Parameterizing module altpll_0 Progress: Parameterizing module altpll_0
Progress: Adding clk_50 [clock_source 16.1] Progress: Adding clk_50 [clock_source 16.0]
Progress: Parameterizing module clk_50 Progress: Parameterizing module clk_50
Progress: Adding i2c_opencores_camera [i2c_opencores 12.0] Progress: Adding i2c_opencores_camera [i2c_opencores 12.0]
Progress: Parameterizing module i2c_opencores_camera Progress: Parameterizing module i2c_opencores_camera
Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0] Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0]
Progress: Parameterizing module i2c_opencores_mipi Progress: Parameterizing module i2c_opencores_mipi
Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.1] Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.0]
Progress: Parameterizing module jtag_uart Progress: Parameterizing module jtag_uart
Progress: Adding key [altera_avalon_pio 16.1] Progress: Adding key [altera_avalon_pio 16.0]
Progress: Parameterizing module key Progress: Parameterizing module key
Progress: Adding led [altera_avalon_pio 16.1] Progress: Adding led [altera_avalon_pio 16.0]
Progress: Parameterizing module led Progress: Parameterizing module led
Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.1] Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.0]
Progress: Parameterizing module mipi_pwdn_n Progress: Parameterizing module mipi_pwdn_n
Progress: Adding mipi_reset_n [altera_avalon_pio 16.1] Progress: Adding mipi_reset_n [altera_avalon_pio 16.0]
Progress: Parameterizing module mipi_reset_n Progress: Parameterizing module mipi_reset_n
Progress: Adding nios2_gen2 [altera_nios2_gen2 16.1] Progress: Adding nios2_gen2 [altera_nios2_gen2 16.0]
Progress: Parameterizing module nios2_gen2 Progress: Parameterizing module nios2_gen2
Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.1] Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.0]
Progress: Parameterizing module onchip_memory2_0 Progress: Parameterizing module onchip_memory2_0
Progress: Adding sdram [altera_avalon_new_sdram_controller 16.1] Progress: Adding sdram [altera_avalon_new_sdram_controller 16.0]
Progress: Parameterizing module sdram Progress: Parameterizing module sdram
Progress: Adding sw [altera_avalon_pio 16.1] Progress: Adding sw [altera_avalon_pio 16.0]
Progress: Parameterizing module sw Progress: Parameterizing module sw
Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.1] Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.0]
Progress: Parameterizing module sysid_qsys Progress: Parameterizing module sysid_qsys
Progress: Adding timer [altera_avalon_timer 16.1] Progress: Adding timer [altera_avalon_timer 16.0]
Progress: Parameterizing module timer Progress: Parameterizing module timer
Progress: Building connections Progress: Building connections
Progress: Parameterizing connections Progress: Parameterizing connections
@ -49,7 +47,6 @@ Progress: Done reading input file
Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II. Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II.
Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: Qsys.sdram: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release.
Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated. Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated.
@ -57,11 +54,9 @@ Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf) Info: Finished: Create block symbol file (.bsf)
Info: Info:
Info: Starting: Create HDL design files for synthesis Info: Starting: Create HDL design files for synthesis
Info: qsys-generate "C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys.qsys" --synthesis=VERILOG --output-directory="C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys\synthesis" --family="MAX 10" --part=10M50DAF484C7G Info: qsys-generate /home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys.qsys --synthesis=VERILOG --output-directory=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys/synthesis --family="MAX 10" --part=10M50DAF484C7G
Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys
Progress: Reading input file Progress: Reading input file
Progress: Adding EEE_IMGPROC_0 [EEE_IMGPROC 1.0]
Progress: Parameterizing module EEE_IMGPROC_0
Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0] Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0]
Progress: Parameterizing module TERASIC_AUTO_FOCUS_0 Progress: Parameterizing module TERASIC_AUTO_FOCUS_0
Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0] Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0]
@ -70,35 +65,35 @@ Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0]
Progress: Parameterizing module alt_vip_itc_0 Progress: Parameterizing module alt_vip_itc_0
Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1] Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1]
Progress: Parameterizing module alt_vip_vfb_0 Progress: Parameterizing module alt_vip_vfb_0
Progress: Adding altpll_0 [altpll 16.1] Progress: Adding altpll_0 [altpll 16.0]
Progress: Parameterizing module altpll_0 Progress: Parameterizing module altpll_0
Progress: Adding clk_50 [clock_source 16.1] Progress: Adding clk_50 [clock_source 16.0]
Progress: Parameterizing module clk_50 Progress: Parameterizing module clk_50
Progress: Adding i2c_opencores_camera [i2c_opencores 12.0] Progress: Adding i2c_opencores_camera [i2c_opencores 12.0]
Progress: Parameterizing module i2c_opencores_camera Progress: Parameterizing module i2c_opencores_camera
Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0] Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0]
Progress: Parameterizing module i2c_opencores_mipi Progress: Parameterizing module i2c_opencores_mipi
Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.1] Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.0]
Progress: Parameterizing module jtag_uart Progress: Parameterizing module jtag_uart
Progress: Adding key [altera_avalon_pio 16.1] Progress: Adding key [altera_avalon_pio 16.0]
Progress: Parameterizing module key Progress: Parameterizing module key
Progress: Adding led [altera_avalon_pio 16.1] Progress: Adding led [altera_avalon_pio 16.0]
Progress: Parameterizing module led Progress: Parameterizing module led
Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.1] Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.0]
Progress: Parameterizing module mipi_pwdn_n Progress: Parameterizing module mipi_pwdn_n
Progress: Adding mipi_reset_n [altera_avalon_pio 16.1] Progress: Adding mipi_reset_n [altera_avalon_pio 16.0]
Progress: Parameterizing module mipi_reset_n Progress: Parameterizing module mipi_reset_n
Progress: Adding nios2_gen2 [altera_nios2_gen2 16.1] Progress: Adding nios2_gen2 [altera_nios2_gen2 16.0]
Progress: Parameterizing module nios2_gen2 Progress: Parameterizing module nios2_gen2
Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.1] Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.0]
Progress: Parameterizing module onchip_memory2_0 Progress: Parameterizing module onchip_memory2_0
Progress: Adding sdram [altera_avalon_new_sdram_controller 16.1] Progress: Adding sdram [altera_avalon_new_sdram_controller 16.0]
Progress: Parameterizing module sdram Progress: Parameterizing module sdram
Progress: Adding sw [altera_avalon_pio 16.1] Progress: Adding sw [altera_avalon_pio 16.0]
Progress: Parameterizing module sw Progress: Parameterizing module sw
Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.1] Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.0]
Progress: Parameterizing module sysid_qsys Progress: Parameterizing module sysid_qsys
Progress: Adding timer [altera_avalon_timer 16.1] Progress: Adding timer [altera_avalon_timer 16.0]
Progress: Parameterizing module timer Progress: Parameterizing module timer
Progress: Building connections Progress: Building connections
Progress: Parameterizing connections Progress: Parameterizing connections
@ -107,167 +102,28 @@ Progress: Done reading input file
Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II. Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II.
Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: Qsys.sdram: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release.
Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated. Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated.
Info: Qsys: Generating Qsys "Qsys" for QUARTUS_SYNTH Info: Qsys: Generating Qsys "Qsys" for QUARTUS_SYNTH
Info: Inserting clock-crossing logic between cmd_demux.src5 and cmd_mux_005.sink0 Info: Inserting clock-crossing logic between cmd_demux.src5 and cmd_mux_005.sink0
Info: Inserting clock-crossing logic between cmd_demux.src14 and cmd_mux_014.sink0
Info: Inserting clock-crossing logic between rsp_demux_005.src0 and rsp_mux.sink5 Info: Inserting clock-crossing logic between rsp_demux_005.src0 and rsp_mux.sink5
Info: Inserting clock-crossing logic between rsp_demux_014.src0 and rsp_mux.sink14
Info: EEE_IMGPROC_0: "Qsys" instantiated EEE_IMGPROC "EEE_IMGPROC_0"
Info: TERASIC_AUTO_FOCUS_0: "Qsys" instantiated TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS_0" Info: TERASIC_AUTO_FOCUS_0: "Qsys" instantiated TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS_0"
Info: TERASIC_CAMERA_0: "Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0" Info: TERASIC_CAMERA_0: "Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0"
Info: alt_vip_itc_0: "Qsys" instantiated alt_vip_itc "alt_vip_itc_0" Info: alt_vip_itc_0: "Qsys" instantiated alt_vip_itc "alt_vip_itc_0"
Info: alt_vip_vfb_0: "Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0" Info: alt_vip_vfb_0: "Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0"
Info: altpll_0: Error while generating Qsys_altpll_0.v : 1 : Illegal port or parameter name scandone Illegal port or parameter name scanclkena Illegal port or parameter name scandataout Illegal port or parameter name configupdate Illegal port or parameter name scandata child process exited abnormally
Info: altpll_0: Illegal port or parameter name scandone Illegal port or parameter name scanclkena Illegal port or parameter name scandataout Illegal port or parameter name configupdate Illegal port or parameter name scandata child process exited abnormally while executing "exec /home/ed/altera_lite/16.0/quartus/linux64/clearbox altpll_avalon device_family=MAX10 CBX_FILE=Qsys_altpll_0.v -f cbxcmdln_1617092322619640" ("eval" body line 1) invoked from within "eval exec $cbx_cmd "
Error: Can't continue processing -- expected file /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v is missing
Warning: Quartus Prime Generate HDL Interface was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 1399 megabytes
Error: Processing ended: Tue Mar 30 09:18:43 2021
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:00
Error: altpll_0: File /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v written by generation callback did not contain a module called Qsys_altpll_0
Error: altpll_0: /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v (No such file or directory)
Info: altpll_0: "Qsys" instantiated altpll "altpll_0" Info: altpll_0: "Qsys" instantiated altpll "altpll_0"
Info: i2c_opencores_camera: "Qsys" instantiated i2c_opencores "i2c_opencores_camera" Error: Generation stopped, 218 or more modules remaining
Info: jtag_uart: Starting RTL generation for module 'Qsys_jtag_uart' Info: Qsys: Done "Qsys" with 33 modules, 34 files
Info: jtag_uart: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=Qsys_jtag_uart --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0011_jtag_uart_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0011_jtag_uart_gen//Qsys_jtag_uart_component_configuration.pl --do_build_sim=0 ] Error: qsys-generate failed with exit code 1: 8 Errors, 1 Warning
Info: jtag_uart: Done RTL generation for module 'Qsys_jtag_uart'
Info: jtag_uart: "Qsys" instantiated altera_avalon_jtag_uart "jtag_uart"
Info: key: Starting RTL generation for module 'Qsys_key'
Info: key: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_key --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0012_key_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0012_key_gen//Qsys_key_component_configuration.pl --do_build_sim=0 ]
Info: key: Done RTL generation for module 'Qsys_key'
Info: key: "Qsys" instantiated altera_avalon_pio "key"
Info: led: Starting RTL generation for module 'Qsys_led'
Info: led: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_led --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0013_led_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0013_led_gen//Qsys_led_component_configuration.pl --do_build_sim=0 ]
Info: led: Done RTL generation for module 'Qsys_led'
Info: led: "Qsys" instantiated altera_avalon_pio "led"
Info: mipi_pwdn_n: Starting RTL generation for module 'Qsys_mipi_pwdn_n'
Info: mipi_pwdn_n: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_mipi_pwdn_n --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0014_mipi_pwdn_n_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0014_mipi_pwdn_n_gen//Qsys_mipi_pwdn_n_component_configuration.pl --do_build_sim=0 ]
Info: mipi_pwdn_n: Done RTL generation for module 'Qsys_mipi_pwdn_n'
Info: mipi_pwdn_n: "Qsys" instantiated altera_avalon_pio "mipi_pwdn_n"
Info: nios2_gen2: "Qsys" instantiated altera_nios2_gen2 "nios2_gen2"
Info: onchip_memory2_0: Starting RTL generation for module 'Qsys_onchip_memory2_0'
Info: onchip_memory2_0: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=Qsys_onchip_memory2_0 --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0015_onchip_memory2_0_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0015_onchip_memory2_0_gen//Qsys_onchip_memory2_0_component_configuration.pl --do_build_sim=0 ]
Info: onchip_memory2_0: Done RTL generation for module 'Qsys_onchip_memory2_0'
Info: onchip_memory2_0: "Qsys" instantiated altera_avalon_onchip_memory2 "onchip_memory2_0"
Info: sdram: Starting RTL generation for module 'Qsys_sdram'
Info: sdram: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller/generate_rtl.pl --name=Qsys_sdram --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0016_sdram_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0016_sdram_gen//Qsys_sdram_component_configuration.pl --do_build_sim=0 ]
Info: sdram: Done RTL generation for module 'Qsys_sdram'
Info: sdram: "Qsys" instantiated altera_avalon_new_sdram_controller "sdram"
Info: sw: Starting RTL generation for module 'Qsys_sw'
Info: sw: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_sw --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0017_sw_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0017_sw_gen//Qsys_sw_component_configuration.pl --do_build_sim=0 ]
Info: sw: Done RTL generation for module 'Qsys_sw'
Info: sw: "Qsys" instantiated altera_avalon_pio "sw"
Info: sysid_qsys: "Qsys" instantiated altera_avalon_sysid_qsys "sysid_qsys"
Info: timer: Starting RTL generation for module 'Qsys_timer'
Info: timer: Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//perl/bin/perl.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=Qsys_timer --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0019_timer_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0019_timer_gen//Qsys_timer_component_configuration.pl --do_build_sim=0 ]
Info: timer: Done RTL generation for module 'Qsys_timer'
Info: timer: "Qsys" instantiated altera_avalon_timer "timer"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_0: "Qsys" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_1: "Qsys" instantiated altera_mm_interconnect "mm_interconnect_1"
Info: irq_mapper: "Qsys" instantiated altera_irq_mapper "irq_mapper"
Info: rst_controller: "Qsys" instantiated altera_reset_controller "rst_controller"
Info: vfb_writer_packet_write_address_au_l_muxinst: "alt_vip_vfb_0" instantiated alt_cusp_muxbin2 "vfb_writer_packet_write_address_au_l_muxinst"
Info: vfb_writer_packet_write_address_au: "alt_vip_vfb_0" instantiated alt_au "vfb_writer_packet_write_address_au"
Info: vfb_writer_overflow_flag_reg: "alt_vip_vfb_0" instantiated alt_reg "vfb_writer_overflow_flag_reg"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: vfb_writer_length_counter_au_enable_muxinst: "alt_vip_vfb_0" instantiated alt_cusp_muxhot16 "vfb_writer_length_counter_au_enable_muxinst"
Info: din: "alt_vip_vfb_0" instantiated alt_avalon_st_input "din"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: dout: "alt_vip_vfb_0" instantiated alt_avalon_st_output "dout"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: read_master: "alt_vip_vfb_0" instantiated alt_avalon_mm_bursting_master_fifo "read_master"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: read_master_pull: "alt_vip_vfb_0" instantiated alt_cusp_pulling_width_adapter "read_master_pull"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: write_master_push: "alt_vip_vfb_0" instantiated alt_cusp_pushing_width_adapter "write_master_push"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: pc0: "alt_vip_vfb_0" instantiated alt_pc "pc0"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: fu_id_4494_line325_93: "alt_vip_vfb_0" instantiated alt_cmp "fu_id_4494_line325_93"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: clocksource: "alt_vip_vfb_0" instantiated alt_cusp_testbench_clock "clocksource"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: cpu: Starting RTL generation for module 'Qsys_nios2_gen2_cpu'
Info: cpu: Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//eperlcmd.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=Qsys_nios2_gen2_cpu --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0022_cpu_gen/ --quartus_bindir=C:/intelFPGA_lite/16.1/quartus/bin64/ --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0022_cpu_gen//Qsys_nios2_gen2_cpu_processor_configuration.pl --do_build_sim=0 ]
Info: cpu: # 2021.05.27 17:51:00 (*) Starting Nios II generation
Info: cpu: # 2021.05.27 17:51:00 (*) Checking for plaintext license.
Info: cpu: # 2021.05.27 17:51:01 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/
Info: cpu: # 2021.05.27 17:51:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable
Info: cpu: # 2021.05.27 17:51:01 (*) LM_LICENSE_FILE environment variable is empty
Info: cpu: # 2021.05.27 17:51:01 (*) Plaintext license not found.
Info: cpu: # 2021.05.27 17:51:01 (*) Checking for encrypted license (non-evaluation).
Info: cpu: # 2021.05.27 17:51:01 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/
Info: cpu: # 2021.05.27 17:51:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable
Info: cpu: # 2021.05.27 17:51:01 (*) LM_LICENSE_FILE environment variable is empty
Info: cpu: # 2021.05.27 17:51:01 (*) Encrypted license not found. Defaulting to OCP evaluation license (produces a time-limited SOF)
Info: cpu: # 2021.05.27 17:51:01 (*) Elaborating CPU configuration settings
Info: cpu: # 2021.05.27 17:51:01 (*) Creating all objects for CPU
Info: cpu: # 2021.05.27 17:51:01 (*) Testbench
Info: cpu: # 2021.05.27 17:51:02 (*) Instruction decoding
Info: cpu: # 2021.05.27 17:51:02 (*) Instruction fields
Info: cpu: # 2021.05.27 17:51:02 (*) Instruction decodes
Info: cpu: # 2021.05.27 17:51:02 (*) Signals for RTL simulation waveforms
Info: cpu: # 2021.05.27 17:51:02 (*) Instruction controls
Info: cpu: # 2021.05.27 17:51:02 (*) Pipeline frontend
Info: cpu: # 2021.05.27 17:51:02 (*) Pipeline backend
Info: cpu: # 2021.05.27 17:51:05 (*) Generating RTL from CPU objects
Info: cpu: # 2021.05.27 17:51:06 (*) Creating encrypted RTL
Info: cpu: # 2021.05.27 17:51:07 (*) Done Nios II generation
Info: cpu: Done RTL generation for module 'Qsys_nios2_gen2_cpu'
Info: cpu: "nios2_gen2" instantiated altera_nios2_gen2_unit "cpu"
Info: nios2_gen2_data_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_gen2_data_master_translator"
Info: jtag_uart_avalon_jtag_slave_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"
Info: nios2_gen2_data_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_gen2_data_master_agent"
Info: jtag_uart_avalon_jtag_slave_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"
Info: jtag_uart_avalon_jtag_slave_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"
Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001"
Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
Info: router_006: "mm_interconnect_0" instantiated altera_merlin_router "router_006"
Info: nios2_gen2_data_master_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "nios2_gen2_data_master_limiter"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_sc_fifo.v
Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_demux_001: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"
Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
Info: cmd_mux_004: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_004"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_demux_004: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_004"
Info: rsp_demux_005: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_005"
Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_mux_001: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: crosser: "mm_interconnect_0" instantiated altera_avalon_st_handshake_clock_crosser "crosser"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v
Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: router: "mm_interconnect_1" instantiated altera_merlin_router "router"
Info: router_002: "mm_interconnect_1" instantiated altera_merlin_router "router_002"
Info: sdram_s1_burst_adapter: "mm_interconnect_1" instantiated altera_merlin_burst_adapter "sdram_s1_burst_adapter"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v
Info: cmd_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: sdram_s1_rsp_width_adapter: "mm_interconnect_1" instantiated altera_merlin_width_adapter "sdram_s1_rsp_width_adapter"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_address_alignment.sv
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv
Info: avalon_st_adapter: "mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: Qsys: Done "Qsys" with 67 modules, 142 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis Info: Finished: Create HDL design files for synthesis

231
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation_previous.rpt
View file

@ -1,9 +1,7 @@
Info: Starting: Create block symbol file (.bsf) Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate "C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys.qsys" --block-symbol-file --output-directory="C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys" --family="MAX 10" --part=10M50DAF484C7G Info: qsys-generate /home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys.qsys --block-symbol-file --output-directory=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys --family="MAX 10" --part=10M50DAF484C7G
Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys
Progress: Reading input file Progress: Reading input file
Progress: Adding EEE_IMGPROC_0 [EEE_IMGPROC 1.0]
Progress: Parameterizing module EEE_IMGPROC_0
Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0] Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0]
Progress: Parameterizing module TERASIC_AUTO_FOCUS_0 Progress: Parameterizing module TERASIC_AUTO_FOCUS_0
Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0] Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0]
@ -12,38 +10,36 @@ Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0]
Progress: Parameterizing module alt_vip_itc_0 Progress: Parameterizing module alt_vip_itc_0
Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1] Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1]
Progress: Parameterizing module alt_vip_vfb_0 Progress: Parameterizing module alt_vip_vfb_0
Progress: Adding altpll_0 [altpll 16.1] Progress: Adding altpll_0 [altpll 16.0]
Progress: Parameterizing module altpll_0 Progress: Parameterizing module altpll_0
Progress: Adding clk_50 [clock_source 16.1] Progress: Adding clk_50 [clock_source 16.0]
Progress: Parameterizing module clk_50 Progress: Parameterizing module clk_50
Progress: Adding i2c_opencores_camera [i2c_opencores 12.0] Progress: Adding i2c_opencores_camera [i2c_opencores 12.0]
Progress: Parameterizing module i2c_opencores_camera Progress: Parameterizing module i2c_opencores_camera
Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0] Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0]
Progress: Parameterizing module i2c_opencores_mipi Progress: Parameterizing module i2c_opencores_mipi
Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.1] Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.0]
Progress: Parameterizing module jtag_uart Progress: Parameterizing module jtag_uart
Progress: Adding key [altera_avalon_pio 16.1] Progress: Adding key [altera_avalon_pio 16.0]
Progress: Parameterizing module key Progress: Parameterizing module key
Progress: Adding led [altera_avalon_pio 16.1] Progress: Adding led [altera_avalon_pio 16.0]
Progress: Parameterizing module led Progress: Parameterizing module led
Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.1] Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.0]
Progress: Parameterizing module mipi_pwdn_n Progress: Parameterizing module mipi_pwdn_n
Progress: Adding mipi_reset_n [altera_avalon_pio 16.1] Progress: Adding mipi_reset_n [altera_avalon_pio 16.0]
Progress: Parameterizing module mipi_reset_n Progress: Parameterizing module mipi_reset_n
Progress: Adding nios2_gen2 [altera_nios2_gen2 16.1] Progress: Adding nios2_gen2 [altera_nios2_gen2 16.0]
Progress: Parameterizing module nios2_gen2 Progress: Parameterizing module nios2_gen2
Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.1] Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.0]
Progress: Parameterizing module onchip_memory2_0 Progress: Parameterizing module onchip_memory2_0
Progress: Adding sdram [altera_avalon_new_sdram_controller 16.1] Progress: Adding sdram [altera_avalon_new_sdram_controller 16.0]
Progress: Parameterizing module sdram Progress: Parameterizing module sdram
Progress: Adding sw [altera_avalon_pio 16.1] Progress: Adding sw [altera_avalon_pio 16.0]
Progress: Parameterizing module sw Progress: Parameterizing module sw
Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.1] Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.0]
Progress: Parameterizing module sysid_qsys Progress: Parameterizing module sysid_qsys
Progress: Adding timer [altera_avalon_timer 16.1] Progress: Adding timer [altera_avalon_timer 16.0]
Progress: Parameterizing module timer Progress: Parameterizing module timer
Progress: Adding uart_interface_0 [uart_interface 1.0]
Progress: Parameterizing module uart_interface_0
Progress: Building connections Progress: Building connections
Progress: Parameterizing connections Progress: Parameterizing connections
Progress: Validating Progress: Validating
@ -51,7 +47,6 @@ Progress: Done reading input file
Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II. Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II.
Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: Qsys.sdram: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release.
Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated. Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated.
@ -59,11 +54,9 @@ Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf) Info: Finished: Create block symbol file (.bsf)
Info: Info:
Info: Starting: Create HDL design files for synthesis Info: Starting: Create HDL design files for synthesis
Info: qsys-generate "C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys.qsys" --synthesis=VERILOG --output-directory="C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys\synthesis" --family="MAX 10" --part=10M50DAF484C7G Info: qsys-generate /home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys.qsys --synthesis=VERILOG --output-directory=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys/synthesis --family="MAX 10" --part=10M50DAF484C7G
Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys
Progress: Reading input file Progress: Reading input file
Progress: Adding EEE_IMGPROC_0 [EEE_IMGPROC 1.0]
Progress: Parameterizing module EEE_IMGPROC_0
Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0] Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0]
Progress: Parameterizing module TERASIC_AUTO_FOCUS_0 Progress: Parameterizing module TERASIC_AUTO_FOCUS_0
Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0] Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0]
@ -72,38 +65,36 @@ Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0]
Progress: Parameterizing module alt_vip_itc_0 Progress: Parameterizing module alt_vip_itc_0
Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1] Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1]
Progress: Parameterizing module alt_vip_vfb_0 Progress: Parameterizing module alt_vip_vfb_0
Progress: Adding altpll_0 [altpll 16.1] Progress: Adding altpll_0 [altpll 16.0]
Progress: Parameterizing module altpll_0 Progress: Parameterizing module altpll_0
Progress: Adding clk_50 [clock_source 16.1] Progress: Adding clk_50 [clock_source 16.0]
Progress: Parameterizing module clk_50 Progress: Parameterizing module clk_50
Progress: Adding i2c_opencores_camera [i2c_opencores 12.0] Progress: Adding i2c_opencores_camera [i2c_opencores 12.0]
Progress: Parameterizing module i2c_opencores_camera Progress: Parameterizing module i2c_opencores_camera
Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0] Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0]
Progress: Parameterizing module i2c_opencores_mipi Progress: Parameterizing module i2c_opencores_mipi
Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.1] Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.0]
Progress: Parameterizing module jtag_uart Progress: Parameterizing module jtag_uart
Progress: Adding key [altera_avalon_pio 16.1] Progress: Adding key [altera_avalon_pio 16.0]
Progress: Parameterizing module key Progress: Parameterizing module key
Progress: Adding led [altera_avalon_pio 16.1] Progress: Adding led [altera_avalon_pio 16.0]
Progress: Parameterizing module led Progress: Parameterizing module led
Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.1] Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.0]
Progress: Parameterizing module mipi_pwdn_n Progress: Parameterizing module mipi_pwdn_n
Progress: Adding mipi_reset_n [altera_avalon_pio 16.1] Progress: Adding mipi_reset_n [altera_avalon_pio 16.0]
Progress: Parameterizing module mipi_reset_n Progress: Parameterizing module mipi_reset_n
Progress: Adding nios2_gen2 [altera_nios2_gen2 16.1] Progress: Adding nios2_gen2 [altera_nios2_gen2 16.0]
Progress: Parameterizing module nios2_gen2 Progress: Parameterizing module nios2_gen2
Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.1] Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.0]
Progress: Parameterizing module onchip_memory2_0 Progress: Parameterizing module onchip_memory2_0
Progress: Adding sdram [altera_avalon_new_sdram_controller 16.1] Progress: Adding sdram [altera_avalon_new_sdram_controller 16.0]
Progress: Parameterizing module sdram Progress: Parameterizing module sdram
Progress: Adding sw [altera_avalon_pio 16.1] Progress: Adding sw [altera_avalon_pio 16.0]
Progress: Parameterizing module sw Progress: Parameterizing module sw
Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.1] Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.0]
Progress: Parameterizing module sysid_qsys Progress: Parameterizing module sysid_qsys
Progress: Adding timer [altera_avalon_timer 16.1] Progress: Adding timer [altera_avalon_timer 16.0]
Progress: Parameterizing module timer Progress: Parameterizing module timer
Progress: Adding uart_interface_0 [uart_interface 1.0]
Progress: Parameterizing module uart_interface_0
Progress: Building connections Progress: Building connections
Progress: Parameterizing connections Progress: Parameterizing connections
Progress: Validating Progress: Validating
@ -111,168 +102,28 @@ Progress: Done reading input file
Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II. Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II.
Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: Qsys.sdram: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release.
Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated. Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated.
Info: Qsys: Generating Qsys "Qsys" for QUARTUS_SYNTH Info: Qsys: Generating Qsys "Qsys" for QUARTUS_SYNTH
Info: Inserting clock-crossing logic between cmd_demux.src5 and cmd_mux_005.sink0 Info: Inserting clock-crossing logic between cmd_demux.src5 and cmd_mux_005.sink0
Info: Inserting clock-crossing logic between cmd_demux.src14 and cmd_mux_014.sink0
Info: Inserting clock-crossing logic between rsp_demux_005.src0 and rsp_mux.sink5 Info: Inserting clock-crossing logic between rsp_demux_005.src0 and rsp_mux.sink5
Info: Inserting clock-crossing logic between rsp_demux_014.src0 and rsp_mux.sink14
Info: EEE_IMGPROC_0: "Qsys" instantiated EEE_IMGPROC "EEE_IMGPROC_0"
Info: TERASIC_AUTO_FOCUS_0: "Qsys" instantiated TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS_0" Info: TERASIC_AUTO_FOCUS_0: "Qsys" instantiated TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS_0"
Info: TERASIC_CAMERA_0: "Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0" Info: TERASIC_CAMERA_0: "Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0"
Info: alt_vip_itc_0: "Qsys" instantiated alt_vip_itc "alt_vip_itc_0" Info: alt_vip_itc_0: "Qsys" instantiated alt_vip_itc "alt_vip_itc_0"
Info: alt_vip_vfb_0: "Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0" Info: alt_vip_vfb_0: "Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0"
Info: altpll_0: Error while generating Qsys_altpll_0.v : 1 : Illegal port or parameter name scandone Illegal port or parameter name scanclkena Illegal port or parameter name scandataout Illegal port or parameter name configupdate Illegal port or parameter name scandata child process exited abnormally
Info: altpll_0: Illegal port or parameter name scandone Illegal port or parameter name scanclkena Illegal port or parameter name scandataout Illegal port or parameter name configupdate Illegal port or parameter name scandata child process exited abnormally while executing "exec /home/ed/altera_lite/16.0/quartus/linux64/clearbox altpll_avalon device_family=MAX10 CBX_FILE=Qsys_altpll_0.v -f cbxcmdln_1617092145442977" ("eval" body line 1) invoked from within "eval exec $cbx_cmd "
Error: Can't continue processing -- expected file /tmp/alt8716_2763057626446894966.dir/0014_sopcgen/Qsys_altpll_0.v is missing
Warning: Quartus Prime Generate HDL Interface was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 1399 megabytes
Error: Processing ended: Tue Mar 30 09:15:46 2021
Error: Elapsed time: 00:00:00
Error: Total CPU time (on all processors): 00:00:00
Error: altpll_0: File /tmp/alt8716_2763057626446894966.dir/0014_sopcgen/Qsys_altpll_0.v written by generation callback did not contain a module called Qsys_altpll_0
Error: altpll_0: /tmp/alt8716_2763057626446894966.dir/0014_sopcgen/Qsys_altpll_0.v (No such file or directory)
Info: altpll_0: "Qsys" instantiated altpll "altpll_0" Info: altpll_0: "Qsys" instantiated altpll "altpll_0"
Info: i2c_opencores_camera: "Qsys" instantiated i2c_opencores "i2c_opencores_camera" Error: Generation stopped, 218 or more modules remaining
Info: jtag_uart: Starting RTL generation for module 'Qsys_jtag_uart' Info: Qsys: Done "Qsys" with 33 modules, 34 files
Info: jtag_uart: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=Qsys_jtag_uart --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0012_jtag_uart_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0012_jtag_uart_gen//Qsys_jtag_uart_component_configuration.pl --do_build_sim=0 ] Error: qsys-generate failed with exit code 1: 8 Errors, 1 Warning
Info: jtag_uart: Done RTL generation for module 'Qsys_jtag_uart'
Info: jtag_uart: "Qsys" instantiated altera_avalon_jtag_uart "jtag_uart"
Info: key: Starting RTL generation for module 'Qsys_key'
Info: key: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_key --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0013_key_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0013_key_gen//Qsys_key_component_configuration.pl --do_build_sim=0 ]
Info: key: Done RTL generation for module 'Qsys_key'
Info: key: "Qsys" instantiated altera_avalon_pio "key"
Info: led: Starting RTL generation for module 'Qsys_led'
Info: led: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_led --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0014_led_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0014_led_gen//Qsys_led_component_configuration.pl --do_build_sim=0 ]
Info: led: Done RTL generation for module 'Qsys_led'
Info: led: "Qsys" instantiated altera_avalon_pio "led"
Info: mipi_pwdn_n: Starting RTL generation for module 'Qsys_mipi_pwdn_n'
Info: mipi_pwdn_n: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_mipi_pwdn_n --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0015_mipi_pwdn_n_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0015_mipi_pwdn_n_gen//Qsys_mipi_pwdn_n_component_configuration.pl --do_build_sim=0 ]
Info: mipi_pwdn_n: Done RTL generation for module 'Qsys_mipi_pwdn_n'
Info: mipi_pwdn_n: "Qsys" instantiated altera_avalon_pio "mipi_pwdn_n"
Info: nios2_gen2: "Qsys" instantiated altera_nios2_gen2 "nios2_gen2"
Info: onchip_memory2_0: Starting RTL generation for module 'Qsys_onchip_memory2_0'
Info: onchip_memory2_0: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=Qsys_onchip_memory2_0 --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0016_onchip_memory2_0_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0016_onchip_memory2_0_gen//Qsys_onchip_memory2_0_component_configuration.pl --do_build_sim=0 ]
Info: onchip_memory2_0: Done RTL generation for module 'Qsys_onchip_memory2_0'
Info: onchip_memory2_0: "Qsys" instantiated altera_avalon_onchip_memory2 "onchip_memory2_0"
Info: sdram: Starting RTL generation for module 'Qsys_sdram'
Info: sdram: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller/generate_rtl.pl --name=Qsys_sdram --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0017_sdram_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0017_sdram_gen//Qsys_sdram_component_configuration.pl --do_build_sim=0 ]
Info: sdram: Done RTL generation for module 'Qsys_sdram'
Info: sdram: "Qsys" instantiated altera_avalon_new_sdram_controller "sdram"
Info: sw: Starting RTL generation for module 'Qsys_sw'
Info: sw: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_sw --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0018_sw_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0018_sw_gen//Qsys_sw_component_configuration.pl --do_build_sim=0 ]
Info: sw: Done RTL generation for module 'Qsys_sw'
Info: sw: "Qsys" instantiated altera_avalon_pio "sw"
Info: sysid_qsys: "Qsys" instantiated altera_avalon_sysid_qsys "sysid_qsys"
Info: timer: Starting RTL generation for module 'Qsys_timer'
Info: timer: Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//perl/bin/perl.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=Qsys_timer --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0020_timer_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0020_timer_gen//Qsys_timer_component_configuration.pl --do_build_sim=0 ]
Info: timer: Done RTL generation for module 'Qsys_timer'
Info: timer: "Qsys" instantiated altera_avalon_timer "timer"
Info: uart_interface_0: "Qsys" instantiated uart_interface "uart_interface_0"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_0: "Qsys" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_1: "Qsys" instantiated altera_mm_interconnect "mm_interconnect_1"
Info: irq_mapper: "Qsys" instantiated altera_irq_mapper "irq_mapper"
Info: rst_controller: "Qsys" instantiated altera_reset_controller "rst_controller"
Info: vfb_writer_packet_write_address_au_l_muxinst: "alt_vip_vfb_0" instantiated alt_cusp_muxbin2 "vfb_writer_packet_write_address_au_l_muxinst"
Info: vfb_writer_packet_write_address_au: "alt_vip_vfb_0" instantiated alt_au "vfb_writer_packet_write_address_au"
Info: vfb_writer_overflow_flag_reg: "alt_vip_vfb_0" instantiated alt_reg "vfb_writer_overflow_flag_reg"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: vfb_writer_length_counter_au_enable_muxinst: "alt_vip_vfb_0" instantiated alt_cusp_muxhot16 "vfb_writer_length_counter_au_enable_muxinst"
Info: din: "alt_vip_vfb_0" instantiated alt_avalon_st_input "din"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: dout: "alt_vip_vfb_0" instantiated alt_avalon_st_output "dout"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: read_master: "alt_vip_vfb_0" instantiated alt_avalon_mm_bursting_master_fifo "read_master"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: read_master_pull: "alt_vip_vfb_0" instantiated alt_cusp_pulling_width_adapter "read_master_pull"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: write_master_push: "alt_vip_vfb_0" instantiated alt_cusp_pushing_width_adapter "write_master_push"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: pc0: "alt_vip_vfb_0" instantiated alt_pc "pc0"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: fu_id_4494_line325_93: "alt_vip_vfb_0" instantiated alt_cmp "fu_id_4494_line325_93"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: clocksource: "alt_vip_vfb_0" instantiated alt_cusp_testbench_clock "clocksource"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: cpu: Starting RTL generation for module 'Qsys_nios2_gen2_cpu'
Info: cpu: Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//eperlcmd.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=Qsys_nios2_gen2_cpu --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0024_cpu_gen/ --quartus_bindir=C:/intelFPGA_lite/16.1/quartus/bin64/ --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0024_cpu_gen//Qsys_nios2_gen2_cpu_processor_configuration.pl --do_build_sim=0 ]
Info: cpu: # 2021.05.27 17:14:55 (*) Starting Nios II generation
Info: cpu: # 2021.05.27 17:14:55 (*) Checking for plaintext license.
Info: cpu: # 2021.05.27 17:14:55 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/
Info: cpu: # 2021.05.27 17:14:55 (*) Defaulting to contents of LM_LICENSE_FILE environment variable
Info: cpu: # 2021.05.27 17:14:55 (*) LM_LICENSE_FILE environment variable is empty
Info: cpu: # 2021.05.27 17:14:55 (*) Plaintext license not found.
Info: cpu: # 2021.05.27 17:14:55 (*) Checking for encrypted license (non-evaluation).
Info: cpu: # 2021.05.27 17:14:56 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/
Info: cpu: # 2021.05.27 17:14:56 (*) Defaulting to contents of LM_LICENSE_FILE environment variable
Info: cpu: # 2021.05.27 17:14:56 (*) LM_LICENSE_FILE environment variable is empty
Info: cpu: # 2021.05.27 17:14:56 (*) Encrypted license not found. Defaulting to OCP evaluation license (produces a time-limited SOF)
Info: cpu: # 2021.05.27 17:14:56 (*) Elaborating CPU configuration settings
Info: cpu: # 2021.05.27 17:14:56 (*) Creating all objects for CPU
Info: cpu: # 2021.05.27 17:14:56 (*) Testbench
Info: cpu: # 2021.05.27 17:14:56 (*) Instruction decoding
Info: cpu: # 2021.05.27 17:14:56 (*) Instruction fields
Info: cpu: # 2021.05.27 17:14:56 (*) Instruction decodes
Info: cpu: # 2021.05.27 17:14:57 (*) Signals for RTL simulation waveforms
Info: cpu: # 2021.05.27 17:14:57 (*) Instruction controls
Info: cpu: # 2021.05.27 17:14:57 (*) Pipeline frontend
Info: cpu: # 2021.05.27 17:14:57 (*) Pipeline backend
Info: cpu: # 2021.05.27 17:14:59 (*) Generating RTL from CPU objects
Info: cpu: # 2021.05.27 17:15:00 (*) Creating encrypted RTL
Info: cpu: # 2021.05.27 17:15:01 (*) Done Nios II generation
Info: cpu: Done RTL generation for module 'Qsys_nios2_gen2_cpu'
Info: cpu: "nios2_gen2" instantiated altera_nios2_gen2_unit "cpu"
Info: nios2_gen2_data_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_gen2_data_master_translator"
Info: jtag_uart_avalon_jtag_slave_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"
Info: nios2_gen2_data_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_gen2_data_master_agent"
Info: jtag_uart_avalon_jtag_slave_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"
Info: jtag_uart_avalon_jtag_slave_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"
Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001"
Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
Info: router_006: "mm_interconnect_0" instantiated altera_merlin_router "router_006"
Info: nios2_gen2_data_master_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "nios2_gen2_data_master_limiter"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_sc_fifo.v
Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_demux_001: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"
Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
Info: cmd_mux_004: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_004"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_demux_004: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_004"
Info: rsp_demux_005: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_005"
Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_mux_001: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: crosser: "mm_interconnect_0" instantiated altera_avalon_st_handshake_clock_crosser "crosser"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v
Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: router: "mm_interconnect_1" instantiated altera_merlin_router "router"
Info: router_002: "mm_interconnect_1" instantiated altera_merlin_router "router_002"
Info: sdram_s1_burst_adapter: "mm_interconnect_1" instantiated altera_merlin_burst_adapter "sdram_s1_burst_adapter"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v
Info: cmd_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: sdram_s1_rsp_width_adapter: "mm_interconnect_1" instantiated altera_merlin_width_adapter "sdram_s1_rsp_width_adapter"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_address_alignment.sv
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv
Info: avalon_st_adapter: "mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: Qsys: Done "Qsys" with 68 modules, 143 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis Info: Finished: Create HDL design files for synthesis

4
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_inst.v
View file

@ -40,6 +40,8 @@
.terasic_camera_0_conduit_end_D (<connected-to-terasic_camera_0_conduit_end_D>), // terasic_camera_0_conduit_end.D .terasic_camera_0_conduit_end_D (<connected-to-terasic_camera_0_conduit_end_D>), // terasic_camera_0_conduit_end.D
.terasic_camera_0_conduit_end_FVAL (<connected-to-terasic_camera_0_conduit_end_FVAL>), // .FVAL .terasic_camera_0_conduit_end_FVAL (<connected-to-terasic_camera_0_conduit_end_FVAL>), // .FVAL
.terasic_camera_0_conduit_end_LVAL (<connected-to-terasic_camera_0_conduit_end_LVAL>), // .LVAL .terasic_camera_0_conduit_end_LVAL (<connected-to-terasic_camera_0_conduit_end_LVAL>), // .LVAL
.terasic_camera_0_conduit_end_PIXCLK (<connected-to-terasic_camera_0_conduit_end_PIXCLK>) // .PIXCLK .terasic_camera_0_conduit_end_PIXCLK (<connected-to-terasic_camera_0_conduit_end_PIXCLK>), // .PIXCLK
.uart_0_rx_tx_rxd (<connected-to-uart_0_rx_tx_rxd>), // uart_0_rx_tx.rxd
.uart_0_rx_tx_txd (<connected-to-uart_0_rx_tx_txd>) // .txd
); );

8
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_inst.vhd
View file

@ -41,7 +41,9 @@
terasic_camera_0_conduit_end_D : in std_logic_vector(11 downto 0) := (others => 'X'); -- D terasic_camera_0_conduit_end_D : in std_logic_vector(11 downto 0) := (others => 'X'); -- D
terasic_camera_0_conduit_end_FVAL : in std_logic := 'X'; -- FVAL terasic_camera_0_conduit_end_FVAL : in std_logic := 'X'; -- FVAL
terasic_camera_0_conduit_end_LVAL : in std_logic := 'X'; -- LVAL terasic_camera_0_conduit_end_LVAL : in std_logic := 'X'; -- LVAL
terasic_camera_0_conduit_end_PIXCLK : in std_logic := 'X' -- PIXCLK terasic_camera_0_conduit_end_PIXCLK : in std_logic := 'X'; -- PIXCLK
uart_0_rx_tx_rxd : in std_logic := 'X'; -- rxd
uart_0_rx_tx_txd : out std_logic -- txd
); );
end component Qsys; end component Qsys;
@ -88,6 +90,8 @@
terasic_camera_0_conduit_end_D => CONNECTED_TO_terasic_camera_0_conduit_end_D, -- terasic_camera_0_conduit_end.D terasic_camera_0_conduit_end_D => CONNECTED_TO_terasic_camera_0_conduit_end_D, -- terasic_camera_0_conduit_end.D
terasic_camera_0_conduit_end_FVAL => CONNECTED_TO_terasic_camera_0_conduit_end_FVAL, -- .FVAL terasic_camera_0_conduit_end_FVAL => CONNECTED_TO_terasic_camera_0_conduit_end_FVAL, -- .FVAL
terasic_camera_0_conduit_end_LVAL => CONNECTED_TO_terasic_camera_0_conduit_end_LVAL, -- .LVAL terasic_camera_0_conduit_end_LVAL => CONNECTED_TO_terasic_camera_0_conduit_end_LVAL, -- .LVAL
terasic_camera_0_conduit_end_PIXCLK => CONNECTED_TO_terasic_camera_0_conduit_end_PIXCLK -- .PIXCLK terasic_camera_0_conduit_end_PIXCLK => CONNECTED_TO_terasic_camera_0_conduit_end_PIXCLK, -- .PIXCLK
uart_0_rx_tx_rxd => CONNECTED_TO_uart_0_rx_tx_rxd, -- uart_0_rx_tx.rxd
uart_0_rx_tx_txd => CONNECTED_TO_uart_0_rx_tx_txd -- .txd
); );

12
Vision/DE10_LITE_D8M_VIP_16/RemoteSystemsTempFiles/.project
View file

@ -1,12 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>RemoteSystemsTempFiles</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
</buildSpec>
<natures>
<nature>org.eclipse.rse.ui.remoteSystemsTempNature</nature>
</natures>
</projectDescription>

14
Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/EEE_IMGPROC.v
View file

@ -72,25 +72,13 @@ parameter BB_COL_DEFAULT = 24'h00ff00;
wire [7:0] red, green, blue, grey; wire [7:0] red, green, blue, grey;
wire [7:0] red_out, green_out, blue_out; wire [7:0] red_out, green_out, blue_out;
wire [8:0] hue;
wire [7:0] saturation, value;
wire sop, eop, in_valid, out_ready; wire sop, eop, in_valid, out_ready;
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
// RGB --> HSV Conversion
wire [7:0] min, max, delta;
assign min = (red < green) ? ((red < blue) ? red : blue) : ((green < blue) ? green : blue);
assign max = (red > green) ? ((red > blue) ? red : blue) : ((green > blue) ? green : blue);
assign delta = max - min;
assign hue = (red == max) ? (green - blue)/delta : ((green == max) ? 8'h55+((blue - red)/delta) : 8'haa+((red - green)/delta));
assign saturation = (max == 8'h00) ? 8'h00 : delta / max;
assign value = max;
// Detect red areas // Detect red areas
wire red_detect; wire red_detect;
//assign red_detect = red[7] & ~green[7] & ~blue[7]; assign red_detect = red[7] & ~green[7] & ~blue[7];
assign red_detect = blue[7];
// Find boundary of cursor box // Find boundary of cursor box

273
Vision/DE10_LITE_D8M_VIP_16/ip/de10lite-hdl/uart.v
View file

@ -1,273 +0,0 @@
/*
Source: https://github.com/hildebrandmw/de10lite-hdl/blob/master/components/uart/hdl/uart.v
Description: Very simple UART tx/rx module. Requires a streaming interface,
provides no buffering for input or output data.
*/
module uart
#( parameter CLK_FREQ = 50_000_000,
parameter BAUD = 115_200
)
( input clk,
input reset,
// Receiving
input rx, // Received serial stream
output reg [7:0] rx_data, // Deserialized byte.
output rx_valid, // Asserted when rx_data is valid
// Transmitting
output reg tx, // Transmitted serial stream
input [7:0] tx_data, // Deserialized byte to transmit.
input tx_transmit, // Start Signal. No effect if tx_ready = 0
output reg tx_ready // Asserted when ready to accept data
);
///////////////////////////////
// Functionality Description //
///////////////////////////////
/*
RECEIVING: Module receives a serial stream through the port rx.
When a byte has been successfully received, the received data will be
available on the output port rx_data and the output port rx_valid will be
asserted for 1 clock cycle.
Validity of output data is not guaranteed if rx_valid is not 1. If this
is important for you, you may modify this design to register the output.
TRANSMITTING: When input port tx_transmit is 1 (asserted), module will
store the data on the input port tx_data and serialize through the output
port tx.
Module will only save and transmit the data at tx_data if the signal
tx_ready is asserted when tx_transmit is asserted. This module will not
buffer input data. While transmitting, tx_ready is deasserted and the
input port tx_transmit will have no effect.
Once tx_ready is deasserted, data at port tx_data is not used and need
not be stable.
*/
/////////////////////////
// Signal Declarations //
/////////////////////////
// ---------------------- //
// -- Local Parameters -- //
// ---------------------- //
// Number of synchronization stages to avoid metastability
localparam SYNC_STAGES = 2;
// Over Sampling Factor
localparam OSF = 16;
// Compute count to generate local clock enable
localparam CLK_DIV_COUNT = CLK_FREQ / (OSF * BAUD);
// ---------------------------- //
// -- Clock Dividing Counter -- //
// ---------------------------- //
reg [15:0] count;
reg enable; // Local Clock Enable
// -- RX Synchronizer --
reg [SYNC_STAGES-1:0] rx_sync;
reg rx_internal;
// ---------------- //
// -- RX Signals -- //
// ---------------- //
// State Machine Assignments
localparam RX_WAIT = 0;
localparam RX_CHECK_START = 1;
localparam RX_RECEIVING = 2;
localparam RX_WAIT_FOR_STOP = 3;
localparam RX_INITIAL_STATE = RX_WAIT;
reg [1:0] rx_state = RX_INITIAL_STATE;
reg [4:0] rx_count; // Counts Over-sampling clock enables
reg [2:0] rx_sampleCount; // Counts number of bits received
// These last two signals are used to make sure the "rx_valid" signal
// is only asserted for one clock cycle.
reg rx_validInternal, rx_validLast;
// -----------------//
// -- TX Signals -- //
// -----------------//
// State Machine Assignments
localparam TX_WAIT = 0;
localparam TX_TRANSMITTING = 1;
localparam TX_INITIAL_STATE = TX_WAIT;
reg tx_state = TX_INITIAL_STATE;
reg [9:0] tx_dataBuffer; // Capture Register for transmitted data
reg [4:0] tx_count; // Counts over-sampling clock
reg [3:0] tx_sampleCount; // Number of Bits Sent
/////////////////////
// Implementations //
/////////////////////
// ---------------------------- //
// -- Misc Synchronous Logic -- //
// ---------------------------- //
always @(posedge clk) begin
// Clock Divider
if (reset) begin
count <= 0;
enable <= 0;
end else if (count == CLK_DIV_COUNT - 1) begin
count <= 0;
enable <= 1;
end else begin
count <= count + 1;
enable <= 0;
end
// RX Synchronizer
if (enable) begin
{rx_sync,rx_internal} <= {rx, rx_sync};
end
// Pulse Shortener for rx_valid signal
rx_validLast <= rx_validInternal;
end
// Pulse Shortner for rx_valid signal
assign rx_valid = rx_validInternal & ~rx_validLast;
// ---------------------- //
// -- RX State Machine -- //
// ---------------------- //
always @(posedge clk) begin
if (reset) begin
rx_state <= RX_INITIAL_STATE;
rx_validInternal <= 0;
end else if (enable) begin
case (rx_state)
// Wait for the start bit. (RX = 0)
RX_WAIT: begin
rx_validInternal <= 0;
if (rx_internal == 0) begin
rx_state <= RX_CHECK_START;
rx_count <= 1;
end
end
// Aligh with center of transmitted bit
RX_CHECK_START: begin
// Check if RX is still 0
if (rx_count == (OSF >> 1) - 1 && rx_internal == 0) begin
rx_state <= RX_RECEIVING;
rx_count <= 0;
rx_sampleCount <= 0;
// Faulty Start Bit
end else if (rx_count == (OSF >> 1) - 1 && rx_internal == 1) begin
rx_state <= RX_WAIT;
// Default Option: Count local clocks
end else begin
rx_count <= rx_count + 1;
end
end
// Sample in middle of received bit. Shift data into rx_data
RX_RECEIVING: begin
if (rx_count == OSF - 1) begin
rx_count <= 0;
rx_data <= {rx_internal, rx_data[7:1]};
rx_sampleCount <= rx_sampleCount + 1;
// Check if this is the last bit of data
if (rx_sampleCount == 7) begin
rx_state <= RX_WAIT_FOR_STOP;
end
end else begin
rx_count <= rx_count + 1;
end
end
// Wait until stop bit is received
// Not the best logic in the world, but it works.
RX_WAIT_FOR_STOP: begin
if (rx_internal == 1'b1) begin
rx_state <= RX_WAIT;
rx_validInternal <= 1;
end
end
// In case something goes horribly wrong.
default: begin
rx_state <= RX_INITIAL_STATE;
end
endcase
end
end
// ---------------------- //
// -- TX State Machine -- //
// ---------------------- //
always @(posedge clk) begin
if (reset) begin
tx_state <= TX_INITIAL_STATE;
tx <= 1;
end else begin
case (tx_state)
// Wait for start signal.
// Register transmitted data and deassert ready.
TX_WAIT: begin
tx <= 1;
if (tx_transmit) begin
tx_dataBuffer <= {1'b1, tx_data, 1'b0};
tx_count <= 0;
tx_sampleCount <= 0;
tx_ready <= 0;
tx_state <= TX_TRANSMITTING;
end else begin
tx_ready <= 1;
end
end
// Shift Out Data
TX_TRANSMITTING: begin
if (enable) begin
if (tx_count == OSF - 1) begin
tx_count <= 0;
tx_sampleCount <= tx_sampleCount + 1;
tx <= tx_dataBuffer[0];
tx_dataBuffer <= {1'b1, tx_dataBuffer[9:1]};
if (tx_sampleCount == 9) begin
tx_state <= TX_WAIT;
end
end else begin
tx_count <= tx_count + 1;
end
end
end
default: begin
tx_state <= TX_WAIT;
end
endcase
end
end
endmodule

40
Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test/.cproject
View file

@ -1,32 +1,32 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?> <?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings"> <storageModule moduleId="org.eclipse.cdt.core.settings">
<buildSystem id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.2028725746"> <buildSystem id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050">
<storageModule id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.2028725746" moduleId="org.eclipse.cdt.core.settings"/> <storageModule id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050" moduleId="org.eclipse.cdt.core.settings"/>
</buildSystem> </buildSystem>
<cconfiguration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.2028725746"> <cconfiguration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050">
<storageModule moduleId="cdtBuildSystem" version="4.0.0"> <storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration buildProperties="" description="" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.2028725746" name="Nios II" parent="org.eclipse.cdt.build.core.prefbase.cfg"> <configuration buildProperties="" description="" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050" name="Nios II" parent="org.eclipse.cdt.build.core.prefbase.cfg">
<folderInfo id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.2028725746." name="/" resourcePath=""> <folderInfo id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050." name="/" resourcePath="">
<toolChain id="altera.nios2.mingw.gcc4.1531733987" name="MinGW Nios II GCC4" superClass="altera.nios2.mingw.gcc4"> <toolChain id="altera.nios2.mingw.gcc4.360127606" name="MinGW Nios II GCC4" superClass="altera.nios2.mingw.gcc4">
<targetPlatform id="altera.nios2.mingw.gcc4.579067770" name="Nios II" superClass="altera.nios2.mingw.gcc4"/> <targetPlatform id="altera.nios2.mingw.gcc4.1269419812" name="Nios II" superClass="altera.nios2.mingw.gcc4"/>
<builder buildPath="${workspace_loc://camera_test}" id="altera.tool.gnu.builder.mingw.811061440" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="altera.tool.gnu.builder.mingw"/> <builder buildPath="${workspace_loc://D8M_Camera_Test}" id="altera.tool.gnu.builder.mingw.49071199" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="altera.tool.gnu.builder.mingw"/>
<tool id="altera.tool.gnu.c.compiler.mingw.2055167219" name="Nios II GCC C Compiler" superClass="altera.tool.gnu.c.compiler.mingw"> <tool id="altera.tool.gnu.c.compiler.mingw.1481046436" name="Nios II GCC C Compiler" superClass="altera.tool.gnu.c.compiler.mingw">
<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.858527592" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/> <inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.586658978" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
</tool> </tool>
<tool id="altera.tool.gnu.cpp.compiler.mingw.40803439" name="Nios II GCC C++ Compiler" superClass="altera.tool.gnu.cpp.compiler.mingw"> <tool id="altera.tool.gnu.cpp.compiler.mingw.1510030252" name="Nios II GCC C++ Compiler" superClass="altera.tool.gnu.cpp.compiler.mingw">
<inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.1689406633" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/> <inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.373987131" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
</tool> </tool>
<tool id="altera.tool.gnu.archiver.mingw.1823496507" name="Nios II GCC Archiver" superClass="altera.tool.gnu.archiver.mingw"/> <tool id="altera.tool.gnu.archiver.mingw.1404974041" name="Nios II GCC Archiver" superClass="altera.tool.gnu.archiver.mingw"/>
<tool id="altera.tool.gnu.c.linker.mingw.1028904150" name="Nios II GCC C Linker" superClass="altera.tool.gnu.c.linker.mingw"/> <tool id="altera.tool.gnu.c.linker.mingw.134928044" name="Nios II GCC C Linker" superClass="altera.tool.gnu.c.linker.mingw"/>
<tool id="altera.tool.gnu.assembler.mingw.1351004326" name="Nios II GCC Assembler" superClass="altera.tool.gnu.assembler.mingw"> <tool id="altera.tool.gnu.assembler.mingw.775279607" name="Nios II GCC Assembler" superClass="altera.tool.gnu.assembler.mingw">
<inputType id="cdt.managedbuild.tool.gnu.assembler.input.1047514398" superClass="cdt.managedbuild.tool.gnu.assembler.input"/> <inputType id="cdt.managedbuild.tool.gnu.assembler.input.258488279" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
</tool> </tool>
</toolChain> </toolChain>
</folderInfo> </folderInfo>
</configuration> </configuration>
</storageModule> </storageModule>
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.2028725746" moduleId="org.eclipse.cdt.core.settings" name="Nios II"> <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050" moduleId="org.eclipse.cdt.core.settings" name="Nios II">
<externalSettings/> <externalSettings/>
<extensions> <extensions>
<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/> <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
@ -40,15 +40,15 @@
</cconfiguration> </cconfiguration>
</storageModule> </storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0"> <storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="camera_test.null.871804730" name="camera_test"/> <project id="D8M_Camera_Test.null.1062948969" name="D8M_Camera_Test"/>
</storageModule> </storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="scannerConfiguration"> <storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.2028725746;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.2028725746.;altera.tool.gnu.c.compiler.mingw.2055167219;cdt.managedbuild.tool.gnu.c.compiler.input.858527592"> <scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050.;altera.tool.gnu.cpp.compiler.mingw.1510030252;cdt.managedbuild.tool.gnu.cpp.compiler.input.373987131">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo> </scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.2028725746;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.2028725746.;altera.tool.gnu.cpp.compiler.mingw.40803439;cdt.managedbuild.tool.gnu.cpp.compiler.input.1689406633"> <scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050.;altera.tool.gnu.c.compiler.mingw.1481046436;cdt.managedbuild.tool.gnu.c.compiler.input.586658978">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo> </scannerConfigBuildInfo>
</storageModule> </storageModule>

2
Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test/.project
View file

@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<projectDescription> <projectDescription>
<name>camera_test</name> <name>D8M_Camera_Test</name>
<comment></comment> <comment></comment>
<projects> <projects>
</projects> </projects>

4
Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test/.settings/language.settings.xml
View file

@ -1,8 +1,8 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?> <?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project> <project>
<configuration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.2028725746" name="Nios II"> <configuration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050" name="Nios II">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider"> <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="-1140257491276676675" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true"> <provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="-1853935238722855090" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/> <language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/> <language-scope id="org.eclipse.cdt.core.g++"/>
</provider> </provider>

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Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test/D8M_Camera_Test.map
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Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test/D8M_Camera_Test.objdump
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200
Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test/main.c
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@ -1,5 +1,3 @@
#include <stdio.h> #include <stdio.h>
#include "I2C_core.h" #include "I2C_core.h"
#include "terasic_includes.h" #include "terasic_includes.h"
@ -22,8 +20,8 @@
#define EXPOSURE_INIT 0x002000 #define EXPOSURE_INIT 0x002000
#define EXPOSURE_STEP 0x100 #define EXPOSURE_STEP 0x100
#define GAIN_INIT 0xFFF #define GAIN_INIT 0x080
#define GAIN_STEP 0xFFF #define GAIN_STEP 0x040
#define DEFAULT_LEVEL 3 #define DEFAULT_LEVEL 3
#define MIPI_REG_PHYClkCtl 0x0056 #define MIPI_REG_PHYClkCtl 0x0056
@ -39,7 +37,8 @@
#define MIPI_REG_FrmErrCnt 0x0080 #define MIPI_REG_FrmErrCnt 0x0080
#define MIPI_REG_MDLErrCnt 0x0090 #define MIPI_REG_MDLErrCnt 0x0090
void mipi_clear_error(void){ void mipi_clear_error(void)
{
MipiBridgeRegWrite(MIPI_REG_CSIStatus, 0x01FF); // clear error MipiBridgeRegWrite(MIPI_REG_CSIStatus, 0x01FF); // clear error
MipiBridgeRegWrite(MIPI_REG_MDLSynErr, 0x0000); // clear error MipiBridgeRegWrite(MIPI_REG_MDLSynErr, 0x0000); // clear error
MipiBridgeRegWrite(MIPI_REG_FrmErrCnt, 0x0000); // clear error MipiBridgeRegWrite(MIPI_REG_FrmErrCnt, 0x0000); // clear error
@ -55,7 +54,8 @@ void mipi_clear_error(void){
MipiBridgeRegWrite(0x0090, 0x00); MipiBridgeRegWrite(0x0090, 0x00);
} }
void mipi_show_error_info(void){ void mipi_show_error_info(void)
{
alt_u16 PHY_status, SCI_status, MDLSynErr, FrmErrCnt, MDLErrCnt; alt_u16 PHY_status, SCI_status, MDLSynErr, FrmErrCnt, MDLErrCnt;
@ -67,7 +67,8 @@ void mipi_show_error_info(void){
printf("PHY_status=%xh, CSI_status=%xh, MDLSynErr=%xh, FrmErrCnt=%xh, MDLErrCnt=%xh\r\n", PHY_status, SCI_status, MDLSynErr, FrmErrCnt, MDLErrCnt); printf("PHY_status=%xh, CSI_status=%xh, MDLSynErr=%xh, FrmErrCnt=%xh, MDLErrCnt=%xh\r\n", PHY_status, SCI_status, MDLSynErr, FrmErrCnt, MDLErrCnt);
} }
void mipi_show_error_info_more(void){ void mipi_show_error_info_more(void)
{
printf("FrmErrCnt = %d\n", MipiBridgeRegRead(0x0080)); printf("FrmErrCnt = %d\n", MipiBridgeRegRead(0x0080));
printf("CRCErrCnt = %d\n", MipiBridgeRegRead(0x0082)); printf("CRCErrCnt = %d\n", MipiBridgeRegRead(0x0082));
printf("CorErrCnt = %d\n", MipiBridgeRegRead(0x0084)); printf("CorErrCnt = %d\n", MipiBridgeRegRead(0x0084));
@ -82,46 +83,31 @@ void mipi_show_error_info_more(void){
printf("CSIPktLen = %d\n", MipiBridgeRegRead(0x006E)); printf("CSIPktLen = %d\n", MipiBridgeRegRead(0x006E));
} }
bool MIPI_Init(void)
{
bool MIPI_Init(void){
bool bSuccess; bool bSuccess;
bSuccess = oc_i2c_init_ex(I2C_OPENCORES_MIPI_BASE, 50 * 1000 * 1000, 400 * 1000); //I2C: 400K bSuccess = oc_i2c_init_ex(I2C_OPENCORES_MIPI_BASE, 50 * 1000 * 1000, 400 * 1000); //I2C: 400K
if (!bSuccess) if (!bSuccess)
{
printf("failed to init MIPI- Bridge i2c\r\n"); printf("failed to init MIPI- Bridge i2c\r\n");
}
usleep(50 * 1000); usleep(50 * 1000);
MipiBridgeInit(); MipiBridgeInit();
usleep(500 * 1000); usleep(500 * 1000);
// bSuccess = oc_i2c_init_ex(I2C_OPENCORES_CAMERA_BASE, 50*1000*1000,400*1000); //I2C: 400K
// if (!bSuccess)
// printf("failed to init MIPI- Camera i2c\r\n");
MipiCameraInit(); MipiCameraInit();
MIPI_BIN_LEVEL(DEFAULT_LEVEL); MIPI_BIN_LEVEL(DEFAULT_LEVEL);
// OV8865_FOCUS_Move_to(340);
// oc_i2c_uninit(I2C_OPENCORES_CAMERA_BASE); // Release I2C bus , due to two I2C master shared!
usleep(1000); usleep(1000);
// oc_i2c_uninit(I2C_OPENCORES_MIPI_BASE);
return bSuccess; return bSuccess;
} }
int main() int main()
{ {
fcntl(STDIN_FILENO, F_SETFL, O_NONBLOCK); fcntl(STDIN_FILENO, F_SETFL, O_NONBLOCK);
printf("DE10-LITE D8M VGA Demo\n"); printf("DE10-LITE D8M VGA Demo\n");
@ -137,14 +123,15 @@ int main()
printf("Image Processor ID: %x\n", IORD(0x42000, EEE_IMGPROC_ID)); printf("Image Processor ID: %x\n", IORD(0x42000, EEE_IMGPROC_ID));
//printf("Image Processor ID: %x\n",IORD(EEE_IMGPROC_0_BASE,EEE_IMGPROC_ID)); //Don't know why this doesn't work - definition is in system.h in BSP //printf("Image Processor ID: %x\n",IORD(EEE_IMGPROC_0_BASE,EEE_IMGPROC_ID)); //Don't know why this doesn't work - definition is in system.h in BSP
usleep(2000); usleep(2000);
// MIPI Init // MIPI Init
if (!MIPI_Init()){ if (!MIPI_Init())
{
printf("MIPI_Init Init failed!\r\n"); printf("MIPI_Init Init failed!\r\n");
}else{ }
else
{
printf("MIPI_Init Init successfully!\r\n"); printf("MIPI_Init Init successfully!\r\n");
} }
@ -158,29 +145,6 @@ int main()
printf("\n"); printf("\n");
// } // }
#if 0 // focus sweep
printf("\nFocus sweep\n");
alt_u16 ii= 350;
alt_u8 dir = 0;
while(1){
if(ii< 50) dir = 1;
else if (ii> 1000) dir =0;
if(dir) ii += 20;
else ii -= 20;
printf("%d\n",ii);
OV8865_FOCUS_Move_to(ii);
usleep(50*1000);
}
#endif
////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////
alt_u16 bin_level = DEFAULT_LEVEL; alt_u16 bin_level = DEFAULT_LEVEL;
alt_u8 manual_focus_step = 10; alt_u8 manual_focus_step = 10;
@ -192,63 +156,50 @@ int main()
OV8865SetExposure(exposureTime); OV8865SetExposure(exposureTime);
OV8865SetGain(gain); OV8865SetGain(gain);
Focus_Init(); Focus_Init();
while(1){
FILE *ser = fopen("/dev/uart_0", "rb+");
fcntl(ser, F_SETFL, O_NONBLOCK);
if (ser)
{
printf("Opened UART\n");
}
else
{
printf("Failed to open UART\n");
while (1)
{
}
}
while (1)
{
// touch KEY0 to trigger Auto focus // touch KEY0 to trigger Auto focus
if((IORD(KEY_BASE,0)&0x03) == 0x02){ if ((IORD(KEY_BASE, 0) & 0x03) == 0x02)
{
current_focus = Focus_Window(320, 240); current_focus = Focus_Window(320, 240);
} }
// touch KEY1 to ZOOM // touch KEY1 to ZOOM
if((IORD(KEY_BASE,0)&0x03) == 0x01){ if ((IORD(KEY_BASE, 0) & 0x03) == 0x01)
if(bin_level == 3 )bin_level = 1; {
else bin_level ++; if (bin_level == 3)
bin_level = 1;
else
bin_level++;
printf("set bin level to %d\n", bin_level); printf("set bin level to %d\n", bin_level);
MIPI_BIN_LEVEL(bin_level); MIPI_BIN_LEVEL(bin_level);
usleep(500000); usleep(500000);
} }
#if 0
if((IORD(KEY_BASE,0)&0x0F) == 0x0E){
current_focus = Focus_Window(320,240);
}
// touch KEY1 to trigger Manual focus - step
if((IORD(KEY_BASE,0)&0x0F) == 0x0D){
if(current_focus > manual_focus_step) current_focus -= manual_focus_step;
else current_focus = 0;
OV8865_FOCUS_Move_to(current_focus);
}
// touch KEY2 to trigger Manual focus + step
if((IORD(KEY_BASE,0)&0x0F) == 0x0B){
current_focus += manual_focus_step;
if(current_focus >1023) current_focus = 1023;
OV8865_FOCUS_Move_to(current_focus);
}
// touch KEY3 to ZOOM
if((IORD(KEY_BASE,0)&0x0F) == 0x07){
if(bin_level == 3 )bin_level = 1;
else bin_level ++;
printf("set bin level to %d\n",bin_level);
MIPI_BIN_LEVEL(bin_level);
usleep(500000);
}
#endif
//Read messages from the image processor and print them on the terminal //Read messages from the image processor and print them on the terminal
while ((IORD(0x42000,EEE_IMGPROC_STATUS)>>8) & 0xff) { //Find out if there are words to read while ((IORD(0x42000, EEE_IMGPROC_STATUS) >> 8) & 0xff)
{ //Find out if there are words to read
int word = IORD(0x42000, EEE_IMGPROC_MSG); //Get next word from message buffer int word = IORD(0x42000, EEE_IMGPROC_MSG); //Get next word from message buffer
if (word == EEE_IMGPROC_MSG_START){ //Newline on message identifier if (fwrite(&word, 4, 1, ser) != 1)
printf("Error writing to UART");
if (word == EEE_IMGPROC_MSG_START) //Newline on message identifier
printf("\n"); printf("\n");
}
printf("%08x ", word); printf("%08x ", word);
} }
@ -258,44 +209,57 @@ int main()
//Process input commands //Process input commands
int in = getchar(); int in = getchar();
switch (in) { switch (in)
case 'e': { {
case 'e':
{
exposureTime += EXPOSURE_STEP; exposureTime += EXPOSURE_STEP;
OV8865SetExposure(exposureTime); OV8865SetExposure(exposureTime);
printf("\nExposure = %x ", exposureTime); printf("\nExposure = %x ", exposureTime);
break;} break;
case 'd': { }
case 'd':
{
exposureTime -= EXPOSURE_STEP; exposureTime -= EXPOSURE_STEP;
OV8865SetExposure(exposureTime); OV8865SetExposure(exposureTime);
printf("\nExposure = %x ", exposureTime); printf("\nExposure = %x ", exposureTime);
break;} break;
case 't': { }
case 't':
{
gain += GAIN_STEP; gain += GAIN_STEP;
OV8865SetGain(gain); OV8865SetGain(gain);
printf("\nGain = %x ", gain); printf("\nGain = %x ", gain);
break;} break;
case 'g': { }
case 'g':
{
gain -= GAIN_STEP; gain -= GAIN_STEP;
OV8865SetGain(gain); OV8865SetGain(gain);
printf("\nGain = %x ", gain); printf("\nGain = %x ", gain);
break;} break;
case 'r': { }
current_focus += manual_focus_step; case 'r':
if(current_focus >1023) current_focus = 1023; {
OV8865_FOCUS_Move_to(current_focus); current_focus += manual_focus_step;
printf("\nFocus = %x ",current_focus); if (current_focus > 1023)
break;} current_focus = 1023;
case 'f': { OV8865_FOCUS_Move_to(current_focus);
if(current_focus > manual_focus_step) current_focus -= manual_focus_step; printf("\nFocus = %x ", current_focus);
OV8865_FOCUS_Move_to(current_focus); break;
printf("\nFocus = %x ",current_focus); }
break;} case 'f':
{
if (current_focus > manual_focus_step)
current_focus -= manual_focus_step;
OV8865_FOCUS_Move_to(current_focus);
printf("\nFocus = %x ", current_focus);
break;
}
} }
//Main loop delay //Main loop delay
usleep(10000); usleep(10000);
}; };
return 0; return 0;
} }

12
Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test_bsp/Makefile
View file

@ -239,6 +239,17 @@ altera_avalon_timer_driver_C_LIB_SRCS := \
$(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_ts.c \ $(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_ts.c \
$(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_vars.c $(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_vars.c
# altera_avalon_uart_driver sources root
altera_avalon_uart_driver_SRCS_ROOT := drivers
# altera_avalon_uart_driver sources
altera_avalon_uart_driver_C_LIB_SRCS := \
$(altera_avalon_uart_driver_SRCS_ROOT)/src/altera_avalon_uart_fd.c \
$(altera_avalon_uart_driver_SRCS_ROOT)/src/altera_avalon_uart_init.c \
$(altera_avalon_uart_driver_SRCS_ROOT)/src/altera_avalon_uart_ioctl.c \
$(altera_avalon_uart_driver_SRCS_ROOT)/src/altera_avalon_uart_read.c \
$(altera_avalon_uart_driver_SRCS_ROOT)/src/altera_avalon_uart_write.c
# altera_nios2_gen2_hal_driver sources root # altera_nios2_gen2_hal_driver sources root
altera_nios2_gen2_hal_driver_SRCS_ROOT := HAL altera_nios2_gen2_hal_driver_SRCS_ROOT := HAL
@ -341,6 +352,7 @@ COMPONENT_C_LIB_SRCS += \
$(altera_avalon_jtag_uart_driver_C_LIB_SRCS) \ $(altera_avalon_jtag_uart_driver_C_LIB_SRCS) \
$(altera_avalon_sysid_qsys_driver_C_LIB_SRCS) \ $(altera_avalon_sysid_qsys_driver_C_LIB_SRCS) \
$(altera_avalon_timer_driver_C_LIB_SRCS) \ $(altera_avalon_timer_driver_C_LIB_SRCS) \
$(altera_avalon_uart_driver_C_LIB_SRCS) \
$(altera_nios2_gen2_hal_driver_C_LIB_SRCS) \ $(altera_nios2_gen2_hal_driver_C_LIB_SRCS) \
$(hal_C_LIB_SRCS) $(hal_C_LIB_SRCS)

319
Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test_bsp/drivers/inc/altera_avalon_uart.h Normal file
View file

@ -0,0 +1,319 @@
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#ifndef __ALT_AVALON_UART_H__
#define __ALT_AVALON_UART_H__
#include <stddef.h>
#include <sys/termios.h>
#include "sys/alt_warning.h"
#include "os/alt_sem.h"
#include "os/alt_flag.h"
#include "alt_types.h"
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
#if defined(ALT_USE_SMALL_DRIVERS) || defined(ALTERA_AVALON_UART_SMALL)
/*
***********************************************************************
*********************** SMALL DRIVER **********************************
***********************************************************************
*/
/*
* State structure definition. Each instance of the driver uses one
* of these structures to hold its associated state.
*/
typedef struct altera_avalon_uart_state_s
{
unsigned int base;
} altera_avalon_uart_state;
/*
* The macro ALTERA_AVALON_UART_STATE_INSTANCE is used by the
* auto-generated file alt_sys_init.c to create an instance of this
* device driver state.
*/
#define ALTERA_AVALON_UART_STATE_INSTANCE(name, state) \
altera_avalon_uart_state state = \
{ \
name##_BASE \
}
/*
* The macro ALTERA_AVALON_UART_STATE_INIT is used by the auto-generated file
* alt_sys_init.c to initialize an instance of the device driver state.
*/
#define ALTERA_AVALON_UART_STATE_INIT(name, state)
#else /* fast driver */
/*
**********************************************************************
*********************** FAST DRIVER **********************************
**********************************************************************
*/
/*
* ALT_AVALON_UART_READ_RDY and ALT_AVALON_UART_WRITE_RDY are the bitmasks
* that define uC/OS-II event flags that are releated to this device.
*
* ALT_AVALON_UART_READY_RDY indicates that there is read data in the buffer
* ready to be processed. ALT_UART_WRITE_RDY indicates that the transmitter is
* ready for more data.
*/
#define ALT_UART_READ_RDY 0x1
#define ALT_UART_WRITE_RDY 0x2
/*
* ALT_AVALON_UART_BUF_LEN is the length of the circular buffers used to hold
* pending transmit and receive data. This value must be a power of two.
*/
#define ALT_AVALON_UART_BUF_LEN (64)
/*
* ALT_AVALON_UART_BUF_MSK is used as an internal convenience for detecting
* the end of the arrays used to implement the transmit and receive buffers.
*/
#define ALT_AVALON_UART_BUF_MSK (ALT_AVALON_UART_BUF_LEN - 1)
/*
* This is somewhat of an ugly hack, but we need some mechanism for
* representing the non-standard 9 bit mode provided by this UART. In this
* case we abscond with the 5 bit mode setting. The value CS5 is defined in
* termios.h.
*/
#define CS9 CS5
/*
* The value ALT_AVALON_UART_FB is a value set in the devices flag field to
* indicate that the device has a fixed baud rate; i.e. if this flag is set
* software can not control the baud rate of the device.
*/
#define ALT_AVALON_UART_FB 0x1
/*
* The value ALT_AVALON_UART_FC is a value set in the device flag field to
* indicate the the device is using flow control, i.e. the driver must
* throttle on transmit if the nCTS pin is low.
*/
#define ALT_AVALON_UART_FC 0x2
/*
* The altera_avalon_uart_state structure is used to hold device specific data.
* This includes the transmit and receive buffers.
*
* An instance of this structure is created in the auto-generated
* alt_sys_init.c file for each UART listed in the systems PTF file. This is
* done using the ALTERA_AVALON_UART_STATE_INSTANCE macro given below.
*/
typedef struct altera_avalon_uart_state_s
{
void* base; /* The base address of the device */
alt_u32 ctrl; /* Shadow value of the control register */
volatile alt_u32 rx_start; /* Start of the pending receive data */
volatile alt_u32 rx_end; /* End of the pending receive data */
volatile alt_u32 tx_start; /* Start of the pending transmit data */
volatile alt_u32 tx_end; /* End of the pending transmit data */
#ifdef ALTERA_AVALON_UART_USE_IOCTL
struct termios termios; /* Current device configuration */
alt_u32 freq; /* Current baud rate */
#endif
alt_u32 flags; /* Configuation flags */
ALT_FLAG_GRP (events) /* Event flags used for
* foreground/background in mult-threaded
* mode */
ALT_SEM (read_lock) /* Semaphore used to control access to the
* read buffer in multi-threaded mode */
ALT_SEM (write_lock) /* Semaphore used to control access to the
* write buffer in multi-threaded mode */
volatile alt_u8 rx_buf[ALT_AVALON_UART_BUF_LEN]; /* The receive buffer */
volatile alt_u8 tx_buf[ALT_AVALON_UART_BUF_LEN]; /* The transmit buffer */
} altera_avalon_uart_state;
/*
* Conditionally define the data structures used to process ioctl requests.
* The following macros are defined for use in creating a device instance:
*
* ALTERA_AVALON_UART_TERMIOS - Initialise the termios structure used to
* describe the UART configuration.
* ALTERA_AVALON_UART_FREQ - Initialise the 'freq' field of the device
* structure, if the field exists.
* ALTERA_AVALON_UART_IOCTL - Initialise the 'ioctl' field of the device
* callback structure, if ioctls are enabled.
*/
#ifdef ALTERA_AVALON_UART_USE_IOCTL
#define ALTERA_AVALON_UART_TERMIOS(stop_bits, \
parity, \
odd_parity, \
data_bits, \
ctsrts, \
baud) \
{ \
0, \
0, \
((stop_bits == 2) ? CSTOPB: 0) | \
((parity) ? PARENB: 0) | \
((odd_parity) ? PAODD: 0) | \
((data_bits == 7) ? CS7: (data_bits == 9) ? CS9: CS8) | \
((ctsrts) ? CRTSCTS : 0), \
0, \
0, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
baud, \
baud \
},
#define ALTERA_AVALON_UART_FREQ(name) name##_FREQ,
#else /* !ALTERA_AVALON_UART_USE_IOCTL */
#define ALTERA_AVALON_UART_TERMIOS(stop_bits, \
parity, \
odd_parity, \
data_bits, \
ctsrts, \
baud)
#define ALTERA_AVALON_UART_FREQ(name)
#endif /* ALTERA_AVALON_UART_USE_IOCTL */
/*
* The macro ALTERA_AVALON_UART_INSTANCE is used by the auto-generated file
* alt_sys_init.c to create an instance of this device driver state.
*/
#define ALTERA_AVALON_UART_STATE_INSTANCE(name, state) \
altera_avalon_uart_state state = \
{ \
(void*) name##_BASE, \
0, \
0, \
0, \
0, \
0, \
ALTERA_AVALON_UART_TERMIOS(name##_STOP_BITS, \
(name##_PARITY == 'N'), \
(name##_PARITY == 'O'), \
name##_DATA_BITS, \
name##_USE_CTS_RTS, \
name##_BAUD) \
ALTERA_AVALON_UART_FREQ(name) \
(name##_FIXED_BAUD ? ALT_AVALON_UART_FB : 0) | \
(name##_USE_CTS_RTS ? ALT_AVALON_UART_FC : 0) \
}
/*
* altera_avalon_uart_init() is called by the auto-generated function
* alt_sys_init() for each UART in the system. This is done using the
* ALTERA_AVALON_UART_INIT macro given below.
*
* This function is responsible for performing all the run time initilisation
* for a device instance, i.e. registering the interrupt handler, and
* regestering the device with the system.
*/
extern void altera_avalon_uart_init(altera_avalon_uart_state* sp,
alt_u32 irq_controller_id, alt_u32 irq);
/*
* The macro ALTERA_AVALON_UART_STATE_INIT is used by the auto-generated file
* alt_sys_init.c to initialize an instance of the device driver state.
*
* This macro performs a sanity check to ensure that the interrupt has been
* connected for this device. If not, then an apropriate error message is
* generated at build time.
*/
#define ALTERA_AVALON_UART_STATE_INIT(name, state) \
if (name##_IRQ == ALT_IRQ_NOT_CONNECTED) \
{ \
ALT_LINK_ERROR ("Error: Interrupt not connected for " #name ". " \
"You have selected the interrupt driven version of " \
"the ALTERA Avalon UART driver, but the interrupt is " \
"not connected for this device. You can select a " \
"polled mode driver by checking the 'small driver' " \
"option in the HAL configuration window, or by " \
"using the -DALTERA_AVALON_UART_SMALL preprocessor " \
"flag."); \
} \
else \
{ \
altera_avalon_uart_init(&state, name##_IRQ_INTERRUPT_CONTROLLER_ID, \
name##_IRQ); \
}
#endif /* small driver */
/*
* Include in case non-direct version of driver required.
*/
#include "altera_avalon_uart_fd.h"
/*
* Map alt_sys_init macros to direct or non-direct versions.
*/
#ifdef ALT_USE_DIRECT_DRIVERS
#define ALTERA_AVALON_UART_INSTANCE(name, state) \
ALTERA_AVALON_UART_STATE_INSTANCE(name, state)
#define ALTERA_AVALON_UART_INIT(name, state) \
ALTERA_AVALON_UART_STATE_INIT(name, state)
#else /* !ALT_USE_DIRECT_DRIVERS */
#define ALTERA_AVALON_UART_INSTANCE(name, dev) \
ALTERA_AVALON_UART_DEV_INSTANCE(name, dev)
#define ALTERA_AVALON_UART_INIT(name, dev) \
ALTERA_AVALON_UART_DEV_INIT(name, dev)
#endif /* ALT_USE_DIRECT_DRIVERS */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALT_AVALON_UART_H__ */

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/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#ifndef __ALT_AVALON_UART_FD_H__
#define __ALT_AVALON_UART_FD_H__
#include "sys/alt_dev.h"
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/*
* Externally referenced routines
*/
extern int altera_avalon_uart_read_fd (alt_fd* fd, char* ptr, int len);
extern int altera_avalon_uart_write_fd (alt_fd* fd, const char* ptr,
int len);
/*
* Device structure definition. This is needed by alt_sys_init in order to
* reserve memory for the device instance.
*/
typedef struct altera_avalon_uart_dev_s
{
alt_dev dev;
altera_avalon_uart_state state;
} altera_avalon_uart_dev;
#if defined(ALT_USE_SMALL_DRIVERS) || defined(ALTERA_AVALON_UART_SMALL)
/*
* Macros used by alt_sys_init when the ALT file descriptor facility is used.
*/
#define ALTERA_AVALON_UART_DEV_INSTANCE(name, d) \
static altera_avalon_uart_dev d = \
{ \
{ \
ALT_LLIST_ENTRY, \
name##_NAME, \
NULL, /* open */ \
NULL, /* close */ \
altera_avalon_uart_read_fd, \
altera_avalon_uart_write_fd, \
NULL, /* lseek */ \
NULL, /* fstat */ \
NULL, /* ioctl */ \
}, \
{ \
name##_BASE, \
} \
}
#define ALTERA_AVALON_UART_DEV_INIT(name, d) alt_dev_reg (&d.dev)
#else /* use fast version of the driver */
extern int altera_avalon_uart_ioctl_fd (alt_fd* fd, int req, void* arg);
extern int altera_avalon_uart_close_fd(alt_fd* fd);
#ifdef ALTERA_AVALON_UART_USE_IOCTL
#define ALTERA_AVALON_UART_IOCTL_FD altera_avalon_uart_ioctl_fd
#else
#define ALTERA_AVALON_UART_IOCTL_FD NULL
#endif
#define ALTERA_AVALON_UART_DEV_INSTANCE(name, d) \
static altera_avalon_uart_dev d = \
{ \
{ \
ALT_LLIST_ENTRY, \
name##_NAME, \
NULL, /* open */ \
altera_avalon_uart_close_fd, \
altera_avalon_uart_read_fd, \
altera_avalon_uart_write_fd, \
NULL, /* lseek */ \
NULL, /* fstat */ \
ALTERA_AVALON_UART_IOCTL_FD, \
}, \
{ \
(void*) name##_BASE, \
0, \
0, \
0, \
0, \
0, \
ALTERA_AVALON_UART_TERMIOS(name##_STOP_BITS, \
(name##_PARITY == 'N'), \
(name##_PARITY == 'O'), \
name##_DATA_BITS, \
name##_USE_CTS_RTS, \
name##_BAUD) \
ALTERA_AVALON_UART_FREQ(name) \
(name##_FIXED_BAUD ? ALT_AVALON_UART_FB : 0) | \
(name##_USE_CTS_RTS ? ALT_AVALON_UART_FC : 0) \
} \
}
#define ALTERA_AVALON_UART_DEV_INIT(name, d) \
{ \
ALTERA_AVALON_UART_STATE_INIT(name, d.state); \
\
/* make the device available to the system */ \
alt_dev_reg(&d.dev); \
}
#endif /* fast driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALT_AVALON_UART_FD_H__ */

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/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#ifndef __ALTERA_AVALON_UART_REGS_H__
#define __ALTERA_AVALON_UART_REGS_H__
#include <io.h>
#define ALTERA_AVALON_UART_RXDATA_REG 0
#define IOADDR_ALTERA_AVALON_UART_RXDATA(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_RXDATA_REG)
#define IORD_ALTERA_AVALON_UART_RXDATA(base) \
IORD(base, ALTERA_AVALON_UART_RXDATA_REG)
#define IOWR_ALTERA_AVALON_UART_RXDATA(base, data) \
IOWR(base, ALTERA_AVALON_UART_RXDATA_REG, data)
#define ALTERA_AVALON_UART_TXDATA_REG 1
#define IOADDR_ALTERA_AVALON_UART_TXDATA(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_TXDATA_REG)
#define IORD_ALTERA_AVALON_UART_TXDATA(base) \
IORD(base, ALTERA_AVALON_UART_TXDATA_REG)
#define IOWR_ALTERA_AVALON_UART_TXDATA(base, data) \
IOWR(base, ALTERA_AVALON_UART_TXDATA_REG, data)
#define ALTERA_AVALON_UART_STATUS_REG 2
#define IOADDR_ALTERA_AVALON_UART_STATUS(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_STATUS_REG)
#define IORD_ALTERA_AVALON_UART_STATUS(base) \
IORD(base, ALTERA_AVALON_UART_STATUS_REG)
#define IOWR_ALTERA_AVALON_UART_STATUS(base, data) \
IOWR(base, ALTERA_AVALON_UART_STATUS_REG, data)
#define ALTERA_AVALON_UART_STATUS_PE_MSK (0x1)
#define ALTERA_AVALON_UART_STATUS_PE_OFST (0)
#define ALTERA_AVALON_UART_STATUS_FE_MSK (0x2)
#define ALTERA_AVALON_UART_STATUS_FE_OFST (1)
#define ALTERA_AVALON_UART_STATUS_BRK_MSK (0x4)
#define ALTERA_AVALON_UART_STATUS_BRK_OFST (2)
#define ALTERA_AVALON_UART_STATUS_ROE_MSK (0x8)
#define ALTERA_AVALON_UART_STATUS_ROE_OFST (3)
#define ALTERA_AVALON_UART_STATUS_TOE_MSK (0x10)
#define ALTERA_AVALON_UART_STATUS_TOE_OFST (4)
#define ALTERA_AVALON_UART_STATUS_TMT_MSK (0x20)
#define ALTERA_AVALON_UART_STATUS_TMT_OFST (5)
#define ALTERA_AVALON_UART_STATUS_TRDY_MSK (0x40)
#define ALTERA_AVALON_UART_STATUS_TRDY_OFST (6)
#define ALTERA_AVALON_UART_STATUS_RRDY_MSK (0x80)
#define ALTERA_AVALON_UART_STATUS_RRDY_OFST (7)
#define ALTERA_AVALON_UART_STATUS_E_MSK (0x100)
#define ALTERA_AVALON_UART_STATUS_E_OFST (8)
#define ALTERA_AVALON_UART_STATUS_DCTS_MSK (0x400)
#define ALTERA_AVALON_UART_STATUS_DCTS_OFST (10)
#define ALTERA_AVALON_UART_STATUS_CTS_MSK (0x800)
#define ALTERA_AVALON_UART_STATUS_CTS_OFST (11)
#define ALTERA_AVALON_UART_STATUS_EOP_MSK (0x1000)
#define ALTERA_AVALON_UART_STATUS_EOP_OFST (12)
#define ALTERA_AVALON_UART_CONTROL_REG 3
#define IOADDR_ALTERA_AVALON_UART_CONTROL(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_CONTROL_REG)
#define IORD_ALTERA_AVALON_UART_CONTROL(base) \
IORD(base, ALTERA_AVALON_UART_CONTROL_REG)
#define IOWR_ALTERA_AVALON_UART_CONTROL(base, data) \
IOWR(base, ALTERA_AVALON_UART_CONTROL_REG, data)
#define ALTERA_AVALON_UART_CONTROL_PE_MSK (0x1)
#define ALTERA_AVALON_UART_CONTROL_PE_OFST (0)
#define ALTERA_AVALON_UART_CONTROL_FE_MSK (0x2)
#define ALTERA_AVALON_UART_CONTROL_FE_OFST (1)
#define ALTERA_AVALON_UART_CONTROL_BRK_MSK (0x4)
#define ALTERA_AVALON_UART_CONTROL_BRK_OFST (2)
#define ALTERA_AVALON_UART_CONTROL_ROE_MSK (0x8)
#define ALTERA_AVALON_UART_CONTROL_ROE_OFST (3)
#define ALTERA_AVALON_UART_CONTROL_TOE_MSK (0x10)
#define ALTERA_AVALON_UART_CONTROL_TOE_OFST (4)
#define ALTERA_AVALON_UART_CONTROL_TMT_MSK (0x20)
#define ALTERA_AVALON_UART_CONTROL_TMT_OFST (5)
#define ALTERA_AVALON_UART_CONTROL_TRDY_MSK (0x40)
#define ALTERA_AVALON_UART_CONTROL_TRDY_OFST (6)
#define ALTERA_AVALON_UART_CONTROL_RRDY_MSK (0x80)
#define ALTERA_AVALON_UART_CONTROL_RRDY_OFST (7)
#define ALTERA_AVALON_UART_CONTROL_E_MSK (0x100)
#define ALTERA_AVALON_UART_CONTROL_E_OFST (8)
#define ALTERA_AVALON_UART_CONTROL_DCTS_MSK (0x400)
#define ALTERA_AVALON_UART_CONTROL_DCTS_OFST (10)
#define ALTERA_AVALON_UART_CONTROL_RTS_MSK (0x800)
#define ALTERA_AVALON_UART_CONTROL_RTS_OFST (11)
#define ALTERA_AVALON_UART_CONTROL_EOP_MSK (0x1000)
#define ALTERA_AVALON_UART_CONTROL_EOP_OFST (12)
#define ALTERA_AVALON_UART_DIVISOR_REG 4
#define IOADDR_ALTERA_AVALON_UART_DIVISOR(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_DIVISOR_REG)
#define IORD_ALTERA_AVALON_UART_DIVISOR(base) \
IORD(base, ALTERA_AVALON_UART_DIVISOR_REG)
#define IOWR_ALTERA_AVALON_UART_DIVISOR(base, data) \
IOWR(base, ALTERA_AVALON_UART_DIVISOR_REG, data)
#define ALTERA_AVALON_UART_EOP_REG 5
#define IOADDR_ALTERA_AVALON_UART_EOP(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_EOP_REG)
#define IORD_ALTERA_AVALON_UART_EOP(base) \
IORD(base, ALTERA_AVALON_UART_EOP_REG)
#define IOWR_ALTERA_AVALON_UART_EOP(base, data) \
IOWR(base, ALTERA_AVALON_UART_EOP_REG, data)
#define ALTERA_AVALON_UART_EOP_MSK (0xFF)
#define ALTERA_AVALON_UART_EOP_OFST (0)
#endif /* __ALTERA_AVALON_UART_REGS_H__ */

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/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include "alt_types.h"
#include "sys/alt_dev.h"
#include "altera_avalon_uart.h"
extern int altera_avalon_uart_read(altera_avalon_uart_state* sp,
char* buffer, int space, int flags);
extern int altera_avalon_uart_write(altera_avalon_uart_state* sp,
const char* ptr, int count, int flags);
extern int altera_avalon_uart_ioctl(altera_avalon_uart_state* sp,
int req, void* arg);
extern int altera_avalon_uart_close(altera_avalon_uart_state* sp, int flags);
/* ----------------------------------------------------------------------- */
/* --------------------- WRAPPERS FOR ALT FD SUPPORT --------------------- */
/*
*
*/
int
altera_avalon_uart_read_fd(alt_fd* fd, char* buffer, int space)
{
altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev;
return altera_avalon_uart_read(&dev->state, buffer, space,
fd->fd_flags);
}
int
altera_avalon_uart_write_fd(alt_fd* fd, const char* buffer, int space)
{
altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev;
return altera_avalon_uart_write(&dev->state, buffer, space,
fd->fd_flags);
}
#if !defined(ALT_USE_SMALL_DRIVERS) && !defined(ALTERA_AVALON_UART_SMALL)
/*
* Fast driver
*/
/*
* To reduce the code footprint of this driver, the ioctl() function is not
* included by default. If you wish to use the ioctl features provided
* below, you can do so by adding the option : -DALTERA_AVALON_UART_USE_IOCTL
* to CPPFLAGS in the Makefile (or through the Eclipse IDE).
*/
#ifdef ALTERA_AVALON_UART_USE_IOCTL
int
altera_avalon_uart_ioctl_fd(alt_fd* fd, int req, void* arg)
{
altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev;
return altera_avalon_uart_ioctl(&dev->state, req, arg);
}
#endif /* ALTERA_AVALON_UART_USE_IOCTL */
int
altera_avalon_uart_close_fd(alt_fd* fd)
{
altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev;
return altera_avalon_uart_close(&dev->state, fd->fd_flags);
}
#endif /* fast driver */

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/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include <fcntl.h>
#include "sys/alt_dev.h"
#include "sys/alt_irq.h"
#include "sys/ioctl.h"
#include "sys/alt_errno.h"
#include "altera_avalon_uart.h"
#include "altera_avalon_uart_regs.h"
#if !defined(ALT_USE_SMALL_DRIVERS) && !defined(ALTERA_AVALON_UART_SMALL)
/* ----------------------------------------------------------- */
/* ------------------------- FAST DRIVER --------------------- */
/* ----------------------------------------------------------- */
/*
* altera_avalon_uart_init() is called by the auto-generated function
* alt_sys_init() in order to initialize a particular instance of this device.
* It is responsible for configuring the device and associated software
* constructs.
*/
#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
static void altera_avalon_uart_irq(void* context);
#else
static void altera_avalon_uart_irq(void* context, alt_u32 id);
#endif
static void altera_avalon_uart_rxirq(altera_avalon_uart_state* sp,
alt_u32 status);
static void altera_avalon_uart_txirq(altera_avalon_uart_state* sp,
alt_u32 status);
void
altera_avalon_uart_init(altera_avalon_uart_state* sp,
alt_u32 irq_controller_id, alt_u32 irq)
{
void* base = sp->base;
int error;
/*
* Initialise the read and write flags and the semaphores used to
* protect access to the circular buffers when running in a multi-threaded
* environment.
*/
error = ALT_FLAG_CREATE (&sp->events, 0) ||
ALT_SEM_CREATE (&sp->read_lock, 1) ||
ALT_SEM_CREATE (&sp->write_lock, 1);
if (!error)
{
/* enable interrupts at the device */
sp->ctrl = ALTERA_AVALON_UART_CONTROL_RTS_MSK |
ALTERA_AVALON_UART_CONTROL_RRDY_MSK |
ALTERA_AVALON_UART_CONTROL_DCTS_MSK;
IOWR_ALTERA_AVALON_UART_CONTROL(base, sp->ctrl);
/* register the interrupt handler */
#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
alt_ic_isr_register(irq_controller_id, irq, altera_avalon_uart_irq, sp,
0x0);
#else
alt_irq_register (irq, sp, altera_avalon_uart_irq);
#endif
}
}
/*
* altera_avalon_uart_irq() is the interrupt handler registered at
* configuration time for processing UART interrupts. It vectors
* interrupt requests to either altera_avalon_uart_rxirq() (for incoming
* data), or altera_avalon_uart_txirq() (for outgoing data).
*/
#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
static void altera_avalon_uart_irq(void* context)
#else
static void altera_avalon_uart_irq(void* context, alt_u32 id)
#endif
{
alt_u32 status;
altera_avalon_uart_state* sp = (altera_avalon_uart_state*) context;
void* base = sp->base;
/*
* Read the status register in order to determine the cause of the
* interrupt.
*/
status = IORD_ALTERA_AVALON_UART_STATUS(base);
/* Clear any error flags set at the device */
IOWR_ALTERA_AVALON_UART_STATUS(base, 0);
/* Dummy read to ensure IRQ is negated before ISR returns */
IORD_ALTERA_AVALON_UART_STATUS(base);
/* process a read irq */
if (status & ALTERA_AVALON_UART_STATUS_RRDY_MSK)
{
altera_avalon_uart_rxirq(sp, status);
}
/* process a write irq */
if (status & (ALTERA_AVALON_UART_STATUS_TRDY_MSK |
ALTERA_AVALON_UART_STATUS_DCTS_MSK))
{
altera_avalon_uart_txirq(sp, status);
}
}
/*
* altera_avalon_uart_rxirq() is called by altera_avalon_uart_irq() to
* process a receive interrupt. It transfers the incoming character into
* the receive circular buffer, and sets the apropriate flags to indicate
* that there is data ready to be processed.
*/
static void
altera_avalon_uart_rxirq(altera_avalon_uart_state* sp, alt_u32 status)
{
alt_u32 next;
/* If there was an error, discard the data */
if (status & (ALTERA_AVALON_UART_STATUS_PE_MSK |
ALTERA_AVALON_UART_STATUS_FE_MSK))
{
return;
}
/*
* In a multi-threaded environment, set the read event flag to indicate
* that there is data ready. This is only done if the circular buffer was
* previously empty.
*/
if (sp->rx_end == sp->rx_start)
{
ALT_FLAG_POST (sp->events, ALT_UART_READ_RDY, OS_FLAG_SET);
}
/* Determine which slot to use next in the circular buffer */
next = (sp->rx_end + 1) & ALT_AVALON_UART_BUF_MSK;
/* Transfer data from the device to the circular buffer */
sp->rx_buf[sp->rx_end] = IORD_ALTERA_AVALON_UART_RXDATA(sp->base);
sp->rx_end = next;
next = (sp->rx_end + 1) & ALT_AVALON_UART_BUF_MSK;
/*
* If the cicular buffer was full, disable interrupts. Interrupts will be
* re-enabled when data is removed from the buffer.
*/
if (next == sp->rx_start)
{
sp->ctrl &= ~ALTERA_AVALON_UART_CONTROL_RRDY_MSK;
IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl);
}
}
/*
* altera_avalon_uart_txirq() is called by altera_avalon_uart_irq() to
* process a transmit interrupt. It transfers data from the transmit
* buffer to the device, and sets the apropriate flags to indicate that
* there is data ready to be processed.
*/
static void
altera_avalon_uart_txirq(altera_avalon_uart_state* sp, alt_u32 status)
{
/* Transfer data if there is some ready to be transfered */
if (sp->tx_start != sp->tx_end)
{
/*
* If the device is using flow control (i.e. RTS/CTS), then the
* transmitter is required to throttle if CTS is high.
*/
if (!(sp->flags & ALT_AVALON_UART_FC) ||
(status & ALTERA_AVALON_UART_STATUS_CTS_MSK))
{
/*
* In a multi-threaded environment, set the write event flag to indicate
* that there is space in the circular buffer. This is only done if the
* buffer was previously empty.
*/
if (sp->tx_start == ((sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK))
{
ALT_FLAG_POST (sp->events,
ALT_UART_WRITE_RDY,
OS_FLAG_SET);
}
/* Write the data to the device */
IOWR_ALTERA_AVALON_UART_TXDATA(sp->base, sp->tx_buf[sp->tx_start]);
sp->tx_start = (++sp->tx_start) & ALT_AVALON_UART_BUF_MSK;
/*
* In case the tranmit interrupt had previously been disabled by
* detecting a low value on CTS, it is reenabled here.
*/
sp->ctrl |= ALTERA_AVALON_UART_CONTROL_TRDY_MSK;
}
else
{
/*
* CTS is low and we are using flow control, so disable the transmit
* interrupt while we wait for CTS to go high again. This will be
* detected using the DCTS interrupt.
*
* There is a race condition here. "status" may indicate that
* CTS is low, but it actually went high before DCTS was cleared on
* the last write to the status register. To avoid this resulting in
* deadlock, it's necessary to re-check the status register here
* before throttling.
*/
status = IORD_ALTERA_AVALON_UART_STATUS(sp->base);
if (!(status & ALTERA_AVALON_UART_STATUS_CTS_MSK))
{
sp->ctrl &= ~ALTERA_AVALON_UART_CONTROL_TRDY_MSK;
}
}
}
/*
* If the circular buffer is empty, disable the interrupt. This will be
* re-enabled when new data is placed in the buffer.
*/
if (sp->tx_start == sp->tx_end)
{
sp->ctrl &= ~(ALTERA_AVALON_UART_CONTROL_TRDY_MSK |
ALTERA_AVALON_UART_CONTROL_DCTS_MSK);
}
IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl);
}
/*
* The close() routine is implemented to drain the UART transmit buffer
* when not in "small" mode. This routine will wait for transimt data to be
* emptied unless the driver flags have been set to non-blocking mode.
* This routine should be called indirectly (i.e. though the C library
* close() routine) so that the file descriptor associated with the relevant
* stream (i.e. stdout) can be closed as well. This routine does not manage
* file descriptors.
*
* The close routine is not implemented for the small driver; instead it will
* map to null. This is because the small driver simply waits while characters
* are transmitted; there is no interrupt-serviced buffer to empty
*/
int altera_avalon_uart_close(altera_avalon_uart_state* sp, int flags)
{
/*
* Wait for all transmit data to be emptied by the UART ISR.
*/
while (sp->tx_start != sp->tx_end) {
if (flags & O_NONBLOCK) {
return -EWOULDBLOCK;
}
}
return 0;
}
#endif /* fast driver */

153
Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test_bsp/drivers/src/altera_avalon_uart_ioctl.c Normal file
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/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include <fcntl.h>
#include <string.h>
#include "sys/alt_irq.h"
#include "sys/ioctl.h"
#include "sys/alt_errno.h"
#include "altera_avalon_uart_regs.h"
#include "altera_avalon_uart.h"
#if !defined(ALT_USE_SMALL_DRIVERS) && !defined(ALTERA_AVALON_UART_SMALL)
/* ----------------------------------------------------------- */
/* ------------------------- FAST DRIVER --------------------- */
/* ----------------------------------------------------------- */
/*
* To reduce the code footprint of this driver, the ioctl() function is not
* included by default. If you wish to use the ioctl features provided
* below, you can do so by adding the option : -DALTERA_AVALON_UART_USE_IOCTL
* to CPPFLAGS in the Makefile (or through the Eclipse IDE).
*/
#ifdef ALTERA_AVALON_UART_USE_IOCTL
/*
* altera_avalon_uart_ioctl() is called by the system ioctl() function to handle
* ioctl requests for the UART. The only ioctl requests supported are TIOCMGET
* and TIOCMSET.
*
* TIOCMGET returns a termios structure that describes the current device
* configuration.
*
* TIOCMSET sets the device (if possible) to match the requested configuration.
* The requested configuration is described using a termios structure passed
* through the input argument "arg".
*/
static int altera_avalon_uart_tiocmget(altera_avalon_uart_state* sp,
struct termios* term);
static int altera_avalon_uart_tiocmset(altera_avalon_uart_state* sp,
struct termios* term);
int
altera_avalon_uart_ioctl(altera_avalon_uart_state* sp, int req, void* arg)
{
int rc = -ENOTTY;
switch (req)
{
case TIOCMGET:
rc = altera_avalon_uart_tiocmget(sp, (struct termios*) arg);
break;
case TIOCMSET:
rc = altera_avalon_uart_tiocmset(sp, (struct termios*) arg);
break;
default:
break;
}
return rc;
}
/*
* altera_avalon_uart_tiocmget() is used by altera_avalon_uart_ioctl() to fill
* in the input termios structure with the current device configuration.
*
* See termios.h for further details on the contents of the termios structure.
*/
static int
altera_avalon_uart_tiocmget(altera_avalon_uart_state* sp,
struct termios* term)
{
memcpy (term, &sp->termios, sizeof (struct termios));
return 0;
}
/*
* altera_avalon_uart_tiocmset() is used by altera_avalon_uart_ioctl() to
* configure the device according to the settings in the input termios
* structure. In practice the only configuration that can be changed is the
* baud rate, and then only if the hardware is configured to have a writable
* baud register.
*/
static int
altera_avalon_uart_tiocmset(altera_avalon_uart_state* sp,
struct termios* term)
{
speed_t speed;
speed = sp->termios.c_ispeed;
/* Update the settings if the hardware supports it */
if (!(sp->flags & ALT_AVALON_UART_FB))
{
sp->termios.c_ispeed = sp->termios.c_ospeed = term->c_ispeed;
}
/*
* If the request was for an unsupported setting, return an error.
*/
if (memcmp(term, &sp->termios, sizeof (struct termios)))
{
sp->termios.c_ispeed = sp->termios.c_ospeed = speed;
return -EIO;
}
/*
* Otherwise, update the hardware.
*/
IOWR_ALTERA_AVALON_UART_DIVISOR(sp->base,
((sp->freq/sp->termios.c_ispeed) - 1));
return 0;
}
#endif /* ALTERA_AVALON_UART_USE_IOCTL */
#endif /* fast driver */

240
Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test_bsp/drivers/src/altera_avalon_uart_read.c Normal file
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/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include <fcntl.h>
#include "sys/alt_irq.h"
#include "sys/ioctl.h"
#include "sys/alt_errno.h"
#include "altera_avalon_uart.h"
#include "altera_avalon_uart_regs.h"
#if defined(ALT_USE_SMALL_DRIVERS) || defined(ALTERA_AVALON_UART_SMALL)
/* ----------------------------------------------------------- */
/* ----------------------- SMALL DRIVER ---------------------- */
/* ----------------------------------------------------------- */
/*
* altera_avalon_uart_read() is called by the system read() function in order to
* read a block of data from the UART. "len" is the maximum length of the data
* to read, and "ptr" indicates the destination address. "fd" is the file
* descriptor for the device to be read from.
*
* Permission checks are made before the call to altera_avalon_uart_read(), so
* we know that the file descriptor has been opened with the correct permissions
* for this operation.
*
* The return value is the number of bytes actually read.
*
* This implementation polls the device waiting for characters. At most it can
* only return one character, regardless of how many are requested. If the
* device is being accessed in non-blocking mode then it is possible for this
* function to return without reading any characters. In this case errno is
* set to EWOULDBLOCK.
*/
int
altera_avalon_uart_read(altera_avalon_uart_state* sp, char* ptr, int len,
int flags)
{
int block;
unsigned int status;
block = !(flags & O_NONBLOCK);
do
{
status = IORD_ALTERA_AVALON_UART_STATUS(sp->base);
/* clear any error flags */
IOWR_ALTERA_AVALON_UART_STATUS(sp->base, 0);
if (status & ALTERA_AVALON_UART_CONTROL_RRDY_MSK)
{
ptr[0] = IORD_ALTERA_AVALON_UART_RXDATA(sp->base);
if (!(status & (ALTERA_AVALON_UART_STATUS_PE_MSK |
ALTERA_AVALON_UART_STATUS_FE_MSK)))
{
return 1;
}
}
}
while (block);
ALT_ERRNO = EWOULDBLOCK;
return 0;
}
#else
/* ----------------------------------------------------------- */
/* ----------------------- FAST DRIVER ----------------------- */
/* ----------------------------------------------------------- */
/*
* altera_avalon_uart_read() is called by the system read() function in order to
* read a block of data from the UART. "len" is the maximum length of the data
* to read, and "ptr" indicates the destination address. "sp" is the state
* pointer for the device to be read from.
*
* Permission checks are made before the call to altera_avalon_uart_read(), so
* we know that the file descriptor has been opened with the correct permissions
* for this operation.
*
* The return value is the number of bytes actually read.
*
* This function does not communicate with the device directly. Instead data is
* transfered from a circular buffer. The interrupt handler is then responsible
* for copying data from the device into this buffer.
*/
int
altera_avalon_uart_read(altera_avalon_uart_state* sp, char* ptr, int len,
int flags)
{
alt_irq_context context;
int block;
alt_u8 read_would_block = 0;
int count = 0;
/*
* Construct a flag to indicate whether the device is being accessed in
* blocking or non-blocking mode.
*/
block = !(flags & O_NONBLOCK);
/*
* When running in a multi threaded environment, obtain the "read_lock"
* semaphore. This ensures that reading from the device is thread-safe.
*/
ALT_SEM_PEND (sp->read_lock, 0);
/*
* Loop, copying data from the circular buffer to the destination address
* supplied in "ptr". This loop is terminated when the required number of
* bytes have been read. If the circular buffer is empty, and no data has
* been read, then the loop will block (when in blocking mode).
*
* If the circular buffer is empty, and some data has already been
* transferred, or the device is being accessed in non-blocking mode, then
* the loop terminates without necessarily reading all the requested data.
*/
do
{
/*
* Read the required amount of data, until the circular buffer runs
* empty
*/
while ((count < len) && (sp->rx_start != sp->rx_end))
{
count++;
*ptr++ = sp->rx_buf[sp->rx_start];
sp->rx_start = (sp->rx_start+1) & ALT_AVALON_UART_BUF_MSK;
}
/*
* If no data has been transferred, the circular buffer is empty, and
* this is not a non-blocking access, block waiting for data to arrive.
*/
if (!count && (sp->rx_start == sp->rx_end))
{
if (!block)
{
/* Set errno to indicate the reason we're not returning any data */
ALT_ERRNO = EWOULDBLOCK;
read_would_block = 1;
break;
}
else
{
/* Block waiting for some data to arrive */
/* First, ensure read interrupts are enabled to avoid deadlock */
context = alt_irq_disable_all ();
sp->ctrl |= ALTERA_AVALON_UART_CONTROL_RRDY_MSK;
IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl);
alt_irq_enable_all (context);
/*
* When running in a multi-threaded mode, we pend on the read event
* flag set in the interrupt service routine. This avoids wasting CPU
* cycles waiting in this thread, when we could be doing something more
* profitable elsewhere.
*/
ALT_FLAG_PEND (sp->events,
ALT_UART_READ_RDY,
OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME,
0);
}
}
}
while (!count && len);
/*
* Now that access to the circular buffer is complete, release the read
* semaphore so that other threads can access the buffer.
*/
ALT_SEM_POST (sp->read_lock);
/*
* Ensure that interrupts are enabled, so that the circular buffer can
* re-fill.
*/
context = alt_irq_disable_all ();
sp->ctrl |= ALTERA_AVALON_UART_CONTROL_RRDY_MSK;
IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl);
alt_irq_enable_all (context);
/* Return the number of bytes read */
if(read_would_block) {
return -EWOULDBLOCK;
}
else {
return count;
}
}
#endif /* fast driver */

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/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include <fcntl.h>
#include "sys/alt_dev.h"
#include "sys/alt_irq.h"
#include "sys/ioctl.h"
#include "sys/alt_errno.h"
#include "altera_avalon_uart_regs.h"
#include "altera_avalon_uart.h"
#if defined(ALT_USE_SMALL_DRIVERS) || defined(ALTERA_AVALON_UART_SMALL)
/* ----------------------------------------------------------- */
/* ------------------------ SMALL DRIVER --------------------- */
/* ----------------------------------------------------------- */
/*
* altera_avalon_uart_write() is called by the system write() function in
* order to write a block of data to the UART.
* "len" is the length of the data to write,
* and "ptr" indicates the source address. "fd" is the file descriptor for the
* device to be read from.
*
* Permission checks are made before the call to altera_avalon_uart_write(), so
* we know that the file descriptor has been opened with the correct permissions
* for this operation.
*
* The return value is the number of bytes actually written.
*
* This function will block on the devices transmit register, until all
* characters have been transmitted. This is unless the device is being
* accessed in non-blocking mode. In this case this function will return as
* soon as the device reports that it is not ready to transmit.
*
* Since this is the small footprint version of the UART driver, the value of
* CTS is ignored.
*/
int
altera_avalon_uart_write(altera_avalon_uart_state* sp, const char* ptr, int len,
int flags)
{
int block;
unsigned int status;
int count;
block = !(flags & O_NONBLOCK);
count = len;
do
{
status = IORD_ALTERA_AVALON_UART_STATUS(sp->base);
if (status & ALTERA_AVALON_UART_STATUS_TRDY_MSK)
{
IOWR_ALTERA_AVALON_UART_TXDATA(sp->base, *ptr++);
count--;
}
}
while (block && count);
if (count)
{
ALT_ERRNO = EWOULDBLOCK;
}
return (len - count);
}
#else /* Using the "fast" version of the driver */
/* ----------------------------------------------------------- */
/* ------------------------- FAST DRIVER --------------------- */
/* ----------------------------------------------------------- */
/*
* altera_avalon_uart_write() is called by the system write() function in order
* to write a block of data to the UART. "len" is the length of the data to
* write, and "ptr" indicates the source address. "sp" is the state pointer
* for the device to be written to.
*
* Permission checks are made before the call to altera_avalon_uart_write(), so
* we know that the file descriptor has been opened with the correct permissions
* for this operation.
*
* The return value is the number of bytes actually written.
*
* This function does not communicate with the device directly. Instead data is
* transfered to a circular buffer. The interrupt handler is then responsible
* for copying data from this buffer into the device.
*/
int
altera_avalon_uart_write(altera_avalon_uart_state* sp, const char* ptr, int len,
int flags)
{
alt_irq_context context;
int no_block;
alt_u32 next;
int count = len;
/*
* Construct a flag to indicate whether the device is being accessed in
* blocking or non-blocking mode.
*/
no_block = (flags & O_NONBLOCK);
/*
* When running in a multi threaded environment, obtain the "write_lock"
* semaphore. This ensures that writing to the device is thread-safe.
*/
ALT_SEM_PEND (sp->write_lock, 0);
/*
* Loop transferring data from the input buffer to the transmit circular
* buffer. The loop is terminated once all the data has been transferred,
* or, (if in non-blocking mode) the buffer becomes full.
*/
while (count)
{
/* Determine the next slot in the buffer to access */
next = (sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK;
/* block waiting for space if necessary */
if (next == sp->tx_start)
{
if (no_block)
{
/* Set errno to indicate why this function returned early */
ALT_ERRNO = EWOULDBLOCK;
break;
}
else
{
/* Block waiting for space in the circular buffer */
/* First, ensure transmit interrupts are enabled to avoid deadlock */
context = alt_irq_disable_all ();
sp->ctrl |= (ALTERA_AVALON_UART_CONTROL_TRDY_MSK |
ALTERA_AVALON_UART_CONTROL_DCTS_MSK);
IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl);
alt_irq_enable_all (context);
/* wait for space to come free */
do
{
/*
* When running in a multi-threaded mode, we pend on the write event
* flag set in the interrupt service routine. This avoids wasting CPU
* cycles waiting in this thread, when we could be doing something
* more profitable elsewhere.
*/
ALT_FLAG_PEND (sp->events,
ALT_UART_WRITE_RDY,
OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME,
0);
}
while ((next == sp->tx_start));
}
}
count--;
/* Add the next character to the transmit buffer */
sp->tx_buf[sp->tx_end] = *ptr++;
sp->tx_end = next;
}
/*
* Now that access to the circular buffer is complete, release the write
* semaphore so that other threads can access the buffer.
*/
ALT_SEM_POST (sp->write_lock);
/*
* Ensure that interrupts are enabled, so that the circular buffer can
* drain.
*/
context = alt_irq_disable_all ();
sp->ctrl |= ALTERA_AVALON_UART_CONTROL_TRDY_MSK |
ALTERA_AVALON_UART_CONTROL_DCTS_MSK;
IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl);
alt_irq_enable_all (context);
/* return the number of bytes written */
return (len - count);
}
#endif /* fast driver */

4
Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test_bsp/linker.h
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@ -4,7 +4,7 @@
* Machine generated for CPU 'nios2_gen2' in SOPC Builder design 'Qsys' * Machine generated for CPU 'nios2_gen2' in SOPC Builder design 'Qsys'
* SOPC Builder design path: ../../Qsys.sopcinfo * SOPC Builder design path: ../../Qsys.sopcinfo
* *
* Generated: Fri May 14 13:04:40 BST 2021 * Generated: Thu Jun 03 15:15:16 BST 2021
*/ */
/* /*
@ -66,7 +66,7 @@
*/ */
#define ONCHIP_MEMORY2_0_REGION_BASE 0x20020 #define ONCHIP_MEMORY2_0_REGION_BASE 0x20020
#define ONCHIP_MEMORY2_0_REGION_SPAN 99968 #define ONCHIP_MEMORY2_0_REGION_SPAN 131040
#define RESET_REGION_BASE 0x20000 #define RESET_REGION_BASE 0x20000
#define RESET_REGION_SPAN 32 #define RESET_REGION_SPAN 32

4
Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test_bsp/mem_init.mk
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@ -181,8 +181,8 @@ HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).dat
SYM_FILES += $(HDL_SIM_DIR)/$(MEM_0).sym SYM_FILES += $(HDL_SIM_DIR)/$(MEM_0).sym
HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).sym HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).sym
$(MEM_0)_START := 0x00020000 $(MEM_0)_START := 0x00020000
$(MEM_0)_END := 0x0003869f $(MEM_0)_END := 0x0003ffff
$(MEM_0)_SPAN := 0x000186a0 $(MEM_0)_SPAN := 0x00020000
$(MEM_0)_HIERARCHICAL_PATH := onchip_memory2_0 $(MEM_0)_HIERARCHICAL_PATH := onchip_memory2_0
$(MEM_0)_WIDTH := 32 $(MEM_0)_WIDTH := 32
$(MEM_0)_HEX_DATA_WIDTH := 32 $(MEM_0)_HEX_DATA_WIDTH := 32

4
Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test_bsp/memory.gdb
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@ -3,7 +3,7 @@
# Machine generated for CPU 'nios2_gen2' in SOPC Builder design 'Qsys' # Machine generated for CPU 'nios2_gen2' in SOPC Builder design 'Qsys'
# SOPC Builder design path: ../../Qsys.sopcinfo # SOPC Builder design path: ../../Qsys.sopcinfo
# #
# Generated: Fri May 14 13:04:40 BST 2021 # Generated: Thu Jun 03 15:15:16 BST 2021
# DO NOT MODIFY THIS FILE # DO NOT MODIFY THIS FILE
# #
@ -47,4 +47,4 @@
# by allowing GDB to cache memory contents on the host. # by allowing GDB to cache memory contents on the host.
# onchip_memory2_0 # onchip_memory2_0
memory 0x20000 0x386a0 cache memory 0x20000 0x40000 cache

15
Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test_bsp/public.mk
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@ -157,9 +157,9 @@ SOPC_SYSID_FLAG += --sidp=0x410e0
ELF_PATCH_FLAG += --sidp 0x410e0 ELF_PATCH_FLAG += --sidp 0x410e0
# The SOPC Timestamp # The SOPC Timestamp
# setting SOPC_TIMESTAMP is 1621008007 # setting SOPC_TIMESTAMP is 1622729449
SOPC_SYSID_FLAG += --timestamp=1621008007 SOPC_SYSID_FLAG += --timestamp=1622729449
ELF_PATCH_FLAG += --timestamp 1621008007 ELF_PATCH_FLAG += --timestamp 1622729449
# Enable JTAG UART driver to recover when host is inactive causing buffer to # Enable JTAG UART driver to recover when host is inactive causing buffer to
# full without returning error. Printf will not fail with this recovery. none # full without returning error. Printf will not fail with this recovery. none
@ -168,6 +168,15 @@ ELF_PATCH_FLAG += --timestamp 1621008007
# Small-footprint (polled mode) driver none # Small-footprint (polled mode) driver none
# setting altera_avalon_jtag_uart_driver.enable_small_driver is false # setting altera_avalon_jtag_uart_driver.enable_small_driver is false
# Enable driver ioctl() support. This feature is not compatible with the
# 'small' driver; ioctl() support will not be compiled if either the UART
# 'enable_small_driver' or HAL 'enable_reduced_device_drivers' settings are
# enabled. none
# setting altera_avalon_uart_driver.enable_ioctl is false
# Small-footprint (polled mode) driver none
# setting altera_avalon_uart_driver.enable_small_driver is false
# Build a custom version of newlib with the specified space-separated compiler # Build a custom version of newlib with the specified space-separated compiler
# flags. The custom newlib build will be placed in the <bsp root>/newlib # flags. The custom newlib build will be placed in the <bsp root>/newlib
# directory, and will be used only for applications that utilize this BSP. # directory, and will be used only for applications that utilize this BSP.

38
Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test_bsp/settings.bsp
View file

@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema"> <sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType> <BspType>hal</BspType>
<BspVersion>default</BspVersion> <BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>14-May-2021 21:40:25</BspGeneratedTimeStamp> <BspGeneratedTimeStamp>03-Jun-2021 15:15:44</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1621024825749</BspGeneratedUnixTimeStamp> <BspGeneratedUnixTimeStamp>1622729744108</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>F:\Ed\Stuff\EEE2Rover\DE10_LITE_D8M_VIP_16\software\D8M_Camera_Test_bsp</BspGeneratedLocation> <BspGeneratedLocation>F:\Ed\Stuff\EEE2Rover\DE10_LITE_D8M_VIP_16\software\D8M_Camera_Test_bsp</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile> <BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>..\..\Qsys.sopcinfo</SopcDesignFile> <SopcDesignFile>..\..\Qsys.sopcinfo</SopcDesignFile>
@ -898,10 +898,34 @@
<Enabled>false</Enabled> <Enabled>false</Enabled>
<Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/> <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
</Setting> </Setting>
<Setting>
<SettingName>altera_avalon_uart_driver.enable_small_driver</SettingName>
<Identifier>ALTERA_AVALON_UART_SMALL</Identifier>
<Type>BooleanDefineOnly</Type>
<Value>false</Value>
<DefaultValue>false</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Small-footprint (polled mode) driver</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
</Setting>
<Setting>
<SettingName>altera_avalon_uart_driver.enable_ioctl</SettingName>
<Identifier>ALTERA_AVALON_UART_USE_IOCTL</Identifier>
<Type>BooleanDefineOnly</Type>
<Value>false</Value>
<DefaultValue>false</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Enable driver ioctl() support. This feature is not compatible with the 'small' driver; ioctl() support will not be compiled if either the UART 'enable_small_driver' or HAL 'enable_reduced_device_drivers' settings are enabled.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
</Setting>
<MemoryMap> <MemoryMap>
<slaveDescriptor>onchip_memory2_0</slaveDescriptor> <slaveDescriptor>onchip_memory2_0</slaveDescriptor>
<addressRange>0x00020000 - 0x0003869F</addressRange> <addressRange>0x00020000 - 0x0003FFFF</addressRange>
<addressSpan>100000</addressSpan> <addressSpan>131072</addressSpan>
<attributes>memory</attributes> <attributes>memory</attributes>
</MemoryMap> </MemoryMap>
<MemoryMap> <MemoryMap>
@ -982,6 +1006,12 @@
<addressSpan>32</addressSpan> <addressSpan>32</addressSpan>
<attributes/> <attributes/>
</MemoryMap> </MemoryMap>
<MemoryMap>
<slaveDescriptor>uart_0</slaveDescriptor>
<addressRange>0x00042020 - 0x0004203F</addressRange>
<addressSpan>32</addressSpan>
<attributes>printable</attributes>
</MemoryMap>
<LinkerSection> <LinkerSection>
<sectionName>.text</sectionName> <sectionName>.text</sectionName>
<regionName>onchip_memory2_0</regionName> <regionName>onchip_memory2_0</regionName>

34
Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test_bsp/system.h
View file

@ -4,7 +4,7 @@
* Machine generated for CPU 'nios2_gen2' in SOPC Builder design 'Qsys' * Machine generated for CPU 'nios2_gen2' in SOPC Builder design 'Qsys'
* SOPC Builder design path: ../../Qsys.sopcinfo * SOPC Builder design path: ../../Qsys.sopcinfo
* *
* Generated: Fri May 14 17:18:20 BST 2021 * Generated: Thu Jun 03 15:15:16 BST 2021
*/ */
/* /*
@ -146,6 +146,7 @@
#define __ALTERA_AVALON_PIO #define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_SYSID_QSYS #define __ALTERA_AVALON_SYSID_QSYS
#define __ALTERA_AVALON_TIMER #define __ALTERA_AVALON_TIMER
#define __ALTERA_AVALON_UART
#define __ALTERA_NIOS2_GEN2 #define __ALTERA_NIOS2_GEN2
#define __ALTPLL #define __ALTPLL
#define __EEE_IMGPROC #define __EEE_IMGPROC
@ -419,8 +420,8 @@
#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE "DONT_CARE" #define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE "DONT_CARE"
#define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0 #define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0
#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1 #define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1
#define ONCHIP_MEMORY2_0_SIZE_VALUE 100000 #define ONCHIP_MEMORY2_0_SIZE_VALUE 131072
#define ONCHIP_MEMORY2_0_SPAN 100000 #define ONCHIP_MEMORY2_0_SPAN 131072
#define ONCHIP_MEMORY2_0_TYPE "altera_avalon_onchip_memory2" #define ONCHIP_MEMORY2_0_TYPE "altera_avalon_onchip_memory2"
#define ONCHIP_MEMORY2_0_WRITABLE 1 #define ONCHIP_MEMORY2_0_WRITABLE 1
@ -464,7 +465,7 @@
#define SYSID_QSYS_IRQ_INTERRUPT_CONTROLLER_ID -1 #define SYSID_QSYS_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SYSID_QSYS_NAME "/dev/sysid_qsys" #define SYSID_QSYS_NAME "/dev/sysid_qsys"
#define SYSID_QSYS_SPAN 8 #define SYSID_QSYS_SPAN 8
#define SYSID_QSYS_TIMESTAMP 1621008007 #define SYSID_QSYS_TIMESTAMP 1622729449
#define SYSID_QSYS_TYPE "altera_avalon_sysid_qsys" #define SYSID_QSYS_TYPE "altera_avalon_sysid_qsys"
@ -493,4 +494,29 @@
#define TIMER_TIMEOUT_PULSE_OUTPUT 0 #define TIMER_TIMEOUT_PULSE_OUTPUT 0
#define TIMER_TYPE "altera_avalon_timer" #define TIMER_TYPE "altera_avalon_timer"
/*
* uart_0 configuration
*
*/
#define ALT_MODULE_CLASS_uart_0 altera_avalon_uart
#define UART_0_BASE 0x42020
#define UART_0_BAUD 115200
#define UART_0_DATA_BITS 8
#define UART_0_FIXED_BAUD 1
#define UART_0_FREQ 50000000
#define UART_0_IRQ 4
#define UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define UART_0_NAME "/dev/uart_0"
#define UART_0_PARITY 'N'
#define UART_0_SIM_CHAR_STREAM ""
#define UART_0_SIM_TRUE_BAUD 0
#define UART_0_SPAN 32
#define UART_0_STOP_BITS 1
#define UART_0_SYNC_REG_DEPTH 2
#define UART_0_TYPE "altera_avalon_uart"
#define UART_0_USE_CTS_RTS 0
#define UART_0_USE_EOP_REGISTER 0
#endif /* __SYSTEM_H_ */ #endif /* __SYSTEM_H_ */

115
Vision/DE10_LITE_D8M_VIP_16/uart_interface_hw.tcl
View file

@ -1,115 +0,0 @@
# TCL File Generated by Component Editor 16.1
# Thu May 27 17:12:45 BST 2021
# DO NOT MODIFY
#
# uart_interface "uart_interface" v1.0
# 2021.05.27.17:12:45
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module uart_interface
#
set_module_property DESCRIPTION ""
set_module_property NAME uart_interface
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME uart_interface
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL uart
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file uart.v VERILOG PATH ip/de10lite-hdl/uart.v TOP_LEVEL_FILE
#
# parameters
#
add_parameter CLK_FREQ INTEGER 50000000
set_parameter_property CLK_FREQ DEFAULT_VALUE 50000000
set_parameter_property CLK_FREQ DISPLAY_NAME CLK_FREQ
set_parameter_property CLK_FREQ TYPE INTEGER
set_parameter_property CLK_FREQ UNITS None
set_parameter_property CLK_FREQ HDL_PARAMETER true
add_parameter BAUD INTEGER 115200
set_parameter_property BAUD DEFAULT_VALUE 115200
set_parameter_property BAUD DISPLAY_NAME BAUD
set_parameter_property BAUD TYPE INTEGER
set_parameter_property BAUD UNITS None
set_parameter_property BAUD HDL_PARAMETER true
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset reset reset Input 1
#
# connection point conduit_end
#
add_interface conduit_end conduit end
set_interface_property conduit_end associatedClock clock
set_interface_property conduit_end associatedReset ""
set_interface_property conduit_end ENABLED true
set_interface_property conduit_end EXPORT_OF ""
set_interface_property conduit_end PORT_NAME_MAP ""
set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
set_interface_property conduit_end SVD_ADDRESS_GROUP ""
add_interface_port conduit_end rx rx Input 1
add_interface_port conduit_end rx_data rx_data Output 8
add_interface_port conduit_end rx_valid rx_valid Output 1
add_interface_port conduit_end tx tx Output 1
add_interface_port conduit_end tx_data tx_data Input 8
add_interface_port conduit_end tx_transmit tx_transmit Input 1
add_interface_port conduit_end tx_ready tx_ready Output 1

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Vision/doc/OV8865 Data Sheet.pdf Normal file
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