ELEC40006-P1-CW/LUT.qip
Aadi Desai d046242bc1 Final State before Pipelining
Debug Complete, data and instruction mifs + ram files. Test program checked
2020-06-09 22:45:20 +01:00

7 lines
423 B
Plaintext

set_global_assignment -name IP_TOOL_NAME "ROM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "19.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "LUT.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "LUT.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "LUT_bb.v"]