supleed2/ELEC40006-P1-CW
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4 commits

Author SHA1 Message Date
Kacper 685f69a7cf Almost ready CPU 
Changed the MUX blocks into Verilog just cuz they look neater and are probably more optimised in the end. Added the LIFO stack. Working on decoder logic.
 2020-06-07 15:08:34 +01:00
Kacper 1c0032fa95 Fixed decoder and SM 2020-06-02 20:09:22 +01:00
Kacper e1acb56b66 Finished decoder 2020-05-27 18:53:03 +01:00
Kacper 5ed70dabb0 Working on datapath 2020-05-27 11:10:13 +01:00