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Merge branch 'master' of https://github.com/supleed2/CPUProject

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This commit is contained in:
Aadi Desai 2020-06-02 16:58:04 +01:00
parent 2ca1e90a2c 5d6c9803fc
commit e1d7bf884d
11 changed files with 918 additions and 305 deletions
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3
CPUProject.qsf
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@ -57,8 +57,9 @@ set_global_assignment -name BDF_FILE SM.bdf
set_global_assignment -name VERILOG_FILE DECODE.v set_global_assignment -name VERILOG_FILE DECODE.v
set_global_assignment -name MIF_FILE data.mif set_global_assignment -name MIF_FILE data.mif
set_global_assignment -name MIF_FILE instr.mif set_global_assignment -name MIF_FILE instr.mif
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name BDF_FILE mul16.bdf set_global_assignment -name BDF_FILE mul16.bdf
set_global_assignment -name QIP_FILE LUT.qip
set_global_assignment -name VERILOG_FILE min.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

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CPUProject.qws
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LUT.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 0 0 256 120)
(text "LUT" (rect 102 0 129 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 104 25 116)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
(text "address_a[7..0]" (rect 4 8 149 31)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 112 32)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
(text "address_b[7..0]" (rect 4 40 148 63)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 112 64)(line_width 3))
)
(port
(pt 0 96)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 4 72 51 95)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 176 96))
)
(port
(pt 256 32)
(output)
(text "q_a[15..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
(text "q_a[15..0]" (rect 158 8 251 31)(font "Arial" (font_size 8)))
(line (pt 256 32)(pt 192 32)(line_width 3))
)
(port
(pt 256 64)
(output)
(text "q_b[15..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
(text "q_b[15..0]" (rect 159 40 251 63)(font "Arial" (font_size 8)))
(line (pt 256 64)(pt 192 64)(line_width 3))
)
(drawing
(text "256 Word(s)" (rect 127 -1 253 231)(font "Arial" )(vertical))
(text "RAM" (rect 148 -22 243 169)(font "Arial" )(vertical))
(text "Block Type: AUTO" (rect 40 99 239 219)(font "Arial" ))
(line (pt 128 24)(pt 168 24))
(line (pt 168 24)(pt 168 80))
(line (pt 168 80)(pt 128 80))
(line (pt 128 80)(pt 128 24))
(line (pt 112 27)(pt 120 27))
(line (pt 120 27)(pt 120 39))
(line (pt 120 39)(pt 112 39))
(line (pt 112 39)(pt 112 27))
(line (pt 112 34)(pt 114 36))
(line (pt 114 36)(pt 112 38))
(line (pt 104 36)(pt 112 36))
(line (pt 120 32)(pt 128 32)(line_width 3))
(line (pt 112 59)(pt 120 59))
(line (pt 120 59)(pt 120 71))
(line (pt 120 71)(pt 112 71))
(line (pt 112 71)(pt 112 59))
(line (pt 112 66)(pt 114 68))
(line (pt 114 68)(pt 112 70))
(line (pt 104 68)(pt 112 68))
(line (pt 120 64)(pt 128 64)(line_width 3))
(line (pt 104 36)(pt 104 97))
(line (pt 176 36)(pt 176 97))
(line (pt 184 27)(pt 192 27))
(line (pt 192 27)(pt 192 39))
(line (pt 192 39)(pt 184 39))
(line (pt 184 39)(pt 184 27))
(line (pt 184 34)(pt 186 36))
(line (pt 186 36)(pt 184 38))
(line (pt 176 36)(pt 184 36))
(line (pt 168 32)(pt 184 32)(line_width 3))
(line (pt 184 59)(pt 192 59))
(line (pt 192 59)(pt 192 71))
(line (pt 192 71)(pt 184 71))
(line (pt 184 71)(pt 184 59))
(line (pt 184 66)(pt 186 68))
(line (pt 186 68)(pt 184 70))
(line (pt 176 68)(pt 184 68))
(line (pt 168 64)(pt 184 64)(line_width 3))
(line (pt 0 0)(pt 257 0))
(line (pt 257 0)(pt 257 122))
(line (pt 0 122)(pt 257 122))
(line (pt 0 0)(pt 0 122))
(line (pt 0 0)(pt 0 0))
(line (pt 0 0)(pt 0 0))
(line (pt 0 0)(pt 0 0))
(line (pt 0 0)(pt 0 0))
)
)

5
LUT.qip Normal file
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@ -0,0 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ROM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "19.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "LUT.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "LUT.bsf"]

229
LUT.v Normal file
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// megafunction wizard: %ROM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: LUT.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
// ************************************************************
//Copyright (C) 2019 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module LUT (
address_a,
address_b,
clock,
q_a,
q_b);
input [7:0] address_a;
input [7:0] address_b;
input clock;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0 = 16'h0;
wire sub_wire1 = 1'h0;
wire [15:0] sub_wire2;
wire [15:0] sub_wire3;
wire [15:0] q_a = sub_wire2[15:0];
wire [15:0] q_b = sub_wire3[15:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (sub_wire0),
.data_b (sub_wire0),
.wren_a (sub_wire1),
.wren_b (sub_wire1),
.q_a (sub_wire2),
.q_b (sub_wire3)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.clocken2 (),
.clocken3 (),
.eccstatus (),
.rden_a (),
.rden_b ()
// synopsys translate_on
);
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "LUTSquares.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "LUTSquares.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INIT_FILE STRING "LUTSquares.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL "address_a[7..0]"
// Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL "address_b[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 GND 0 0 16 0
// Retrieval info: CONNECT: @data_b 0 0 16 0 GND 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL LUT.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LUT.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL LUT.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL LUT.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LUT_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL LUT_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

58
min.bsf Normal file
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@ -0,0 +1,58 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 176 128)
(text "min" (rect 5 0 19 12)(font "Arial" ))
(text "inst" (rect 8 96 20 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "sign" (rect 0 0 15 12)(font "Arial" ))
(text "sign" (rect 21 27 36 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "a[7..0]" (rect 0 0 24 12)(font "Arial" ))
(text "a[7..0]" (rect 21 43 45 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "b[7..0]" (rect 0 0 24 12)(font "Arial" ))
(text "b[7..0]" (rect 21 59 45 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 160 32)
(output)
(text "num[7..0]" (rect 0 0 37 12)(font "Arial" ))
(text "num[7..0]" (rect 102 27 139 39)(font "Arial" ))
(line (pt 160 32)(pt 144 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 144 96)(line_width 1))
)
)

7
min.v Normal file
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@ -0,0 +1,7 @@
module min(sign, a, b, num);
input sign;
input [7:0] a;
input [7:0] b;
output [7:0] num;
assign num = sign ? a[7:0]:b[7:0];
endmodule

12
min.v.bak Normal file
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@ -0,0 +1,12 @@
module MIN(
input sign,
input a[7..0],
input b[7..0],
output [7..0] num;
);
assign num = sign ? a[7..0]:b[7..0]
endmodule

442
mul16.bdf
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@ -24,7 +24,7 @@ https://fpgasoftware.intel.com/eula.
(input) (input)
(rect 48 256 216 272) (rect 48 256 216 272)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "A[15..0]" (rect 5 0 44 12)(font "Arial" )) (text "A[15..0]" (rect 5 0 43 12)(font "Arial" ))
(pt 168 8) (pt 168 8)
(drawing (drawing
(line (pt 84 12)(pt 109 12)) (line (pt 84 12)(pt 109 12))
@ -40,7 +40,7 @@ https://fpgasoftware.intel.com/eula.
(input) (input)
(rect 40 304 208 320) (rect 40 304 208 320)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "B[15..0]" (rect 5 0 44 12)(font "Arial" )) (text "B[15..0]" (rect 5 0 43 12)(font "Arial" ))
(pt 168 8) (pt 168 8)
(drawing (drawing
(line (pt 84 12)(pt 109 12)) (line (pt 84 12)(pt 109 12))
@ -52,124 +52,40 @@ https://fpgasoftware.intel.com/eula.
) )
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
) )
(symbol (pin
(rect 648 72 816 168)
(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
(text "M1" (rect 8 75 23 92)(font "Intel Clear" ))
(port
(pt 0 32)
(input) (input)
(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8))) (rect 40 208 208 224)
(text "A[7..0]" (rect 21 27 59 46)(font "Intel Clear" (font_size 8))) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(line (pt 0 32)(pt 16 32)(line_width 3)) (text "CLOCK" (rect 5 0 42 12)(font "Arial" ))
) (pt 168 8)
(port
(pt 0 48)
(input)
(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "B[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 168 32)
(output)
(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
(text "PROD[15..0]" (rect 73 27 147 46)(font "Intel Clear" (font_size 8)))
(line (pt 168 32)(pt 152 32)(line_width 3))
)
(drawing (drawing
(rectangle (rect 16 16 152 80)) (line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 1872 272 2054 288)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "PRODUCT[31..0]" (rect 90 0 176 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
) )
) )
(symbol (symbol
(rect 648 192 816 288) (rect 1296 544 1456 712)
(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
(text "M2" (rect 8 75 23 92)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "A[7..0]" (rect 21 27 59 46)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "B[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 168 32)
(output)
(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
(text "PROD[15..0]" (rect 73 27 147 46)(font "Intel Clear" (font_size 8)))
(line (pt 168 32)(pt 152 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 152 80))
)
)
(symbol
(rect 648 304 816 400)
(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
(text "M3" (rect 8 75 23 92)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "A[7..0]" (rect 21 27 59 46)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "B[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 168 32)
(output)
(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
(text "PROD[15..0]" (rect 73 27 147 46)(font "Intel Clear" (font_size 8)))
(line (pt 168 32)(pt 152 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 152 80))
)
)
(symbol
(rect 648 408 816 504)
(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
(text "M4" (rect 8 75 23 92)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "A[7..0]" (rect 21 27 59 46)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "B[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 168 32)
(output)
(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
(text "PROD[15..0]" (rect 73 27 147 46)(font "Intel Clear" (font_size 8)))
(line (pt 168 32)(pt 152 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 152 80))
)
)
(symbol
(rect 1032 360 1192 528)
(text "LPM_ADD_SUB" (rect 37 0 149 16)(font "Arial" (font_size 10))) (text "LPM_ADD_SUB" (rect 37 0 149 16)(font "Arial" (font_size 10)))
(text "ADD2" (rect 3 156 32 168)(font "Arial" )) (text "ADD2" (rect 3 156 32 168)(font "Arial" ))
(port (port
@ -307,10 +223,10 @@ https://fpgasoftware.intel.com/eula.
(line (pt 56 56)(pt 104 80)) (line (pt 56 56)(pt 104 80))
(line (pt 56 136)(pt 104 112)) (line (pt 56 136)(pt 104 112))
) )
(annotation_block (parameter)(rect 1192 224 1502 357)) (annotation_block (parameter)(rect 1208 416 1518 549))
) )
(symbol (symbol
(rect 1008 16 1168 184) (rect 1264 48 1424 216)
(text "LPM_ADD_SUB" (rect 37 0 149 16)(font "Arial" (font_size 10))) (text "LPM_ADD_SUB" (rect 37 0 149 16)(font "Arial" (font_size 10)))
(text "ADD3" (rect 3 156 30 173)(font "Intel Clear" )) (text "ADD3" (rect 3 156 30 173)(font "Intel Clear" ))
(port (port
@ -448,7 +364,7 @@ https://fpgasoftware.intel.com/eula.
(line (pt 56 56)(pt 104 80)) (line (pt 56 56)(pt 104 80))
(line (pt 56 136)(pt 104 112)) (line (pt 56 136)(pt 104 112))
) )
(annotation_block (parameter)(rect 1168 -120 1478 13)) (annotation_block (parameter)(rect 1208 -104 1518 29))
) )
(symbol (symbol
(rect 1568 184 1728 352) (rect 1568 184 1728 352)
@ -591,6 +507,167 @@ https://fpgasoftware.intel.com/eula.
) )
(annotation_block (parameter)(rect 1728 48 2038 181)) (annotation_block (parameter)(rect 1728 48 2038 181))
) )
(symbol
(rect 648 56 816 152)
(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
(text "MUL1" (rect 8 75 36 92)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
(text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "A[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "B[7..0]" (rect 21 59 59 78)(font "Intel Clear" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 168 32)
(output)
(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
(text "PROD[15..0]" (rect 73 27 147 46)(font "Intel Clear" (font_size 8)))
(line (pt 168 32)(pt 152 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 152 80))
)
)
(symbol
(rect 648 176 816 272)
(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
(text "MUL2" (rect 8 75 36 92)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
(text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "A[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "B[7..0]" (rect 21 59 59 78)(font "Intel Clear" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 168 32)
(output)
(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
(text "PROD[15..0]" (rect 73 27 147 46)(font "Intel Clear" (font_size 8)))
(line (pt 168 32)(pt 152 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 152 80))
)
)
(symbol
(rect 648 288 816 384)
(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
(text "MUL3" (rect 8 75 36 92)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
(text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "A[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "B[7..0]" (rect 21 59 59 78)(font "Intel Clear" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 168 32)
(output)
(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
(text "PROD[15..0]" (rect 73 27 147 46)(font "Intel Clear" (font_size 8)))
(line (pt 168 32)(pt 152 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 152 80))
)
)
(symbol
(rect 648 392 816 488)
(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
(text "MUL4" (rect 8 75 36 92)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
(text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "A[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "B[7..0]" (rect 21 59 59 78)(font "Intel Clear" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 168 32)
(output)
(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
(text "PROD[15..0]" (rect 73 27 147 46)(font "Intel Clear" (font_size 8)))
(line (pt 168 32)(pt 152 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 152 80))
)
)
(symbol
(rect 168 160 200 192)
(text "GND" (rect 8 16 29 26)(font "Arial" (font_size 6)))
(text "inst5" (rect 3 21 25 38)(font "Intel Clear" )(invisible))
(port
(pt 16 0)
(output)
(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
(line (pt 16 8)(pt 16 0))
)
(drawing
(line (pt 8 8)(pt 16 16))
(line (pt 16 16)(pt 24 8))
(line (pt 8 8)(pt 24 8))
)
)
(connector (connector
(pt 208 312) (pt 208 312)
(pt 376 312) (pt 376 312)
@ -650,32 +727,135 @@ https://fpgasoftware.intel.com/eula.
(bus) (bus)
) )
(connector (connector
(text "P1[15..0]" (rect 826 88 868 105)(font "Intel Clear" )) (text "P1[15..0]" (rect 826 72 868 89)(font "Intel Clear" ))
(pt 816 104) (pt 816 88)
(pt 880 104) (pt 880 88)
(bus) (bus)
) )
(connector (connector
(text "P2[15..0]" (rect 826 208 868 225)(font "Intel Clear" )) (text "P2[15..0]" (rect 826 192 868 209)(font "Intel Clear" ))
(pt 816 224) (pt 816 208)
(pt 880 224) (pt 880 208)
(bus) (bus)
) )
(connector (connector
(text "P3[15..0]" (rect 826 320 868 337)(font "Intel Clear" )) (text "P3[15..0]" (rect 834 296 876 313)(font "Intel Clear" ))
(pt 816 336) (pt 816 320)
(pt 888 336) (pt 888 320)
(bus) (bus)
) )
(connector (connector
(text "P4[15..0]" (rect 826 424 868 441)(font "Intel Clear" )) (text "P4[15..0]" (rect 826 408 868 425)(font "Intel Clear" ))
(pt 816 440) (pt 816 424)
(pt 888 440) (pt 888 424)
(bus) (bus)
) )
(connector (connector
(text "P[31..0]" (rect 1738 264 1774 281)(font "Intel Clear" )) (pt 200 216)
(pt 208 216)
)
(connector
(pt 208 216)
(pt 520 216)
)
(connector
(pt 520 88)
(pt 648 88)
)
(connector
(pt 520 208)
(pt 648 208)
)
(connector
(pt 520 208)
(pt 520 88)
)
(connector
(pt 520 424)
(pt 648 424)
)
(connector
(pt 520 208)
(pt 520 216)
)
(connector
(pt 520 320)
(pt 648 320)
)
(connector
(pt 520 216)
(pt 520 320)
)
(connector
(pt 520 320)
(pt 520 424)
)
(connector
(pt 1544 304)
(pt 1568 304)
(bus)
)
(connector
(pt 1544 304)
(pt 1544 640)
(bus)
)
(connector
(pt 1544 640)
(pt 1456 640)
(bus)
)
(connector
(pt 1424 144)
(pt 1480 144)
(bus)
)
(connector
(pt 1480 144)
(pt 1480 256)
(bus)
)
(connector
(pt 1568 256)
(pt 1480 256)
(bus)
)
(connector
(text "0" (rect 168 153 185 158)(font "Intel Clear" )(vertical))
(pt 184 136)
(pt 184 160)
)
(connector
(text "P1[15..0],0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" (rect 962 104 1136 121)(font "Intel Clear" ))
(pt 1264 120)
(pt 952 120)
(bus)
)
(connector
(text "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,P4[15..0]" (rect 978 152 1152 169)(font "Intel Clear" ))
(pt 1264 168)
(pt 968 168)
(bus)
)
(connector
(text "0,0,0,0,0,0,0,0,P2[15..0],0,0,0,0,0,0,0,0" (rect 986 600 1160 617)(font "Intel Clear" ))
(pt 1296 616)
(pt 976 616)
(bus)
)
(connector
(text "0,0,0,0,0,0,0,0,P3[15..0],0,0,0,0,0,0,0,0" (rect 994 648 1168 665)(font "Intel Clear" ))
(pt 1296 664)
(pt 984 664)
(bus)
)
(connector
(text "PR[31..0]" (rect 1738 264 1781 281)(font "Intel Clear" ))
(pt 1728 280) (pt 1728 280)
(pt 1872 280) (pt 1872 280)
(bus) (bus)
) )
(junction (pt 208 216))
(junction (pt 520 208))
(junction (pt 520 216))
(junction (pt 520 320))

335
mul8.bdf
View file

@ -52,6 +52,22 @@ https://fpgasoftware.intel.com/eula.
) )
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
) )
(pin
(input)
(rect 320 40 488 56)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "CLOCK" (rect 5 0 43 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(pin (pin
(output) (output)
(rect 1584 160 1760 176) (rect 1584 160 1760 176)
@ -627,7 +643,7 @@ https://fpgasoftware.intel.com/eula.
(annotation_block (parameter)(rect 1128 -8 1322 30)) (annotation_block (parameter)(rect 1128 -8 1322 30))
) )
(symbol (symbol
(rect 192 376 344 472) (rect 312 216 464 312)
(text "abs" (rect 5 0 26 19)(font "Intel Clear" (font_size 8))) (text "abs" (rect 5 0 26 19)(font "Intel Clear" (font_size 8)))
(text "inst1" (rect 8 75 30 92)(font "Intel Clear" )) (text "inst1" (rect 8 75 30 92)(font "Intel Clear" ))
(port (port
@ -649,172 +665,131 @@ https://fpgasoftware.intel.com/eula.
) )
) )
(symbol (symbol
(rect 736 -160 848 -64) (rect 688 -48 944 72)
(text "LPM_ROM" (rect 25 0 100 16)(font "Arial" (font_size 10))) (text "LUT" (rect 102 0 129 16)(font "Arial" (font_size 10)))
(text "LUTSum" (rect 3 85 43 102)(font "Intel Clear" )) (text "LookupTable" (rect 8 104 70 121)(font "Intel Clear" ))
(port (port
(pt 0 24) (pt 0 32)
(input) (input)
(text "address[LPM_WIDTHAD-1..0]" (rect 20 17 186 31)(font "Arial" (font_size 8))) (text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
(text "address[]" (rect 20 17 74 31)(font "Arial" (font_size 8))) (text "address_a[7..0]" (rect 4 8 93 22)(font "Arial" (font_size 8)))
(line (pt 0 24)(pt 16 24)(line_width 3)) (line (pt 0 32)(pt 112 32)(line_width 3))
) )
(port (port
(pt 0 40) (pt 0 64)
(input) (input)
(text "inclock" (rect 20 33 58 47)(font "Arial" (font_size 8))) (text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
(text "inclock" (rect 20 33 58 47)(font "Arial" (font_size 8))) (text "address_b[7..0]" (rect 4 40 93 54)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 16 40)) (line (pt 0 64)(pt 112 64)(line_width 3))
(unused)
) )
(port (port
(pt 0 72) (pt 0 96)
(input) (input)
(text "memenab" (rect 20 65 74 79)(font "Arial" (font_size 8))) (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "memenab" (rect 20 65 74 79)(font "Arial" (font_size 8))) (text "clock" (rect 4 72 33 86)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 16 72)) (line (pt 0 96)(pt 176 96))
(unused)
) )
(port (port
(pt 0 56) (pt 256 32)
(input)
(text "outclock" (rect 20 49 67 63)(font "Arial" (font_size 8)))
(text "outclock" (rect 20 49 67 63)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 16 56))
(unused)
)
(port
(pt 112 48)
(output) (output)
(text "q[LPM_WIDTH-1..0]" (rect 80 41 188 55)(font "Arial" (font_size 8))) (text "q_a[15..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
(text "q[]" (rect 80 41 94 55)(font "Arial" (font_size 8))) (text "q_a[15..0]" (rect 158 8 214 22)(font "Arial" (font_size 8)))
(line (pt 96 48)(pt 112 48)(line_width 3)) (line (pt 256 32)(pt 192 32)(line_width 3))
) )
(parameter (port
"LPM_ADDRESS_CONTROL" (pt 256 64)
"\"UNREGISTERED\"" (output)
"Should the address and control ports be registered?" (text "q_b[15..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
"\"REGISTERED\"" "\"UNREGISTERED\"" (text "q_b[15..0]" (rect 159 40 215 54)(font "Arial" (font_size 8)))
(line (pt 256 64)(pt 192 64)(line_width 3))
) )
(parameter
"LPM_FILE"
"\"LUTSquares.mif\""
"File containing initial contents of memory array"
(type "PARAMETER_UNKNOWN") )
(parameter
"LPM_NUMWORDS"
"256"
"Number of memory words, default is 2^LPM_WIDTHAD"
(type "PARAMETER_UNSIGNED_DEC") )
(parameter
"LPM_OUTDATA"
"\"UNREGISTERED\""
"Should the output data be registered?"
"\"REGISTERED\"" "\"UNREGISTERED\""
)
(parameter
"LPM_WIDTH"
"16"
"Data width in bits, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
(type "PARAMETER_UNSIGNED_DEC") )
(parameter
"LPM_WIDTHAD"
"8"
"Number of address lines, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12"
(type "PARAMETER_UNSIGNED_DEC") )
(drawing (drawing
(line (pt 16 16)(pt 96 16)) (text "256 Word(s)" (rect 127 -1 139 59)(font "Arial" )(vertical))
(line (pt 16 80)(pt 96 80)) (text "RAM" (rect 148 -22 160 1)(font "Arial" )(vertical))
(line (pt 96 80)(pt 96 16)) (text "Block Type: AUTO" (rect 40 99 132 111)(font "Arial" ))
(line (pt 16 80)(pt 16 16)) (line (pt 128 24)(pt 168 24))
(line (pt 168 24)(pt 168 80))
(line (pt 168 80)(pt 128 80))
(line (pt 128 80)(pt 128 24))
(line (pt 112 27)(pt 120 27))
(line (pt 120 27)(pt 120 39))
(line (pt 120 39)(pt 112 39))
(line (pt 112 39)(pt 112 27))
(line (pt 112 34)(pt 114 36))
(line (pt 114 36)(pt 112 38))
(line (pt 104 36)(pt 112 36))
(line (pt 120 32)(pt 128 32)(line_width 3))
(line (pt 112 59)(pt 120 59))
(line (pt 120 59)(pt 120 71))
(line (pt 120 71)(pt 112 71))
(line (pt 112 71)(pt 112 59))
(line (pt 112 66)(pt 114 68))
(line (pt 114 68)(pt 112 70))
(line (pt 104 68)(pt 112 68))
(line (pt 120 64)(pt 128 64)(line_width 3))
(line (pt 104 36)(pt 104 97))
(line (pt 176 36)(pt 176 97))
(line (pt 184 27)(pt 192 27))
(line (pt 192 27)(pt 192 39))
(line (pt 192 39)(pt 184 39))
(line (pt 184 39)(pt 184 27))
(line (pt 184 34)(pt 186 36))
(line (pt 186 36)(pt 184 38))
(line (pt 176 36)(pt 184 36))
(line (pt 168 32)(pt 184 32)(line_width 3))
(line (pt 184 59)(pt 192 59))
(line (pt 192 59)(pt 192 71))
(line (pt 192 71)(pt 184 71))
(line (pt 184 71)(pt 184 59))
(line (pt 184 66)(pt 186 68))
(line (pt 186 68)(pt 184 70))
(line (pt 176 68)(pt 184 68))
(line (pt 168 64)(pt 184 64)(line_width 3))
(line (pt 0 0)(pt 257 0))
(line (pt 257 0)(pt 257 122))
(line (pt 0 122)(pt 257 122))
(line (pt 0 0)(pt 0 122))
(line (pt 0 0)(pt 0 0))
(line (pt 0 0)(pt 0 0))
(line (pt 0 0)(pt 0 0))
(line (pt 0 0)(pt 0 0))
) )
(annotation_block (parameter)(rect 848 -296 1178 -163))
) )
(symbol (symbol
(rect 760 16 872 112) (rect 360 440 520 552)
(text "LPM_ROM" (rect 25 0 100 16)(font "Arial" (font_size 10))) (text "min" (rect 5 0 22 12)(font "Arial" ))
(text "LUTDifference" (rect 3 85 70 102)(font "Intel Clear" )) (text "inst4" (rect 8 96 30 113)(font "Intel Clear" ))
(port (port
(pt 0 24) (pt 0 32)
(input) (input)
(text "address[LPM_WIDTHAD-1..0]" (rect 20 17 186 31)(font "Arial" (font_size 8))) (text "sign" (rect 0 0 20 12)(font "Arial" ))
(text "address[]" (rect 20 17 74 31)(font "Arial" (font_size 8))) (text "sign" (rect 21 27 41 39)(font "Arial" ))
(line (pt 0 24)(pt 16 24)(line_width 3)) (line (pt 0 32)(pt 16 32))
) )
(port (port
(pt 0 40) (pt 0 48)
(input) (input)
(text "inclock" (rect 20 33 58 47)(font "Arial" (font_size 8))) (text "a[7..0]" (rect 0 0 31 12)(font "Arial" ))
(text "inclock" (rect 20 33 58 47)(font "Arial" (font_size 8))) (text "a[7..0]" (rect 21 43 52 55)(font "Arial" ))
(line (pt 0 40)(pt 16 40)) (line (pt 0 48)(pt 16 48)(line_width 3))
(unused)
) )
(port (port
(pt 0 72) (pt 0 64)
(input) (input)
(text "memenab" (rect 20 65 74 79)(font "Arial" (font_size 8))) (text "b[7..0]" (rect 0 0 31 12)(font "Arial" ))
(text "memenab" (rect 20 65 74 79)(font "Arial" (font_size 8))) (text "b[7..0]" (rect 21 59 52 71)(font "Arial" ))
(line (pt 0 72)(pt 16 72)) (line (pt 0 64)(pt 16 64)(line_width 3))
(unused)
) )
(port (port
(pt 0 56) (pt 160 32)
(input)
(text "outclock" (rect 20 49 67 63)(font "Arial" (font_size 8)))
(text "outclock" (rect 20 49 67 63)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 16 56))
(unused)
)
(port
(pt 112 48)
(output) (output)
(text "q[LPM_WIDTH-1..0]" (rect 80 41 188 55)(font "Arial" (font_size 8))) (text "num[7..0]" (rect 0 0 47 12)(font "Arial" ))
(text "q[]" (rect 80 41 94 55)(font "Arial" (font_size 8))) (text "num[7..0]" (rect 100 27 147 39)(font "Arial" ))
(line (pt 96 48)(pt 112 48)(line_width 3)) (line (pt 160 32)(pt 144 32)(line_width 3))
) )
(parameter
"LPM_ADDRESS_CONTROL"
"\"UNREGISTERED\""
"Should the address and control ports be registered?"
"\"REGISTERED\"" "\"UNREGISTERED\""
)
(parameter
"LPM_FILE"
"\"LUTSquares.mif\""
"File containing initial contents of memory array"
(type "PARAMETER_UNKNOWN") )
(parameter
"LPM_NUMWORDS"
"256"
"Number of memory words, default is 2^LPM_WIDTHAD"
(type "PARAMETER_UNSIGNED_DEC") )
(parameter
"LPM_OUTDATA"
"\"UNREGISTERED\""
"Should the output data be registered?"
"\"REGISTERED\"" "\"UNREGISTERED\""
)
(parameter
"LPM_WIDTH"
"16"
"Data width in bits, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
(type "PARAMETER_UNSIGNED_DEC") )
(parameter
"LPM_WIDTHAD"
"8"
"Number of address lines, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12"
(type "PARAMETER_UNSIGNED_DEC") )
(drawing (drawing
(line (pt 16 16)(pt 96 16)) (rectangle (rect 16 16 144 96))
(line (pt 16 80)(pt 96 80))
(line (pt 96 80)(pt 96 16))
(line (pt 16 80)(pt 16 16))
) )
(annotation_block (parameter)(rect 872 -120 1202 13))
) )
(connector (connector
(text "1" (rect -94 -64 -89 -47)(font "Intel Clear" )) (text "1" (rect -94 -64 -89 -47)(font "Intel Clear" ))
@ -942,12 +917,6 @@ https://fpgasoftware.intel.com/eula.
(pt 1224 248) (pt 1224 248)
(bus) (bus)
) )
(connector
(text "0,0,0,0,0,0,0,0,EXTRA[7..0]" (rect 1144 232 1266 249)(font "Intel Clear" ))
(pt 1224 248)
(pt 1144 248)
(bus)
)
(connector (connector
(text "A[0]" (rect 698 536 718 553)(font "Intel Clear" )) (text "A[0]" (rect 698 536 718 553)(font "Intel Clear" ))
(pt 720 552) (pt 720 552)
@ -972,12 +941,6 @@ https://fpgasoftware.intel.com/eula.
(pt 968 456) (pt 968 456)
(bus) (bus)
) )
(connector
(text "B[7..0]" (rect 738 456 768 473)(font "Intel Clear" ))
(pt 728 472)
(pt 800 472)
(bus)
)
(connector (connector
(text "0,0,0,0,0,0,0,0" (rect 730 424 793 441)(font "Intel Clear" )) (text "0,0,0,0,0,0,0,0" (rect 730 424 793 441)(font "Intel Clear" ))
(pt 800 440) (pt 800 440)
@ -985,47 +948,85 @@ https://fpgasoftware.intel.com/eula.
(bus) (bus)
) )
(connector (connector
(text "<<__$DEF_ALIAS8980>>" (rect 96 392 214 409)(font "Intel Clear" )(invisible)) (text "0,S[7..1]" (rect 530 -40 567 -23)(font "Intel Clear" ))
(pt 96 408) (pt 520 -16)
(pt 192 408) (pt 688 -16)
(bus) (bus)
) )
(connector (connector
(text "D[7..0]" (rect 354 392 384 409)(font "Intel Clear" )) (pt 976 16)
(pt 344 408) (pt 976 152)
(pt 392 408)
(bus) (bus)
) )
(connector (connector
(text "0,S[7..1]" (rect 578 -160 615 -143)(font "Intel Clear" )) (pt 944 16)
(pt 568 -136) (pt 976 16)
(pt 736 -136) (bus)
)
(connector
(pt 944 -16)
(pt 992 -16)
(bus) (bus)
) )
(connector (connector
(pt 992 104) (pt 992 104)
(pt 992 -112) (pt 992 -16)
(bus) (bus)
) )
(connector (connector
(pt 992 -112) (text "0,D[7..1]" (rect 538 0 576 17)(font "Intel Clear" ))
(pt 848 -112) (pt 528 16)
(pt 688 16)
(bus) (bus)
) )
(connector (connector
(pt 976 152) (pt 688 48)
(pt 976 64) (pt 488 48)
)
(connector
(text "0,0,0,0,0,0,0,0,EXTRA[7..0]" (rect 1144 232 1266 249)(font "Intel Clear" ))
(pt 1224 248)
(pt 1144 248)
(bus) (bus)
) )
(connector (connector
(pt 976 64) (text "DIFF[7..0]" (rect 106 392 150 409)(font "Intel Clear" ))
(pt 872 64) (pt 96 408)
(pt 152 408)
(bus) (bus)
) )
(connector (connector
(text "0,D[7..1]" (rect 610 24 648 41)(font "Intel Clear" )) (text "D[7..0]" (rect 474 232 504 249)(font "Intel Clear" ))
(pt 600 40) (pt 464 248)
(pt 760 40) (pt 512 248)
(bus)
)
(connector
(text "DIFF[7..0]" (rect 282 232 326 249)(font "Intel Clear" ))
(pt 312 248)
(pt 272 248)
(bus)
)
(connector
(pt 520 472)
(pt 800 472)
(bus)
)
(connector
(text "DIFF[7]" (rect 298 456 332 473)(font "Intel Clear" ))
(pt 360 472)
(pt 288 472)
)
(connector
(text "A[7..0]" (rect 298 472 328 489)(font "Intel Clear" ))
(pt 360 488)
(pt 288 488)
(bus)
)
(connector
(text "B[7..0]" (rect 298 488 328 505)(font "Intel Clear" ))
(pt 360 504)
(pt 288 504)
(bus) (bus)
) )
(junction (pt -200 160)) (junction (pt -200 160))

17
mul8.bsf
View file

@ -27,17 +27,24 @@ https://fpgasoftware.intel.com/eula.
(port (port
(pt 0 32) (pt 0 32)
(input) (input)
(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8))) (text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
(text "A[7..0]" (rect 21 27 59 46)(font "Intel Clear" (font_size 8))) (text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3)) (line (pt 0 32)(pt 16 32))
) )
(port (port
(pt 0 48) (pt 0 48)
(input) (input)
(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8))) (text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "B[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8))) (text "A[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 3)) (line (pt 0 48)(pt 16 48)(line_width 3))
) )
(port
(pt 0 64)
(input)
(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "B[7..0]" (rect 21 59 59 78)(font "Intel Clear" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port (port
(pt 168 32) (pt 168 32)
(output) (output)