mirror of
https://github.com/supleed2/ELEC40006-P1-CW.git
synced 2024-11-10 02:05:48 +00:00
230 lines
9.6 KiB
Verilog
230 lines
9.6 KiB
Verilog
// megafunction wizard: %ROM: 2-PORT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altsyncram
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// ============================================================
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// File Name: LUT.v
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// Megafunction Name(s):
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// altsyncram
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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// ************************************************************
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//Copyright (C) 2019 Intel Corporation. All rights reserved.
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//Your use of Intel Corporation's design tools, logic functions
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//and other software and tools, and any partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Intel Program License
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//Subscription Agreement, the Intel Quartus Prime License Agreement,
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//the Intel FPGA IP License Agreement, or other applicable license
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//agreement, including, without limitation, that your use is for
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//the sole purpose of programming logic devices manufactured by
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//Intel and sold by Intel or its authorized distributors. Please
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//refer to the applicable agreement for further details, at
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//https://fpgasoftware.intel.com/eula.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module LUT (
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address_a,
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address_b,
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clock,
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q_a,
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q_b);
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input [7:0] address_a;
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input [7:0] address_b;
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input clock;
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output [15:0] q_a;
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output [15:0] q_b;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 clock;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [15:0] sub_wire0 = 16'h0;
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wire sub_wire1 = 1'h0;
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wire [15:0] sub_wire2;
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wire [15:0] sub_wire3;
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wire [15:0] q_a = sub_wire2[15:0];
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wire [15:0] q_b = sub_wire3[15:0];
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altsyncram altsyncram_component (
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.address_a (address_a),
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.address_b (address_b),
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.clock0 (clock),
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.data_a (sub_wire0),
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.data_b (sub_wire0),
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.wren_a (sub_wire1),
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.wren_b (sub_wire1),
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.q_a (sub_wire2),
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.q_b (sub_wire3)
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// synopsys translate_off
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,
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.aclr0 (),
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.aclr1 (),
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.addressstall_a (),
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.addressstall_b (),
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.byteena_a (),
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.byteena_b (),
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.clock1 (),
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.clocken0 (),
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.clocken1 (),
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.clocken2 (),
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.clocken3 (),
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.eccstatus (),
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.rden_a (),
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.rden_b ()
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// synopsys translate_on
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);
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defparam
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altsyncram_component.address_reg_b = "CLOCK0",
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_output_a = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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altsyncram_component.indata_reg_b = "CLOCK0",
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altsyncram_component.init_file = "LUTSquares.mif",
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altsyncram_component.intended_device_family = "Cyclone IV E",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 256,
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altsyncram_component.numwords_b = 256,
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altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
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altsyncram_component.outdata_aclr_a = "NONE",
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altsyncram_component.outdata_aclr_b = "NONE",
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altsyncram_component.outdata_reg_a = "CLOCK0",
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altsyncram_component.outdata_reg_b = "CLOCK0",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.widthad_a = 8,
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altsyncram_component.widthad_b = 8,
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altsyncram_component.width_a = 16,
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altsyncram_component.width_b = 16,
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altsyncram_component.width_byteena_a = 1,
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altsyncram_component.width_byteena_b = 1,
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altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
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// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
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// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
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// Retrieval info: PRIVATE: CLRq NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
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// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
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// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
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// Retrieval info: PRIVATE: Clock NUMERIC "0"
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// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
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// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
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// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
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// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
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// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
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// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
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// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING "LUTSquares.mif"
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// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
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// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
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// Retrieval info: PRIVATE: REGdata NUMERIC "1"
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// Retrieval info: PRIVATE: REGq NUMERIC "1"
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// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
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// Retrieval info: PRIVATE: REGrren NUMERIC "0"
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// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
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// Retrieval info: PRIVATE: REGwren NUMERIC "1"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
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// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
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// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
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// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
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// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
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// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
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// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
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// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
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// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: enable NUMERIC "0"
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// Retrieval info: PRIVATE: rden NUMERIC "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
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// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
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// Retrieval info: CONSTANT: INIT_FILE STRING "LUTSquares.mif"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
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// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
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// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
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// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
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// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
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// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
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// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
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// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
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// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
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// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
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// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
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// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
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// Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL "address_a[7..0]"
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// Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL "address_b[7..0]"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
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// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
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// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
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// Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
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// Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
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// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: @data_a 0 0 16 0 GND 0 0 16 0
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// Retrieval info: CONNECT: @data_b 0 0 16 0 GND 0 0 16 0
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// Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0
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// Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0
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// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
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// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL LUT.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL LUT.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL LUT.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL LUT.bsf TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL LUT_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL LUT_bb.v FALSE
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// Retrieval info: LIB_FILE: altera_mf
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