mirror of
https://github.com/supleed2/ELEC40006-P1-CW.git
synced 2024-12-22 21:45:49 +00:00
CPU set up for testing and analysis
This commit is contained in:
parent
6c1f7fc59b
commit
87f3d0e919
291
ALU_top.bdf
291
ALU_top.bdf
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@ -118,7 +118,7 @@ https://fpgasoftware.intel.com/eula.
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@ -482,47 +397,17 @@ https://fpgasoftware.intel.com/eula.
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36
ALU_top.bsf
36
ALU_top.bsf
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@ -76,16 +76,9 @@ https://fpgasoftware.intel.com/eula.
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1178
CPUProject.bdf
1178
CPUProject.bdf
File diff suppressed because it is too large
Load diff
|
|
@ -62,6 +62,7 @@ set_global_assignment -name POWER_USE_PVA ON
|
|||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name SDC_FILE CPUProject.sdc
|
||||
set_global_assignment -name VERILOG_FILE LIFOstack.v
|
||||
set_global_assignment -name VERILOG_FILE alu.v
|
||||
set_global_assignment -name MIF_FILE LUTSquares.mif
|
||||
|
|
@ -84,4 +85,5 @@ set_global_assignment -name VERILOG_FILE mux_3x16.v
|
|||
set_global_assignment -name VERILOG_FILE ADD_1.v
|
||||
set_global_assignment -name VERILOG_FILE SM_pipelined.v
|
||||
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
|
||||
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
BIN
CPUProject.qws
Normal file
BIN
CPUProject.qws
Normal file
Binary file not shown.
4
CPUProject.sdc
Normal file
4
CPUProject.sdc
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
#This file must have the same name as your project
|
||||
|
||||
#Make input CLK a clock and set frequency to 100MHz (10ns period)
|
||||
create_clock -name {CLK} -period 10.0 [get_ports {CLK}]
|
||||
4
CPUProject.sdc.bak
Normal file
4
CPUProject.sdc.bak
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
#This file must have the same name as your project
|
||||
|
||||
#Make input CLK a clock and set frequency to 250MHz (4ns period)
|
||||
create_clock -name {CLK} -period 4.0 [get_ports {CLK}]
|
||||
|
|
@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
|
|||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
|
|
@ -16,7 +16,8 @@ the Intel FPGA IP License Agreement, or other applicable license
|
|||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
|
|
@ -65,20 +66,6 @@ refer to the applicable agreement for further details.
|
|||
(text "Dout[15..0]" (rect 121 27 163 39)(font "Arial" ))
|
||||
(line (pt 184 32)(pt 168 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 184 48)
|
||||
(output)
|
||||
(text "empty" (rect 0 0 25 12)(font "Arial" ))
|
||||
(text "empty" (rect 138 43 163 55)(font "Arial" ))
|
||||
(line (pt 184 48)(pt 168 48)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 184 64)
|
||||
(output)
|
||||
(text "full" (rect 0 0 10 12)(font "Arial" ))
|
||||
(text "full" (rect 153 59 163 71)(font "Arial" ))
|
||||
(line (pt 184 64)(pt 168 64)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 168 128)(line_width 1))
|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
module LIFOstack (Din, clk, en, rst, rw, Dout, empty, full);
|
||||
module LIFOstack (Din, clk, en, rst, rw, Dout);
|
||||
|
||||
input [15:0] Din; // Data being fed to stack
|
||||
input clk; // clock signal input
|
||||
|
|
@ -7,8 +7,8 @@ input rst; // reset pin to clear and reinitialise stack (active high)
|
|||
input rw; // 0: read, 1: write
|
||||
|
||||
output reg [15:0] Dout; // Data being pulled from stack
|
||||
output reg empty; // goes high to indicate SP is at 0
|
||||
output reg full; // goes high to indicate SP is at (slots)
|
||||
reg empty; // goes high to indicate SP is at 0
|
||||
reg full; // goes high to indicate SP is at (slots)
|
||||
|
||||
reg [5:0] SP; // Points to slot to save next value to
|
||||
integer i;
|
||||
|
|
|
|||
57
alu.bsf
57
alu.bsf
|
|
@ -21,9 +21,9 @@ https://fpgasoftware.intel.com/eula.
|
|||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 16 16 248 224)
|
||||
(rect 16 16 240 192)
|
||||
(text "alu" (rect 5 0 15 12)(font "Arial" ))
|
||||
(text "inst" (rect 8 192 20 204)(font "Arial" ))
|
||||
(text "inst" (rect 8 160 20 172)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
|
|
@ -81,62 +81,41 @@ https://fpgasoftware.intel.com/eula.
|
|||
(line (pt 0 144)(pt 16 144)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 160)
|
||||
(input)
|
||||
(text "memdatain[15..0]" (rect 0 0 67 12)(font "Arial" ))
|
||||
(text "memdatain[15..0]" (rect 21 155 88 167)(font "Arial" ))
|
||||
(line (pt 0 160)(pt 16 160)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 232 32)
|
||||
(pt 224 32)
|
||||
(output)
|
||||
(text "mul1[15..0]" (rect 0 0 41 12)(font "Arial" ))
|
||||
(text "mul1[15..0]" (rect 170 27 211 39)(font "Arial" ))
|
||||
(line (pt 232 32)(pt 216 32)(line_width 3))
|
||||
(text "mul1[15..0]" (rect 162 27 203 39)(font "Arial" ))
|
||||
(line (pt 224 32)(pt 208 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 232 48)
|
||||
(pt 224 48)
|
||||
(output)
|
||||
(text "mul2[15..0]" (rect 0 0 42 12)(font "Arial" ))
|
||||
(text "mul2[15..0]" (rect 169 43 211 55)(font "Arial" ))
|
||||
(line (pt 232 48)(pt 216 48)(line_width 3))
|
||||
(text "mul2[15..0]" (rect 161 43 203 55)(font "Arial" ))
|
||||
(line (pt 224 48)(pt 208 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 232 64)
|
||||
(pt 224 64)
|
||||
(output)
|
||||
(text "Rout[15..0]" (rect 0 0 43 12)(font "Arial" ))
|
||||
(text "Rout[15..0]" (rect 168 59 211 71)(font "Arial" ))
|
||||
(line (pt 232 64)(pt 216 64)(line_width 3))
|
||||
(text "Rout[15..0]" (rect 160 59 203 71)(font "Arial" ))
|
||||
(line (pt 224 64)(pt 208 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 232 80)
|
||||
(pt 224 80)
|
||||
(output)
|
||||
(text "jump" (rect 0 0 18 12)(font "Arial" ))
|
||||
(text "jump" (rect 193 75 211 87)(font "Arial" ))
|
||||
(line (pt 232 80)(pt 216 80)(line_width 1))
|
||||
(text "jump" (rect 185 75 203 87)(font "Arial" ))
|
||||
(line (pt 224 80)(pt 208 80)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 232 96)
|
||||
(output)
|
||||
(text "carry" (rect 0 0 22 12)(font "Arial" ))
|
||||
(text "carry" (rect 189 91 211 103)(font "Arial" ))
|
||||
(line (pt 232 96)(pt 216 96)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 232 112)
|
||||
(output)
|
||||
(text "jumpflags[7..0]" (rect 0 0 57 12)(font "Arial" ))
|
||||
(text "jumpflags[7..0]" (rect 154 107 211 119)(font "Arial" ))
|
||||
(line (pt 232 112)(pt 216 112)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 232 128)
|
||||
(pt 224 96)
|
||||
(output)
|
||||
(text "memaddr[10..0]" (rect 0 0 62 12)(font "Arial" ))
|
||||
(text "memaddr[10..0]" (rect 149 123 211 135)(font "Arial" ))
|
||||
(line (pt 232 128)(pt 216 128)(line_width 3))
|
||||
(text "memaddr[10..0]" (rect 141 91 203 103)(font "Arial" ))
|
||||
(line (pt 224 96)(pt 208 96)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 216 192)(line_width 1))
|
||||
(rectangle (rect 16 16 208 160)(line_width 1))
|
||||
)
|
||||
)
|
||||
|
|
|
|||
Loading…
Reference in a new issue