CPU set up for testing and analysis

This commit is contained in:
Aadi Desai 2020-06-11 17:28:00 +01:00
parent 6c1f7fc59b
commit 87f3d0e919
10 changed files with 266 additions and 1333 deletions

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@ -76,16 +76,9 @@ https://fpgasoftware.intel.com/eula.
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@ -62,6 +62,7 @@ set_global_assignment -name POWER_USE_PVA ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SDC_FILE CPUProject.sdc
set_global_assignment -name VERILOG_FILE LIFOstack.v
set_global_assignment -name VERILOG_FILE alu.v
set_global_assignment -name MIF_FILE LUTSquares.mif
@ -84,4 +85,5 @@ set_global_assignment -name VERILOG_FILE mux_3x16.v
set_global_assignment -name VERILOG_FILE ADD_1.v
set_global_assignment -name VERILOG_FILE SM_pipelined.v
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
CPUProject.qws Normal file

Binary file not shown.

4
CPUProject.sdc Normal file
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@ -0,0 +1,4 @@
#This file must have the same name as your project
#Make input CLK a clock and set frequency to 100MHz (10ns period)
create_clock -name {CLK} -period 10.0 [get_ports {CLK}]

4
CPUProject.sdc.bak Normal file
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@ -0,0 +1,4 @@
#This file must have the same name as your project
#Make input CLK a clock and set frequency to 250MHz (4ns period)
create_clock -name {CLK} -period 4.0 [get_ports {CLK}]

View file

@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2018 Intel Corporation. All rights reserved.
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
@ -16,7 +16,8 @@ the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
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@ -65,20 +66,6 @@ refer to the applicable agreement for further details.
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@ -1,4 +1,4 @@
module LIFOstack (Din, clk, en, rst, rw, Dout, empty, full);
module LIFOstack (Din, clk, en, rst, rw, Dout);
input [15:0] Din; // Data being fed to stack
input clk; // clock signal input
@ -7,8 +7,8 @@ input rst; // reset pin to clear and reinitialise stack (active high)
input rw; // 0: read, 1: write
output reg [15:0] Dout; // Data being pulled from stack
output reg empty; // goes high to indicate SP is at 0
output reg full; // goes high to indicate SP is at (slots)
reg empty; // goes high to indicate SP is at 0
reg full; // goes high to indicate SP is at (slots)
reg [5:0] SP; // Points to slot to save next value to
integer i;

57
alu.bsf
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@ -21,9 +21,9 @@ https://fpgasoftware.intel.com/eula.
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