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CPU set up for testing and analysis

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This commit is contained in:
Aadi Desai 2020-06-11 17:28:00 +01:00
parent 6c1f7fc59b
commit 87f3d0e919
10 changed files with 266 additions and 1333 deletions
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291
ALU_top.bdf
View file

@ -118,7 +118,7 @@ https://fpgasoftware.intel.com/eula.
) )
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(text "CLK" (rect 9 0 30 12)(font "Arial" )) (text "CLK" (rect 9 0 30 12)(font "Arial" ))
(pt 176 8) (pt 176 8)
@ -148,25 +148,9 @@ https://fpgasoftware.intel.com/eula.
) )
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@ -182,7 +166,7 @@ https://fpgasoftware.intel.com/eula.
) )
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@ -198,55 +182,7 @@ https://fpgasoftware.intel.com/eula.
) )
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@ -262,7 +198,7 @@ https://fpgasoftware.intel.com/eula.
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@ -278,9 +214,9 @@ https://fpgasoftware.intel.com/eula.
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@ -293,7 +229,7 @@ https://fpgasoftware.intel.com/eula.
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@ -329,9 +265,9 @@ https://fpgasoftware.intel.com/eula.
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@ -389,63 +325,42 @@ https://fpgasoftware.intel.com/eula.
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@ -482,47 +397,17 @@ https://fpgasoftware.intel.com/eula.
(bus) (bus)
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@ -531,78 +416,88 @@ https://fpgasoftware.intel.com/eula.
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36
ALU_top.bsf
View file

@ -76,16 +76,9 @@ https://fpgasoftware.intel.com/eula.
(port (port
(pt 0 144) (pt 0 144)
(input) (input)
(text "memdatain[15..0]" (rect 0 0 107 19)(font "Intel Clear" (font_size 8)))
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(line (pt 0 144)(pt 16 144)(line_width 3))
)
(port
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(input)
(text "CLK" (rect 0 0 23 19)(font "Intel Clear" (font_size 8))) (text "CLK" (rect 0 0 23 19)(font "Intel Clear" (font_size 8)))
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(line (pt 0 160)(pt 16 160)) (line (pt 0 144)(pt 16 144))
) )
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@ -118,30 +111,9 @@ https://fpgasoftware.intel.com/eula.
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1178
CPUProject.bdf
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File diff suppressed because it is too large Load diff

2
CPUProject.qsf
View file

@ -62,6 +62,7 @@ set_global_assignment -name POWER_USE_PVA ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SDC_FILE CPUProject.sdc
set_global_assignment -name VERILOG_FILE LIFOstack.v set_global_assignment -name VERILOG_FILE LIFOstack.v
set_global_assignment -name VERILOG_FILE alu.v set_global_assignment -name VERILOG_FILE alu.v
set_global_assignment -name MIF_FILE LUTSquares.mif set_global_assignment -name MIF_FILE LUTSquares.mif
@ -84,4 +85,5 @@ set_global_assignment -name VERILOG_FILE mux_3x16.v
set_global_assignment -name VERILOG_FILE ADD_1.v set_global_assignment -name VERILOG_FILE ADD_1.v
set_global_assignment -name VERILOG_FILE SM_pipelined.v set_global_assignment -name VERILOG_FILE SM_pipelined.v
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
CPUProject.qws Normal file
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Binary file not shown.

4
CPUProject.sdc Normal file
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@ -0,0 +1,4 @@
#This file must have the same name as your project
#Make input CLK a clock and set frequency to 100MHz (10ns period)
create_clock -name {CLK} -period 10.0 [get_ports {CLK}]

4
CPUProject.sdc.bak Normal file
View file

@ -0,0 +1,4 @@
#This file must have the same name as your project
#Make input CLK a clock and set frequency to 250MHz (4ns period)
create_clock -name {CLK} -period 4.0 [get_ports {CLK}]

21
LIFOstack.bsf
View file

@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 2018 Intel Corporation. All rights reserved. Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic and other software and tools, and any partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
(including device programming or simulation files), and any (including device programming or simulation files), and any
associated documentation or information are expressly subject associated documentation or information are expressly subject
@ -16,7 +16,8 @@ the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details. refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/ */
(header "symbol" (version "1.1")) (header "symbol" (version "1.1"))
(symbol (symbol
@ -65,20 +66,6 @@ refer to the applicable agreement for further details.
(text "Dout[15..0]" (rect 121 27 163 39)(font "Arial" )) (text "Dout[15..0]" (rect 121 27 163 39)(font "Arial" ))
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) )
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(output)
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(text "empty" (rect 138 43 163 55)(font "Arial" ))
(line (pt 184 48)(pt 168 48)(line_width 1))
)
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(text "full" (rect 153 59 163 71)(font "Arial" ))
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)
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(rectangle (rect 16 16 168 128)(line_width 1)) (rectangle (rect 16 16 168 128)(line_width 1))
) )

6
LIFOstack.v
View file

@ -1,4 +1,4 @@
module LIFOstack (Din, clk, en, rst, rw, Dout, empty, full); module LIFOstack (Din, clk, en, rst, rw, Dout);
input [15:0] Din; // Data being fed to stack input [15:0] Din; // Data being fed to stack
input clk; // clock signal input input clk; // clock signal input
@ -7,8 +7,8 @@ input rst; // reset pin to clear and reinitialise stack (active high)
input rw; // 0: read, 1: write input rw; // 0: read, 1: write
output reg [15:0] Dout; // Data being pulled from stack output reg [15:0] Dout; // Data being pulled from stack
output reg empty; // goes high to indicate SP is at 0 reg empty; // goes high to indicate SP is at 0
output reg full; // goes high to indicate SP is at (slots) reg full; // goes high to indicate SP is at (slots)
reg [5:0] SP; // Points to slot to save next value to reg [5:0] SP; // Points to slot to save next value to
integer i; integer i;

57
alu.bsf
View file

@ -21,9 +21,9 @@ https://fpgasoftware.intel.com/eula.
*/ */
(header "symbol" (version "1.1")) (header "symbol" (version "1.1"))
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@ -81,62 +81,41 @@ https://fpgasoftware.intel.com/eula.
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(text "jump" (rect 193 75 211 87)(font "Arial" )) (text "jump" (rect 185 75 203 87)(font "Arial" ))
(line (pt 232 80)(pt 216 80)(line_width 1)) (line (pt 224 80)(pt 208 80)(line_width 1))
) )
(port (port
(pt 232 96) (pt 224 96)
(output)
(text "carry" (rect 0 0 22 12)(font "Arial" ))
(text "carry" (rect 189 91 211 103)(font "Arial" ))
(line (pt 232 96)(pt 216 96)(line_width 1))
)
(port
(pt 232 112)
(output)
(text "jumpflags[7..0]" (rect 0 0 57 12)(font "Arial" ))
(text "jumpflags[7..0]" (rect 154 107 211 119)(font "Arial" ))
(line (pt 232 112)(pt 216 112)(line_width 3))
)
(port
(pt 232 128)
(output) (output)
(text "memaddr[10..0]" (rect 0 0 62 12)(font "Arial" )) (text "memaddr[10..0]" (rect 0 0 62 12)(font "Arial" ))
(text "memaddr[10..0]" (rect 149 123 211 135)(font "Arial" )) (text "memaddr[10..0]" (rect 141 91 203 103)(font "Arial" ))
(line (pt 232 128)(pt 216 128)(line_width 3)) (line (pt 224 96)(pt 208 96)(line_width 3))
) )
(drawing (drawing
(rectangle (rect 16 16 216 192)(line_width 1)) (rectangle (rect 16 16 208 160)(line_width 1))
) )
) )