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Kacper 2020-05-27 11:10:13 +01:00
parent 9db1fb0af6
commit 5ed70dabb0
13 changed files with 1398 additions and 408 deletions
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1175
CPUProject.bdf
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File diff suppressed because it is too large Load diff

8
CPUProject.qsf
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@ -38,7 +38,7 @@
set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE AUTO set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY CPUProject set_global_assignment -name TOP_LEVEL_ENTITY test
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020" set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition" set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
@ -49,7 +49,13 @@ set_global_assignment -name BDF_FILE CPUProject.bdf
set_global_assignment -name BDF_FILE reg_file.bdf set_global_assignment -name BDF_FILE reg_file.bdf
set_global_assignment -name BDF_FILE mux_8x16.bdf set_global_assignment -name BDF_FILE mux_8x16.bdf
set_global_assignment -name QIP_FILE ram_data.qip set_global_assignment -name QIP_FILE ram_data.qip
set_global_assignment -name QIP_FILE ram_instr.qip
set_global_assignment -name BDF_FILE SM.bdf
set_global_assignment -name VERILOG_FILE DECODE.v
set_global_assignment -name MIF_FILE test.mif
set_global_assignment -name BDF_FILE test.bdf
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
CPUProject.qws
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32
DECODE.v Normal file
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@ -0,0 +1,32 @@
module DECODE
(
input [15:0] instr,
input FETCH,
input EXEC,
input COND_result,
output R0_count,
output R1_en,
output R2_en,
output R3_en,
output R4_en,
output R5_en,
output R6_en,
output R7_en,
output [2:0] s1,
output [2:0] s2,
output [2:0] s3,
output s4,
output RAMd_wren,
output RAMd_en,
output RAMi_en
);
wire msb, ls, [reg_ls, addr, op, Rd, Rs1, Rs2;
assign msb = instr[15]; //MSB of the instruction word
assign ls = instr[14]; //LOAD or STORE bit
assign reg_ls = instr
wire LOAD, STORE, UJMP, JMP, AND, OR, XOR, NOT, NND, NOR, XNR, MOV, ADD, ADC, ADO, SUB, SBC, SBO, MUL, MLA, MLS, MRT, LSL, LSR, ASR, ROR, RRC, NOP, STP;
assign LOAD =
endmodule

20
DECODE.v.bak Normal file
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@ -0,0 +1,20 @@
module DECODE
(
input [15:0]instr,
input FETCH,
input EXEC,
output R0_count,
output R1_en,
output R2_en,
output R3_en,
output R4_en,
output R5_en,
output R6_en,
output R7_en,
output [2:0]s1,
output [2:0]s2,
output [2:0]s3,
output s4,
output RAMd_wren,
output RAMd_en,

283
SM.bdf Normal file
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@ -0,0 +1,283 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 272 296 440 312)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "CLK" (rect 5 0 27 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 736 192 912 208)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "FETCH" (rect 90 0 126 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(pin
(output)
(rect 736 224 912 240)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "EXEC" (rect 90 0 115 17)(font "Intel Clear" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(symbol
(rect 448 216 624 360)
(text "LPM_FF" (rect 19 0 78 16)(font "Arial" (font_size 10)))
(text "STATE" (rect 3 133 41 147)(font "Arial" (font_size 8)))
(port
(pt 88 144)
(input)
(text "aclr" (rect 80 113 101 127)(font "Arial" (font_size 8)))
(text "aclr" (rect 80 113 101 127)(font "Arial" (font_size 8)))
(line (pt 88 144)(pt 88 128))
(unused)
)
(port
(pt 0 24)
(input)
(text "aload" (rect 20 17 50 31)(font "Arial" (font_size 8)))
(text "aload" (rect 20 17 50 31)(font "Arial" (font_size 8)))
(line (pt 0 24)(pt 16 24))
(unused)
)
(port
(pt 88 0)
(input)
(text "aset" (rect 79 17 103 31)(font "Arial" (font_size 8)))
(text "aset" (rect 79 17 103 31)(font "Arial" (font_size 8)))
(line (pt 88 16)(pt 88 0))
(unused)
)
(port
(pt 0 88)
(input)
(text "clock" (rect 20 81 49 95)(font "Arial" (font_size 8))(invisible))
(text "clock" (rect 20 81 49 95)(font "Arial" (font_size 8))(invisible))
(line (pt 0 88)(pt 16 88))
)
(port
(pt 0 72)
(input)
(text "data[LPM_WIDTH-1..0]" (rect 20 63 146 77)(font "Arial" (font_size 8)))
(text "data[]" (rect 20 63 51 77)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 16 72)(line_width 3))
)
(port
(pt 0 104)
(input)
(text "enable" (rect 20 97 57 111)(font "Arial" (font_size 8)))
(text "enable" (rect 20 97 57 111)(font "Arial" (font_size 8)))
(line (pt 0 104)(pt 16 104))
(unused)
)
(port
(pt 0 120)
(input)
(text "sclr" (rect 20 113 41 127)(font "Arial" (font_size 8)))
(text "sclr" (rect 20 113 41 127)(font "Arial" (font_size 8)))
(line (pt 0 120)(pt 16 120))
(unused)
)
(port
(pt 0 56)
(input)
(text "sload" (rect 20 49 50 63)(font "Arial" (font_size 8)))
(text "sload" (rect 20 49 50 63)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 16 56))
(unused)
)
(port
(pt 0 40)
(input)
(text "sset" (rect 20 33 44 47)(font "Arial" (font_size 8)))
(text "sset" (rect 20 33 44 47)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 16 40))
(unused)
)
(port
(pt 176 88)
(output)
(text "q[LPM_WIDTH-1..0]" (rect 144 81 252 95)(font "Arial" (font_size 8)))
(text "q[]" (rect 144 81 158 95)(font "Arial" (font_size 8)))
(line (pt 160 88)(pt 176 88)(line_width 3))
)
(parameter
"LPM_AVALUE"
""
"Unsigned value associated with the aset port"
)
(parameter
"LPM_FFTYPE"
"\"DFF\""
"Selects behavior as DFF or TFF"
"\"DFF\"" "\"TFF\""
)
(parameter
"LPM_SVALUE"
""
"Unsigned value associated with the sset port"
)
(parameter
"LPM_WIDTH"
"1"
"Width of I/O, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
)
(drawing
(line (pt 16 16)(pt 160 16))
(line (pt 16 128)(pt 160 128))
(line (pt 160 128)(pt 160 16))
(line (pt 16 128)(pt 16 16))
(line (pt 16 80)(pt 24 88))
(line (pt 24 88)(pt 16 96))
)
(annotation_block (parameter)(rect 624 216 648 232))
)
(symbol
(rect 512 168 560 200)
(text "NOT" (rect 27 0 47 10)(font "Arial" (font_size 6)))
(text "NOT1" (rect 17 21 45 33)(font "Arial" ))
(port
(pt 48 16)
(input)
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
(text "IN" (rect 35 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 48 16)(pt 35 16))
)
(port
(pt 0 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect -1 7 16 19)(font "Courier New" (bold))(invisible))
(line (pt 9 16)(pt 0 16))
)
(drawing
(line (pt 35 25)(pt 35 7))
(line (pt 35 7)(pt 17 16))
(line (pt 35 25)(pt 17 16))
(circle (rect 9 12 17 20))
)
(flipy)
)
(symbol
(rect 680 184 728 216)
(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
(text "NOT2" (rect 3 21 31 33)(font "Arial" ))
(port
(pt 0 16)
(input)
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 13 16))
)
(port
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
)
(drawing
(line (pt 13 25)(pt 13 7))
(line (pt 13 7)(pt 31 16))
(line (pt 13 25)(pt 31 16))
(circle (rect 31 12 39 20))
)
)
(connector
(pt 448 304)
(pt 440 304)
)
(connector
(pt 624 304)
(pt 664 304)
)
(connector
(pt 560 184)
(pt 664 184)
)
(connector
(pt 512 184)
(pt 432 184)
)
(connector
(pt 432 184)
(pt 432 288)
)
(connector
(pt 432 288)
(pt 448 288)
)
(connector
(pt 680 200)
(pt 664 200)
)
(connector
(pt 664 184)
(pt 664 200)
)
(connector
(pt 728 200)
(pt 736 200)
)
(connector
(pt 736 232)
(pt 664 232)
)
(connector
(pt 664 200)
(pt 664 232)
)
(connector
(pt 664 232)
(pt 664 304)
)
(junction (pt 664 200))
(junction (pt 664 232))

50
SM.bsf Normal file
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@ -0,0 +1,50 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 136 112)
(text "SM" (rect 5 0 23 19)(font "Intel Clear" (font_size 8)))
(text "inst" (rect 8 75 24 92)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "CLK" (rect 0 0 23 19)(font "Intel Clear" (font_size 8)))
(text "CLK" (rect 21 27 44 46)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 120 32)
(output)
(text "FETCH" (rect 0 0 40 19)(font "Intel Clear" (font_size 8)))
(text "FETCH" (rect 59 27 99 46)(font "Intel Clear" (font_size 8)))
(line (pt 120 32)(pt 104 32))
)
(port
(pt 120 48)
(output)
(text "EXEC" (rect 0 0 30 19)(font "Intel Clear" (font_size 8)))
(text "EXEC" (rect 69 43 99 62)(font "Intel Clear" (font_size 8)))
(line (pt 120 48)(pt 104 48))
)
(drawing
(rectangle (rect 16 16 104 80))
)
)

19
ram_data.bsf
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@ -20,9 +20,9 @@ refer to the applicable agreement for further details.
*/ */
(header "symbol" (version "1.2")) (header "symbol" (version "1.2"))
(symbol (symbol
(rect 0 0 216 128) (rect 0 0 216 144)
(text "ram_data" (rect 81 0 144 16)(font "Arial" (font_size 10))) (text "ram_data" (rect 81 0 144 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 112 25 124)(font "Arial" )) (text "inst" (rect 8 128 25 140)(font "Arial" ))
(port (port
(pt 0 32) (pt 0 32)
(input) (input)
@ -51,6 +51,13 @@ refer to the applicable agreement for further details.
(text "clock" (rect 4 98 27 111)(font "Arial" (font_size 8))) (text "clock" (rect 4 98 27 111)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 80 112)) (line (pt 0 112)(pt 80 112))
) )
(port
(pt 0 128)
(input)
(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clken" (rect 4 114 27 127)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 16 128))
)
(port (port
(pt 216 32) (pt 216 32)
(output) (output)
@ -61,7 +68,7 @@ refer to the applicable agreement for further details.
(drawing (drawing
(text "16 bits" (rect 109 24 194 159)(font "Arial" )(vertical)) (text "16 bits" (rect 109 24 194 159)(font "Arial" )(vertical))
(text "2048 words" (rect 120 12 214 177)(font "Arial" )(vertical)) (text "2048 words" (rect 120 12 214 177)(font "Arial" )(vertical))
(text "Block type: AUTO" (rect 48 114 170 239)(font "Arial" )) (text "Block type: AUTO" (rect 48 130 170 271)(font "Arial" ))
(line (pt 104 24)(pt 136 24)) (line (pt 104 24)(pt 136 24))
(line (pt 136 24)(pt 136 96)) (line (pt 136 24)(pt 136 96))
(line (pt 136 96)(pt 104 96)) (line (pt 136 96)(pt 104 96))
@ -94,9 +101,9 @@ refer to the applicable agreement for further details.
(line (pt 96 64)(pt 104 64)(line_width 3)) (line (pt 96 64)(pt 104 64)(line_width 3))
(line (pt 80 112)(pt 80 36)) (line (pt 80 112)(pt 80 36))
(line (pt 0 0)(pt 217 0)) (line (pt 0 0)(pt 217 0))
(line (pt 217 0)(pt 217 130)) (line (pt 217 0)(pt 217 146))
(line (pt 0 130)(pt 217 130)) (line (pt 0 146)(pt 217 146))
(line (pt 0 0)(pt 0 130)) (line (pt 0 0)(pt 0 146))
(line (pt 0 0)(pt 0 0)) (line (pt 0 0)(pt 0 0))
(line (pt 0 0)(pt 0 0)) (line (pt 0 0)(pt 0 0))
(line (pt 0 0)(pt 0 0)) (line (pt 0 0)(pt 0 0))

1
ram_data.qip
View file

@ -3,4 +3,3 @@ set_global_assignment -name IP_TOOL_VERSION "18.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram_data.v"] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram_data.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_data.bsf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_data.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_data_bb.v"]

23
ram_data.v
View file

@ -38,12 +38,14 @@
// synopsys translate_on // synopsys translate_on
module ram_data ( module ram_data (
address, address,
clken,
clock, clock,
data, data,
wren, wren,
q); q);
input [10:0] address; input [10:0] address;
input clken;
input clock; input clock;
input [15:0] data; input [15:0] data;
input wren; input wren;
@ -51,6 +53,7 @@ module ram_data (
`ifndef ALTERA_RESERVED_QIS `ifndef ALTERA_RESERVED_QIS
// synopsys translate_off // synopsys translate_off
`endif `endif
tri1 clken;
tri1 clock; tri1 clock;
`ifndef ALTERA_RESERVED_QIS `ifndef ALTERA_RESERVED_QIS
// synopsys translate_on // synopsys translate_on
@ -62,6 +65,7 @@ module ram_data (
altsyncram altsyncram_component ( altsyncram altsyncram_component (
.address_a (address), .address_a (address),
.clock0 (clock), .clock0 (clock),
.clocken0 (clken),
.data_a (data), .data_a (data),
.wren_a (wren), .wren_a (wren),
.q_a (sub_wire0), .q_a (sub_wire0),
@ -73,7 +77,6 @@ module ram_data (
.byteena_a (1'b1), .byteena_a (1'b1),
.byteena_b (1'b1), .byteena_b (1'b1),
.clock1 (1'b1), .clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1), .clocken1 (1'b1),
.clocken2 (1'b1), .clocken2 (1'b1),
.clocken3 (1'b1), .clocken3 (1'b1),
@ -84,8 +87,9 @@ module ram_data (
.rden_b (1'b1), .rden_b (1'b1),
.wren_b (1'b0)); .wren_b (1'b0));
defparam defparam
altsyncram_component.clock_enable_input_a = "BYPASS", altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS", altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "test.mif",
altsyncram_component.intended_device_family = "Cyclone IV E", altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram", altsyncram_component.lpm_type = "altsyncram",
@ -112,10 +116,10 @@ endmodule
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" // Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" // Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0" // Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
@ -124,7 +128,7 @@ endmodule
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "" // Retrieval info: PRIVATE: MIFfilename STRING "test.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048" // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
@ -139,8 +143,9 @@ endmodule
// Retrieval info: PRIVATE: WidthData NUMERIC "16" // Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0" // Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "test.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
@ -154,12 +159,14 @@ endmodule
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]" // Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0 // Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 // Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 // Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
@ -168,5 +175,5 @@ endmodule
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_data.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL ram_data.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_data.bsf TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL ram_data.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_data_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL ram_data_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_data_bb.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL ram_data_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf // Retrieval info: LIB_FILE: altera_mf

112
ram_instr.bsf Normal file
View file

@ -0,0 +1,112 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 0 0 216 144)
(text "ram_instr" (rect 81 0 144 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 128 25 140)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "data[15..0]" (rect 4 18 53 31)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 88 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "wren" (rect 0 0 30 14)(font "Arial" (font_size 8)))
(text "wren" (rect 4 34 28 47)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 88 48))
)
(port
(pt 0 64)
(input)
(text "address[10..0]" (rect 0 0 82 14)(font "Arial" (font_size 8)))
(text "address[10..0]" (rect 4 50 72 63)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 88 64)(line_width 3))
)
(port
(pt 0 112)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 4 98 27 111)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 80 112))
)
(port
(pt 0 128)
(input)
(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clken" (rect 4 114 27 127)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 16 128))
)
(port
(pt 216 32)
(output)
(text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "q[15..0]" (rect 177 18 211 31)(font "Arial" (font_size 8)))
(line (pt 216 32)(pt 136 32)(line_width 3))
)
(drawing
(text "16 bits" (rect 109 24 194 159)(font "Arial" )(vertical))
(text "2048 words" (rect 120 12 214 177)(font "Arial" )(vertical))
(text "Block type: AUTO" (rect 48 130 170 271)(font "Arial" ))
(line (pt 104 24)(pt 136 24))
(line (pt 136 24)(pt 136 96))
(line (pt 136 96)(pt 104 96))
(line (pt 104 96)(pt 104 24))
(line (pt 118 58)(pt 123 63))
(line (pt 118 62)(pt 123 57))
(line (pt 88 27)(pt 96 27))
(line (pt 96 27)(pt 96 39))
(line (pt 96 39)(pt 88 39))
(line (pt 88 39)(pt 88 27))
(line (pt 88 34)(pt 90 36))
(line (pt 90 36)(pt 88 38))
(line (pt 80 36)(pt 88 36))
(line (pt 96 32)(pt 104 32)(line_width 3))
(line (pt 88 43)(pt 96 43))
(line (pt 96 43)(pt 96 55))
(line (pt 96 55)(pt 88 55))
(line (pt 88 55)(pt 88 43))
(line (pt 88 50)(pt 90 52))
(line (pt 90 52)(pt 88 54))
(line (pt 80 52)(pt 88 52))
(line (pt 96 48)(pt 104 48))
(line (pt 88 59)(pt 96 59))
(line (pt 96 59)(pt 96 71))
(line (pt 96 71)(pt 88 71))
(line (pt 88 71)(pt 88 59))
(line (pt 88 66)(pt 90 68))
(line (pt 90 68)(pt 88 70))
(line (pt 80 68)(pt 88 68))
(line (pt 96 64)(pt 104 64)(line_width 3))
(line (pt 80 112)(pt 80 36))
(line (pt 0 0)(pt 217 0))
(line (pt 217 0)(pt 217 146))
(line (pt 0 146)(pt 217 146))
(line (pt 0 0)(pt 0 146))
(line (pt 0 0)(pt 0 0))
(line (pt 0 0)(pt 0 0))
(line (pt 0 0)(pt 0 0))
(line (pt 0 0)(pt 0 0))
)
)

5
ram_instr.qip Normal file
View file

@ -0,0 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "18.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram_instr.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_instr.bsf"]

78
ram_data_bb.v → ram_instr.v
View file

@ -1,10 +1,10 @@
// megafunction wizard: %RAM: 1-PORT%VBB% // megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD // GENERATION: STANDARD
// VERSION: WM1.0 // VERSION: WM1.0
// MODULE: altsyncram // MODULE: altsyncram
// ============================================================ // ============================================================
// File Name: ram_data.v // File Name: ram_instr.v
// Megafunction Name(s): // Megafunction Name(s):
// altsyncram // altsyncram
// //
@ -17,6 +17,7 @@
// 18.1.0 Build 625 09/12/2018 SJ Standard Edition // 18.1.0 Build 625 09/12/2018 SJ Standard Edition
// ************************************************************ // ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved. //Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions //Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic //and other software and tools, and its AMPP partner logic
@ -31,14 +32,20 @@
//Intel and sold by Intel or its authorized distributors. Please //Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details. //refer to the applicable agreement for further details.
module ram_data (
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram_instr (
address, address,
clken,
clock, clock,
data, data,
wren, wren,
q); q);
input [10:0] address; input [10:0] address;
input clken;
input clock; input clock;
input [15:0] data; input [15:0] data;
input wren; input wren;
@ -46,11 +53,56 @@ module ram_data (
`ifndef ALTERA_RESERVED_QIS `ifndef ALTERA_RESERVED_QIS
// synopsys translate_off // synopsys translate_off
`endif `endif
tri1 clken;
tri1 clock; tri1 clock;
`ifndef ALTERA_RESERVED_QIS `ifndef ALTERA_RESERVED_QIS
// synopsys translate_on // synopsys translate_on
`endif `endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.clocken0 (clken),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 1;
endmodule endmodule
// ============================================================ // ============================================================
@ -64,9 +116,9 @@ endmodule
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" // Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0" // Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
@ -90,7 +142,7 @@ endmodule
// Retrieval info: PRIVATE: WidthData NUMERIC "16" // Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0" // Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
@ -105,19 +157,21 @@ endmodule
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]" // Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0 // Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 // Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 // Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_data.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL ram_instr.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_data.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL ram_instr.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_data.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL ram_instr.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_data.bsf TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL ram_instr.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_data_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL ram_instr_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_data_bb.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL ram_instr_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf // Retrieval info: LIB_FILE: altera_mf