From 5ed70dabb0cbcbcc75ca7cdd9336681c2a88227b Mon Sep 17 00:00:00 2001 From: Kacper Date: Wed, 27 May 2020 11:10:13 +0100 Subject: [PATCH] Working on datapath --- CPUProject.bdf | 1175 +++++++++++++++++++++++----------- CPUProject.qsf | 8 +- CPUProject.qws | Bin 2478 -> 0 bytes DECODE.v | 32 + DECODE.v.bak | 20 + SM.bdf | 283 ++++++++ SM.bsf | 50 ++ ram_data.bsf | 19 +- ram_data.qip | 1 - ram_data.v | 23 +- ram_instr.bsf | 112 ++++ ram_instr.qip | 5 + ram_data_bb.v => ram_instr.v | 78 ++- 13 files changed, 1398 insertions(+), 408 deletions(-) delete mode 100644 CPUProject.qws create mode 100644 DECODE.v create mode 100644 DECODE.v.bak create mode 100644 SM.bdf create mode 100644 SM.bsf create mode 100644 ram_instr.bsf create mode 100644 ram_instr.qip rename ram_data_bb.v => ram_instr.v (69%) diff --git a/CPUProject.bdf b/CPUProject.bdf index 1a183d3..68acf1c 100644 --- a/CPUProject.bdf +++ b/CPUProject.bdf @@ -19,6 +19,22 @@ Intel and sold by Intel or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "graphic" (version "1.4")) +(pin + (input) + (rect 192 752 360 768) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "CLK" (rect 5 0 27 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) (symbol (rect 632 112 816 336) (text "mux_8x16" (rect 5 0 67 19)(font "Intel Clear" (font_size 8))) @@ -295,90 +311,6 @@ refer to the applicable agreement for further details. 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applicable agreement for further details. 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16) + (bus) +) +(connector + (text "CLK" (rect 514 -72 534 -55)(font "Intel Clear" )) + (pt 504 -56) + (pt 536 -56) +) +(connector + (pt 488 -72) + (pt 536 -72) + (bus) +) +(connector + (text "EXEC" (rect 514 -104 539 -87)(font "Intel Clear" )) + (pt 504 -88) + (pt 536 -88) +) +(connector + (pt 728 -88) + (pt 744 -88) + (bus) +) +(connector + (text "CLK" (rect 234 -48 254 -31)(font "Intel Clear" )) + (pt 224 -32) + (pt 256 -32) +) +(connector + (pt 488 -112) + (pt 488 -72) + (bus) +) +(connector + (pt 488 -72) + (pt 488 16) + (bus) +) +(connector + (pt 712 -56) + (pt 744 -56) + (bus) +) +(connector + (pt 472 -112) + (pt 488 -112) + (bus) +) +(connector + (text "instr[10..0]" (rect 882 160 931 177)(font "Intel Clear" )) + (pt 936 176) + (pt 872 176) + (bus) +) +(connector + (text "instr[15..0]" (rect 864 -88 913 -71)(font "Intel Clear" )) + (pt 856 -72) + (pt 872 -72) + (bus) +) +(connector + (text "EXEC" (rect 783 -28 800 -3)(font "Intel Clear" )(vertical)) + (pt 800 -32) + (pt 800 0) +) +(connector + (text "s3[2..0]" (rect 432 105 449 139)(font "Intel Clear" )(vertical)) + (pt 448 104) + (pt 448 592) + (bus) +) +(connector + (pt 448 592) + (pt 448 608) + (bus) +) +(connector + (text "s2[2..0]" (rect 448 105 465 139)(font "Intel Clear" )(vertical)) + (pt 464 104) + (pt 464 368) + (bus) +) +(connector + (pt 464 368) + (pt 464 384) + (bus) +) +(connector + (pt 592 128) + (pt 480 128) + (bus) +) +(connector + (text "s1[2..0]" (rect 464 107 481 141)(font "Intel Clear" )(vertical)) + (pt 480 128) + (pt 480 104) + (bus) +) +(connector + (pt 208 144) + (pt 504 144) + (bus) +) +(connector + (pt 256 -80) + (pt 208 -80) + (bus) +) +(connector + (pt 208 144) + (pt 208 -80) + (bus) +) +(connector + (text "RAMd_en" (rect 890 224 937 241)(font "Intel Clear" )) + (pt 936 240) + (pt 880 240) +) +(connector + (text "CLK" (rect 890 208 910 225)(font "Intel Clear" )) + (pt 936 224) + (pt 880 224) +) +(connector + (text "RAMd_wren" (rect 882 144 941 161)(font "Intel Clear" )) + (pt 936 160) + (pt 880 160) +) +(connector + (pt 872 -72) + (pt 872 176) + (bus) +) +(connector + (pt 504 192) + (pt 504 416) + (bus) +) +(connector + (pt 520 208) + (pt 520 432) + (bus) +) +(connector + (pt 536 224) + (pt 536 448) + (bus) +) +(connector + (pt 552 240) + (pt 552 464) + (bus) +) +(connector + (pt 568 256) + (pt 568 480) + (bus) +) +(connector + (pt 584 272) + (pt 584 496) + (bus) +) +(connector + (pt 600 288) + (pt 600 512) + (bus) +) +(connector + (pt 616 304) + (pt 616 528) + (bus) +) +(connector + (text "R0_en" (rect 186 192 216 209)(font "Intel Clear" )) + (pt 224 208) + (pt 176 208) +) +(connector + (text "CLK" (rect 186 176 206 193)(font "Intel Clear" )) + (pt 224 192) + (pt 176 192) +) +(connector + (text "R0_count" (rect 186 224 230 241)(font "Intel Clear" )) + (pt 224 240) + (pt 176 240) +) +(connector + (text "R1_en" (rect 186 256 216 273)(font "Intel Clear" )) + (pt 224 272) + (pt 176 272) +) +(connector + (text "R2_en" (rect 186 288 216 305)(font "Intel Clear" )) + (pt 224 304) + (pt 176 304) +) +(connector + (text "R3_en" (rect 186 320 216 337)(font "Intel Clear" )) + (pt 224 336) + (pt 176 336) +) +(connector + (text "R4_en" (rect 186 352 216 369)(font "Intel Clear" )) + (pt 224 368) + (pt 176 368) +) +(connector + (text "R5_en" (rect 186 384 216 401)(font "Intel Clear" )) + (pt 224 400) + (pt 176 400) +) +(connector + (text "R6_en" (rect 186 416 216 433)(font "Intel Clear" )) + (pt 224 432) + (pt 176 432) +) +(connector + (text "R7_en" (rect 186 448 216 465)(font "Intel Clear" )) + (pt 224 464) + (pt 176 464) +) +(connector + (pt 160 224) + (pt 224 224) + (bus) +) +(connector + (pt 160 256) + (pt 224 256) + (bus) +) +(connector + (pt 160 288) + (pt 224 288) + (bus) +) +(connector + (pt 160 320) + (pt 224 320) + (bus) +) +(connector + (pt 160 352) + (pt 224 352) + (bus) +) +(connector + (pt 160 384) + (pt 224 384) + (bus) +) +(connector + (pt 160 416) + (pt 224 416) + (bus) +) +(connector + (pt 160 448) + (pt 224 448) + (bus) +) +(connector + (pt 504 144) + (pt 504 192) + (bus) +) (connector (pt 432 192) (pt 504 192) @@ -904,6 +1523,11 @@ refer to the applicable agreement for further details. (pt 632 272) (bus) ) +(connector + (pt 160 256) + (pt 160 288) + (bus) +) (connector (pt 432 288) (pt 600 288) @@ -915,6 +1539,7 @@ refer to the applicable agreement for further details. (bus) ) (connector + (text " " (rect 549 288 551 305)(font "Intel Clear" )) (pt 432 304) (pt 616 304) (bus) @@ -924,128 +1549,6 @@ refer to the applicable agreement for further details. (pt 632 304) (bus) ) -(connector - (text "Rs2[15..0]" (rect 826 352 873 369)(font "Intel Clear" )) - (pt 816 368) - (pt 896 368) - (bus) -) -(connector - (text "Rd[15..0]" (rect 826 576 868 593)(font "Intel Clear" )) - (pt 816 592) - (pt 864 592) - (bus) -) -(connector - (pt 864 592) - (pt 864 392) - (bus) -) -(connector - (pt 896 392) - (pt 864 392) - (bus) -) -(connector - (text "R0_en" (rect 186 192 216 209)(font "Intel Clear" )) - (pt 224 208) - (pt 176 208) -) -(connector - (text "CLK" (rect 186 176 206 193)(font "Intel Clear" )) - (pt 224 192) - (pt 176 192) -) -(connector - (text "R0_count" (rect 186 224 230 241)(font "Intel Clear" )) - (pt 224 240) - (pt 176 240) -) -(connector - (text "R1_en" (rect 186 256 216 273)(font "Intel Clear" )) - (pt 224 272) - (pt 176 272) -) -(connector - (text "R2_en" (rect 186 288 216 305)(font "Intel Clear" )) - (pt 224 304) - (pt 176 304) -) -(connector - (text "R3_en" (rect 186 320 216 337)(font "Intel Clear" )) - (pt 224 336) - (pt 176 336) -) -(connector - (text "R4_en" (rect 186 352 216 369)(font "Intel Clear" )) - (pt 224 368) - (pt 176 368) -) -(connector - (text "R5_en" (rect 186 384 216 401)(font "Intel Clear" )) - (pt 224 400) - (pt 176 400) -) -(connector - (text "R6_en" (rect 186 416 216 433)(font "Intel Clear" )) - (pt 224 432) - (pt 176 432) -) -(connector - (text "R7_en" (rect 186 448 216 465)(font "Intel Clear" )) - (pt 224 464) - (pt 176 464) -) -(connector - (pt 224 224) - (pt 160 224) - (bus) -) -(connector - (pt 224 256) - (pt 160 256) - (bus) -) -(connector - (pt 224 288) - (pt 160 288) - (bus) -) -(connector - (pt 224 320) - (pt 160 320) - (bus) -) -(connector - (pt 224 352) - (pt 160 352) - (bus) -) -(connector - (pt 224 384) - (pt 160 384) - (bus) -) -(connector - (pt 224 416) - (pt 160 416) - (bus) -) -(connector - (pt 224 448) - (pt 160 448) - (bus) -) -(connector - (pt 160 224) - (pt 160 256) - (bus) -) -(connector - (pt 160 256) - (pt 160 288) - (bus) -) (connector (pt 160 288) (pt 160 320) @@ -1071,150 +1574,65 @@ refer to the applicable agreement for further details. (pt 160 448) (bus) ) -(connector - (text "s3[2]" (rect 474 608 497 625)(font "Intel Clear" )) - (pt 632 624) - (pt 448 624) -) -(connector - (text "s3[0]" (rect 474 576 497 593)(font "Intel Clear" )) - (pt 448 592) - (pt 632 592) -) -(connector - (text "s3[2..0]" (rect 432 113 449 147)(font "Intel Clear" )(vertical)) - (pt 448 112) - (pt 448 592) - (bus) -) -(connector - (text "s3[1]" (rect 474 592 497 609)(font "Intel Clear" )) - (pt 448 608) - (pt 632 608) -) -(connector - (pt 448 592) - (pt 448 608) - (bus) -) -(connector - (pt 448 608) - (pt 448 624) - (bus) -) (connector (pt 160 448) (pt 160 792) (bus) ) (connector - (pt 1152 144) - (pt 1160 144) + (pt 160 224) + (pt 160 256) (bus) ) (connector - (pt 1160 304) - (pt 1168 304) - (bus) + (text "CLK" (rect 236 40 256 57)(font "Intel Clear" )) + (pt 256 56) + (pt 224 56) ) (connector - (pt 1160 144) - (pt 1160 304) - (bus) + (text "EXEC" (rect 386 56 411 73)(font "Intel Clear" )) + (pt 376 72) + (pt 416 72) ) (connector - (pt 1288 792) - (pt 1288 320) - (bus) + (text "FETCH" (rect 386 40 417 57)(font "Intel Clear" )) + (pt 376 56) + (pt 416 56) ) (connector - (pt 1280 320) - (pt 1288 320) - (bus) + (text "CLK" (rect 370 744 390 761)(font "Intel Clear" )) + (pt 360 760) + (pt 400 760) ) (connector - (pt 160 792) - (pt 1288 792) - (bus) -) -(connector - (text "rd_wren" (rect 898 144 936 161)(font "Intel Clear" )) - (pt 888 160) - (pt 936 160) -) -(connector - (text "CLK" (rect 898 208 918 225)(font "Intel Clear" )) - (pt 888 224) - (pt 936 224) -) -(connector - (pt 936 176) - (pt 872 176) - (bus) -) -(connector - (pt 856 144) - (pt 856 344) - (bus) -) -(connector - (pt 896 344) - (pt 856 344) - (bus) -) -(connector - (text "Rs1[15..0]" (rect 826 128 873 145)(font "Intel Clear" )) - (pt 816 144) - (pt 856 144) - (bus) -) -(connector - (pt 856 144) - (pt 936 144) - (bus) -) -(connector - (pt 504 192) - (pt 504 416) - (bus) -) -(connector - (text "R0_out[15..0]" (rect 488 128 505 191)(font "Intel Clear" )(vertical)) - (pt 504 112) - (pt 504 192) - (bus) -) -(connector - (text "s4" (rect 1208 373 1225 383)(font "Intel Clear" )(vertical)) - (pt 1224 360) - (pt 1224 392) -) -(connector - (text "rd_addr[10..0]" (rect 854 133 871 199)(font "Intel Clear" )(vertical)) - (pt 872 176) - (pt 872 112) - (bus) + (text "RAMi_en" (rect 216 -32 259 -15)(font "Intel Clear" )) + (pt 256 -16) + (pt 216 -16) ) (junction (pt 504 416)) (junction (pt 504 192)) (junction (pt 520 432)) -(junction (pt 520 208)) (junction (pt 536 448)) -(junction (pt 536 224)) (junction (pt 552 464)) -(junction (pt 552 240)) (junction (pt 568 480)) -(junction (pt 568 256)) (junction (pt 584 496)) -(junction (pt 584 272)) (junction (pt 600 512)) -(junction (pt 600 288)) (junction (pt 616 528)) -(junction (pt 616 304)) (junction (pt 592 160)) (junction (pt 464 368)) (junction (pt 464 384)) (junction (pt 592 144)) +(junction (pt 448 592)) +(junction (pt 448 608)) +(junction (pt 856 144)) +(junction (pt 488 -72)) +(junction (pt 520 208)) +(junction (pt 536 224)) +(junction (pt 552 240)) +(junction (pt 568 256)) +(junction (pt 584 272)) +(junction (pt 600 288)) +(junction (pt 616 304)) (junction (pt 160 256)) (junction (pt 160 288)) (junction (pt 160 320)) @@ -1222,6 +1640,3 @@ refer to the applicable agreement for further details. (junction (pt 160 384)) (junction (pt 160 416)) (junction (pt 160 448)) -(junction (pt 448 592)) -(junction (pt 448 608)) -(junction (pt 856 144)) diff --git a/CPUProject.qsf b/CPUProject.qsf index 56a9a15..cbd2662 100644 --- a/CPUProject.qsf +++ b/CPUProject.qsf @@ -38,7 +38,7 @@ set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name DEVICE AUTO -set_global_assignment -name TOP_LEVEL_ENTITY CPUProject +set_global_assignment -name TOP_LEVEL_ENTITY test set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020" set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition" @@ -49,7 +49,13 @@ set_global_assignment -name BDF_FILE CPUProject.bdf set_global_assignment -name BDF_FILE reg_file.bdf set_global_assignment -name BDF_FILE mux_8x16.bdf set_global_assignment -name QIP_FILE ram_data.qip +set_global_assignment -name QIP_FILE ram_instr.qip +set_global_assignment -name BDF_FILE SM.bdf +set_global_assignment -name VERILOG_FILE DECODE.v +set_global_assignment -name MIF_FILE test.mif +set_global_assignment -name BDF_FILE test.bdf set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/CPUProject.qws b/CPUProject.qws deleted file mode 100644 index bdc0a5093e17a0e5bfbf7fc13c07b8a198c28778..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2478 zcmeH|y-piJ5Xb*_0f{oD3l}LOWJNN<4k1n#fkKr6MM+KkaW=-ET#P_M7Q6!QkcKpQ z15%|*la`8(DsK=c&Tp18G6!}f{Z*JygN`sM9U3q;_M_bxgOQC9T zZO)1cPDKNtc;fD35lT^_fEwsQWjp9tz$mOCQoNTcr8A zAM=eEbNr~@1*voF*lYfZn|O6fXhb!fCDTw5b(bHjCsUnFKR|pL zRi>{bQ;Z)0zTSfL#RLQOFSK%sPxGMV?oniFe>OarTi2pw-nqAGk+v7iKYNU>T K1d%#!#P~l?g_$(~ diff --git a/DECODE.v b/DECODE.v new file mode 100644 index 0000000..c2e193b --- /dev/null +++ b/DECODE.v @@ -0,0 +1,32 @@ +module DECODE +( + input [15:0] instr, + input FETCH, + input EXEC, + input COND_result, + output R0_count, + output R1_en, + output R2_en, + output R3_en, + output R4_en, + output R5_en, + output R6_en, + output R7_en, + output [2:0] s1, + output [2:0] s2, + output [2:0] s3, + output s4, + output RAMd_wren, + output RAMd_en, + output RAMi_en +); + wire msb, ls, [reg_ls, addr, op, Rd, Rs1, Rs2; + assign msb = instr[15]; //MSB of the instruction word + assign ls = instr[14]; //LOAD or STORE bit + assign reg_ls = instr + + wire LOAD, STORE, UJMP, JMP, AND, OR, XOR, NOT, NND, NOR, XNR, MOV, ADD, ADC, ADO, SUB, SBC, SBO, MUL, MLA, MLS, MRT, LSL, LSR, ASR, ROR, RRC, NOP, STP; + assign LOAD = + +endmodule + \ No newline at end of file diff --git a/DECODE.v.bak b/DECODE.v.bak new file mode 100644 index 0000000..b453c72 --- /dev/null +++ b/DECODE.v.bak @@ -0,0 +1,20 @@ +module DECODE +( + input [15:0]instr, + input FETCH, + input EXEC, + output R0_count, + output R1_en, + output R2_en, + output R3_en, + output R4_en, + output R5_en, + output R6_en, + output R7_en, + output [2:0]s1, + output [2:0]s2, + output [2:0]s3, + output s4, + output RAMd_wren, + output RAMd_en, + \ No newline at end of file diff --git a/SM.bdf b/SM.bdf new file mode 100644 index 0000000..b687e5a --- /dev/null +++ b/SM.bdf @@ -0,0 +1,283 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 272 296 440 312) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "CLK" (rect 5 0 27 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (output) + (rect 736 192 912 208) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "FETCH" (rect 90 0 126 12)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(pin + (output) + (rect 736 224 912 240) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "EXEC" (rect 90 0 115 17)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(symbol + (rect 448 216 624 360) + (text "LPM_FF" (rect 19 0 78 16)(font "Arial" (font_size 10))) + (text "STATE" (rect 3 133 41 147)(font "Arial" (font_size 8))) + (port + (pt 88 144) + (input) + (text "aclr" (rect 80 113 101 127)(font "Arial" (font_size 8))) + (text "aclr" (rect 80 113 101 127)(font "Arial" (font_size 8))) + (line (pt 88 144)(pt 88 128)) + (unused) + ) + (port + (pt 0 24) + (input) + (text "aload" (rect 20 17 50 31)(font "Arial" (font_size 8))) + (text "aload" (rect 20 17 50 31)(font "Arial" (font_size 8))) + (line (pt 0 24)(pt 16 24)) + (unused) + ) + (port + (pt 88 0) + (input) + (text "aset" (rect 79 17 103 31)(font "Arial" (font_size 8))) + (text "aset" (rect 79 17 103 31)(font "Arial" (font_size 8))) + (line (pt 88 16)(pt 88 0)) + (unused) + ) + (port + (pt 0 88) + (input) + (text "clock" (rect 20 81 49 95)(font "Arial" (font_size 8))(invisible)) + (text "clock" (rect 20 81 49 95)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 88)(pt 16 88)) + ) + (port + (pt 0 72) + (input) + (text "data[LPM_WIDTH-1..0]" (rect 20 63 146 77)(font "Arial" (font_size 8))) + (text "data[]" (rect 20 63 51 77)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 3)) + ) + (port + (pt 0 104) + (input) + (text "enable" (rect 20 97 57 111)(font "Arial" (font_size 8))) + (text "enable" (rect 20 97 57 111)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 16 104)) + (unused) + ) + (port + (pt 0 120) + (input) + (text "sclr" (rect 20 113 41 127)(font "Arial" (font_size 8))) + (text "sclr" (rect 20 113 41 127)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 16 120)) + (unused) + ) + (port + (pt 0 56) + (input) + (text "sload" (rect 20 49 50 63)(font "Arial" (font_size 8))) + (text "sload" (rect 20 49 50 63)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)) + (unused) + ) + (port + (pt 0 40) + (input) + (text "sset" (rect 20 33 44 47)(font "Arial" (font_size 8))) + (text "sset" (rect 20 33 44 47)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 16 40)) + (unused) + ) + (port + (pt 176 88) + (output) + (text "q[LPM_WIDTH-1..0]" (rect 144 81 252 95)(font "Arial" (font_size 8))) + (text "q[]" (rect 144 81 158 95)(font "Arial" (font_size 8))) + (line (pt 160 88)(pt 176 88)(line_width 3)) + ) + (parameter + "LPM_AVALUE" + "" + "Unsigned value associated with the aset port" + ) + (parameter + "LPM_FFTYPE" + "\"DFF\"" + "Selects behavior as DFF or TFF" + "\"DFF\"" "\"TFF\"" + ) + (parameter + "LPM_SVALUE" + "" + "Unsigned value associated with the sset port" + ) + (parameter + "LPM_WIDTH" + "1" + "Width of I/O, any integer > 0" + " 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64" + ) + (drawing + (line (pt 16 16)(pt 160 16)) + (line (pt 16 128)(pt 160 128)) + (line (pt 160 128)(pt 160 16)) + (line (pt 16 128)(pt 16 16)) + (line (pt 16 80)(pt 24 88)) + (line (pt 24 88)(pt 16 96)) + ) + (annotation_block (parameter)(rect 624 216 648 232)) +) +(symbol + (rect 512 168 560 200) + (text "NOT" (rect 27 0 47 10)(font "Arial" (font_size 6))) + (text "NOT1" (rect 17 21 45 33)(font "Arial" )) + (port + (pt 48 16) + (input) + (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) + (text "IN" (rect 35 7 46 19)(font "Courier New" (bold))(invisible)) + (line (pt 48 16)(pt 35 16)) + ) + (port + (pt 0 16) + (output) + (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect -1 7 16 19)(font "Courier New" (bold))(invisible)) + (line (pt 9 16)(pt 0 16)) + ) + (drawing + (line (pt 35 25)(pt 35 7)) + (line (pt 35 7)(pt 17 16)) + (line (pt 35 25)(pt 17 16)) + (circle (rect 9 12 17 20)) + ) + (flipy) +) +(symbol + (rect 680 184 728 216) + (text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6))) + (text "NOT2" (rect 3 21 31 33)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) + (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 13 16)) + ) + (port + (pt 48 16) + (output) + (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible)) + (line (pt 39 16)(pt 48 16)) + ) + (drawing + (line (pt 13 25)(pt 13 7)) + (line (pt 13 7)(pt 31 16)) + (line (pt 13 25)(pt 31 16)) + (circle (rect 31 12 39 20)) + ) +) +(connector + (pt 448 304) + (pt 440 304) +) +(connector + (pt 624 304) + (pt 664 304) +) +(connector + (pt 560 184) + (pt 664 184) +) +(connector + (pt 512 184) + (pt 432 184) +) +(connector + (pt 432 184) + (pt 432 288) +) +(connector + (pt 432 288) + (pt 448 288) +) +(connector + (pt 680 200) + (pt 664 200) +) +(connector + (pt 664 184) + (pt 664 200) +) +(connector + (pt 728 200) + (pt 736 200) +) +(connector + (pt 736 232) + (pt 664 232) +) +(connector + (pt 664 200) + (pt 664 232) +) +(connector + (pt 664 232) + (pt 664 304) +) +(junction (pt 664 200)) +(junction (pt 664 232)) diff --git a/SM.bsf b/SM.bsf new file mode 100644 index 0000000..69de486 --- /dev/null +++ b/SM.bsf @@ -0,0 +1,50 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 136 112) + (text "SM" (rect 5 0 23 19)(font "Intel Clear" (font_size 8))) + (text "inst" (rect 8 75 24 92)(font "Intel Clear" )) + (port + (pt 0 32) + (input) + (text "CLK" (rect 0 0 23 19)(font "Intel Clear" (font_size 8))) + (text "CLK" (rect 21 27 44 46)(font "Intel Clear" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 120 32) + (output) + (text "FETCH" (rect 0 0 40 19)(font "Intel Clear" (font_size 8))) + (text "FETCH" (rect 59 27 99 46)(font "Intel Clear" (font_size 8))) + (line (pt 120 32)(pt 104 32)) + ) + (port + (pt 120 48) + (output) + (text "EXEC" (rect 0 0 30 19)(font "Intel Clear" (font_size 8))) + (text "EXEC" (rect 69 43 99 62)(font "Intel Clear" (font_size 8))) + (line (pt 120 48)(pt 104 48)) + ) + (drawing + (rectangle (rect 16 16 104 80)) + ) +) diff --git a/ram_data.bsf b/ram_data.bsf index b71803c..625323e 100644 --- a/ram_data.bsf +++ b/ram_data.bsf @@ -20,9 +20,9 @@ refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol - (rect 0 0 216 128) + (rect 0 0 216 144) (text "ram_data" (rect 81 0 144 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 112 25 124)(font "Arial" )) + (text "inst" (rect 8 128 25 140)(font "Arial" )) (port (pt 0 32) (input) @@ -51,6 +51,13 @@ refer to the applicable agreement for further details. (text "clock" (rect 4 98 27 111)(font "Arial" (font_size 8))) (line (pt 0 112)(pt 80 112)) ) + (port + (pt 0 128) + (input) + (text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clken" (rect 4 114 27 127)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 16 128)) + ) (port (pt 216 32) (output) @@ -61,7 +68,7 @@ refer to the applicable agreement for further details. (drawing (text "16 bits" (rect 109 24 194 159)(font "Arial" )(vertical)) (text "2048 words" (rect 120 12 214 177)(font "Arial" )(vertical)) - (text "Block type: AUTO" (rect 48 114 170 239)(font "Arial" )) + (text "Block type: AUTO" (rect 48 130 170 271)(font "Arial" )) (line (pt 104 24)(pt 136 24)) (line (pt 136 24)(pt 136 96)) (line (pt 136 96)(pt 104 96)) @@ -94,9 +101,9 @@ refer to the applicable agreement for further details. (line (pt 96 64)(pt 104 64)(line_width 3)) (line (pt 80 112)(pt 80 36)) (line (pt 0 0)(pt 217 0)) - (line (pt 217 0)(pt 217 130)) - (line (pt 0 130)(pt 217 130)) - (line (pt 0 0)(pt 0 130)) + (line (pt 217 0)(pt 217 146)) + (line (pt 0 146)(pt 217 146)) + (line (pt 0 0)(pt 0 146)) (line (pt 0 0)(pt 0 0)) (line (pt 0 0)(pt 0 0)) (line (pt 0 0)(pt 0 0)) diff --git a/ram_data.qip b/ram_data.qip index ae73c97..be8b35f 100644 --- a/ram_data.qip +++ b/ram_data.qip @@ -3,4 +3,3 @@ set_global_assignment -name IP_TOOL_VERSION "18.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram_data.v"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_data.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_data_bb.v"] diff --git a/ram_data.v b/ram_data.v index 092b51d..41e23a4 100644 --- a/ram_data.v +++ b/ram_data.v @@ -38,12 +38,14 @@ // synopsys translate_on module ram_data ( address, + clken, clock, data, wren, q); input [10:0] address; + input clken; input clock; input [15:0] data; input wren; @@ -51,6 +53,7 @@ module ram_data ( `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif + tri1 clken; tri1 clock; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on @@ -62,6 +65,7 @@ module ram_data ( altsyncram altsyncram_component ( .address_a (address), .clock0 (clock), + .clocken0 (clken), .data_a (data), .wren_a (wren), .q_a (sub_wire0), @@ -73,7 +77,6 @@ module ram_data ( .byteena_a (1'b1), .byteena_b (1'b1), .clock1 (1'b1), - .clocken0 (1'b1), .clocken1 (1'b1), .clocken2 (1'b1), .clocken3 (1'b1), @@ -84,8 +87,9 @@ module ram_data ( .rden_b (1'b1), .wren_b (1'b0)); defparam - altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_a = "NORMAL", altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "test.mif", altsyncram_component.intended_device_family = "Cyclone IV E", altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", altsyncram_component.lpm_type = "altsyncram", @@ -112,10 +116,10 @@ endmodule // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "1" // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" @@ -124,7 +128,7 @@ endmodule // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: MIFfilename STRING "test.mif" // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" @@ -139,8 +143,9 @@ endmodule // Retrieval info: PRIVATE: WidthData NUMERIC "16" // Retrieval info: PRIVATE: rden NUMERIC "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "test.mif" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" @@ -154,12 +159,14 @@ endmodule // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]" +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" // Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 // Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 // Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 @@ -168,5 +175,5 @@ endmodule // Retrieval info: GEN_FILE: TYPE_NORMAL ram_data.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL ram_data.bsf TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL ram_data_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram_data_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_data_bb.v FALSE // Retrieval info: LIB_FILE: altera_mf diff --git a/ram_instr.bsf b/ram_instr.bsf new file mode 100644 index 0000000..27c4f04 --- /dev/null +++ b/ram_instr.bsf @@ -0,0 +1,112 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 216 144) + (text "ram_instr" (rect 81 0 144 16)(font "Arial" (font_size 10))) + (text "inst" (rect 8 128 25 140)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[15..0]" (rect 4 18 53 31)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 88 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "wren" (rect 0 0 30 14)(font "Arial" (font_size 8))) + (text "wren" (rect 4 34 28 47)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 88 48)) + ) + (port + (pt 0 64) + (input) + (text "address[10..0]" (rect 0 0 82 14)(font "Arial" (font_size 8))) + (text "address[10..0]" (rect 4 50 72 63)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 88 64)(line_width 3)) + ) + (port + (pt 0 112) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 4 98 27 111)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 80 112)) + ) + (port + (pt 0 128) + (input) + (text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clken" (rect 4 114 27 127)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 16 128)) + ) + (port + (pt 216 32) + (output) + (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[15..0]" (rect 177 18 211 31)(font "Arial" (font_size 8))) + (line (pt 216 32)(pt 136 32)(line_width 3)) + ) + (drawing + (text "16 bits" (rect 109 24 194 159)(font "Arial" )(vertical)) + (text "2048 words" (rect 120 12 214 177)(font "Arial" )(vertical)) + (text "Block type: AUTO" (rect 48 130 170 271)(font "Arial" )) + (line (pt 104 24)(pt 136 24)) + (line (pt 136 24)(pt 136 96)) + (line (pt 136 96)(pt 104 96)) + (line (pt 104 96)(pt 104 24)) + (line (pt 118 58)(pt 123 63)) + (line (pt 118 62)(pt 123 57)) + (line (pt 88 27)(pt 96 27)) + (line (pt 96 27)(pt 96 39)) + (line (pt 96 39)(pt 88 39)) + (line (pt 88 39)(pt 88 27)) + (line (pt 88 34)(pt 90 36)) + (line (pt 90 36)(pt 88 38)) + (line (pt 80 36)(pt 88 36)) + (line (pt 96 32)(pt 104 32)(line_width 3)) + (line (pt 88 43)(pt 96 43)) + (line (pt 96 43)(pt 96 55)) + (line (pt 96 55)(pt 88 55)) + (line (pt 88 55)(pt 88 43)) + (line (pt 88 50)(pt 90 52)) + (line (pt 90 52)(pt 88 54)) + (line (pt 80 52)(pt 88 52)) + (line (pt 96 48)(pt 104 48)) + (line (pt 88 59)(pt 96 59)) + (line (pt 96 59)(pt 96 71)) + (line (pt 96 71)(pt 88 71)) + (line (pt 88 71)(pt 88 59)) + (line (pt 88 66)(pt 90 68)) + (line (pt 90 68)(pt 88 70)) + (line (pt 80 68)(pt 88 68)) + (line (pt 96 64)(pt 104 64)(line_width 3)) + (line (pt 80 112)(pt 80 36)) + (line (pt 0 0)(pt 217 0)) + (line (pt 217 0)(pt 217 146)) + (line (pt 0 146)(pt 217 146)) + (line (pt 0 0)(pt 0 146)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + ) +) diff --git a/ram_instr.qip b/ram_instr.qip new file mode 100644 index 0000000..5027280 --- /dev/null +++ b/ram_instr.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram_instr.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_instr.bsf"] diff --git a/ram_data_bb.v b/ram_instr.v similarity index 69% rename from ram_data_bb.v rename to ram_instr.v index 64372ba..a52ca4c 100644 --- a/ram_data_bb.v +++ b/ram_instr.v @@ -1,10 +1,10 @@ -// megafunction wizard: %RAM: 1-PORT%VBB% +// megafunction wizard: %RAM: 1-PORT% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ -// File Name: ram_data.v +// File Name: ram_instr.v // Megafunction Name(s): // altsyncram // @@ -17,6 +17,7 @@ // 18.1.0 Build 625 09/12/2018 SJ Standard Edition // ************************************************************ + //Copyright (C) 2018 Intel Corporation. All rights reserved. //Your use of Intel Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic @@ -31,14 +32,20 @@ //Intel and sold by Intel or its authorized distributors. Please //refer to the applicable agreement for further details. -module ram_data ( + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ram_instr ( address, + clken, clock, data, wren, q); input [10:0] address; + input clken; input clock; input [15:0] data; input wren; @@ -46,11 +53,56 @@ module ram_data ( `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif + tri1 clken; tri1 clock; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .clocken0 (clken), + .data_a (data), + .wren_a (wren), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "NORMAL", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone IV E", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 2048, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 11, + altsyncram_component.width_a = 16, + altsyncram_component.width_byteena_a = 1; + + endmodule // ============================================================ @@ -64,9 +116,9 @@ endmodule // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "1" // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" @@ -90,7 +142,7 @@ endmodule // Retrieval info: PRIVATE: WidthData NUMERIC "16" // Retrieval info: PRIVATE: rden NUMERIC "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" @@ -105,19 +157,21 @@ endmodule // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]" +// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" // Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 // Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 // Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL ram_data.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram_data.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram_data.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram_data.bsf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram_data_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram_data_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_instr.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_instr.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_instr.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_instr.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_instr_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram_instr_bb.v FALSE // Retrieval info: LIB_FILE: altera_mf