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Modified Test Program to add LDR and STR

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Also fixed logic within decoder for LDR and STR
This commit is contained in:
Aadi Desai 2020-06-10 15:51:51 +01:00
parent 719c9ede2b
commit 4688a56452
6 changed files with 379 additions and 316 deletions
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CPUProject.bdf
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@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 2018 Intel Corporation. All rights reserved. Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic and other software and tools, and any partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
(including device programming or simulation files), and any (including device programming or simulation files), and any
associated documentation or information are expressly subject associated documentation or information are expressly subject
@ -16,7 +16,8 @@ the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details. refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/ */
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)
(port
(pt 0 32)
(input)
(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 44 32)(line_width 3))
)
(port
(pt 112 48)
(output)
(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
(line (pt 68 48)(pt 112 48)(line_width 3))
)
(parameter
"WIDTH"
"16"
"Width of I/O, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
)
(drawing
(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
(line (pt 68 64)(pt 68 32))
(line (pt 44 80)(pt 44 16))
(line (pt 44 16)(pt 68 32))
(line (pt 44 80)(pt 68 64))
)
(annotation_block (parameter)(rect 1368 272 1400 288))
)
(symbol
(rect 968 24 1080 112)
(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
(text "MUX5" (rect 3 77 32 94)(font "Intel Clear" ))
(port
(pt 0 64)
(input)
(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 44 64)(line_width 3))
)
(port
(pt 56 88)
(input)
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(line (pt 56 88)(pt 56 72))
)
(port
(pt 0 32)
(input)
(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 44 32)(line_width 3))
)
(port
(pt 112 48)
(output)
(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
(line (pt 68 48)(pt 112 48)(line_width 3))
)
(parameter
"WIDTH"
"11"
"Width of I/O, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
)
(drawing
(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
(line (pt 68 64)(pt 68 32))
(line (pt 44 80)(pt 44 16))
(line (pt 44 16)(pt 68 32))
(line (pt 44 80)(pt 68 64))
)
(annotation_block (parameter)(rect 1080 24 1112 48))
)
(symbol
(rect 1168 -184 1376 216)
(text "DECODE" (rect 5 0 52 12)(font "Arial" )) (text "DECODE" (rect 5 0 52 12)(font "Arial" ))
(text "DECODE" (rect 8 384 55 396)(font "Arial" )) (text "DECODE" (rect 8 384 55 396)(font "Arial" ))
(port (port
@ -2643,12 +2660,6 @@ refer to the applicable agreement for further details.
(pt 272 88) (pt 272 88)
(pt 304 88) (pt 304 88)
) )
(connector
(text "RAMd_out[15..0]" (rect 1450 280 1530 297)(font "Intel Clear" ))
(pt 1512 296)
(pt 1440 296)
(bus)
)
(connector (connector
(text "jumpflags[7..0]" (rect 1448 344 1518 361)(font "Intel Clear" )) (text "jumpflags[7..0]" (rect 1448 344 1518 361)(font "Intel Clear" ))
(pt 1512 360) (pt 1512 360)
@ -2820,11 +2831,6 @@ refer to the applicable agreement for further details.
(pt 1088 152) (pt 1088 152)
(bus) (bus)
) )
(connector
(pt 1088 152)
(pt 872 152)
(bus)
)
(connector (connector
(pt 872 224) (pt 872 224)
(pt 872 152) (pt 872 152)
@ -2846,161 +2852,12 @@ refer to the applicable agreement for further details.
(pt 1160 192) (pt 1160 192)
(bus) (bus)
) )
(connector
(text "R0_count" (rect 1386 -168 1430 -151)(font "Intel Clear" ))
(pt 1376 -152)
(pt 1424 -152)
)
(connector
(text "R0_en" (rect 1386 -152 1416 -135)(font "Intel Clear" ))
(pt 1376 -136)
(pt 1424 -136)
)
(connector
(text "R1_en" (rect 1386 -136 1416 -119)(font "Intel Clear" ))
(pt 1376 -120)
(pt 1424 -120)
)
(connector
(text "R2_en" (rect 1386 -120 1416 -103)(font "Intel Clear" ))
(pt 1376 -104)
(pt 1424 -104)
)
(connector
(text "R3_en" (rect 1386 -104 1416 -87)(font "Intel Clear" ))
(pt 1376 -88)
(pt 1424 -88)
)
(connector
(text "R4_en" (rect 1386 -88 1416 -71)(font "Intel Clear" ))
(pt 1376 -72)
(pt 1424 -72)
)
(connector
(text "R5_en" (rect 1386 -72 1416 -55)(font "Intel Clear" ))
(pt 1376 -56)
(pt 1424 -56)
)
(connector
(text "R6_en" (rect 1386 -56 1416 -39)(font "Intel Clear" ))
(pt 1376 -40)
(pt 1424 -40)
)
(connector
(text "R7_en" (rect 1386 -40 1416 -23)(font "Intel Clear" ))
(pt 1376 -24)
(pt 1424 -24)
)
(connector
(text "s1[2..0]" (rect 1386 -24 1420 -7)(font "Intel Clear" ))
(pt 1376 -8)
(pt 1424 -8)
(bus)
)
(connector
(text "s2[2..0]" (rect 1386 -8 1420 9)(font "Intel Clear" ))
(pt 1376 8)
(pt 1424 8)
(bus)
)
(connector
(text "s3[2..0]" (rect 1386 8 1420 25)(font "Intel Clear" ))
(pt 1376 24)
(pt 1424 24)
(bus)
)
(connector
(text "RAMd_en" (rect 1386 56 1433 73)(font "Intel Clear" ))
(pt 1376 72)
(pt 1424 72)
)
(connector
(text "RAMi_en" (rect 1386 72 1429 89)(font "Intel Clear" ))
(pt 1376 88)
(pt 1424 88)
)
(connector
(text "E2" (rect 1386 104 1397 121)(font "Intel Clear" ))
(pt 1376 120)
(pt 1424 120)
)
(connector
(text "stack_en" (rect 1386 120 1428 137)(font "Intel Clear" ))
(pt 1376 136)
(pt 1424 136)
)
(connector
(text "stack_rst" (rect 1386 136 1428 153)(font "Intel Clear" ))
(pt 1376 152)
(pt 1424 152)
)
(connector
(text "stack_rw" (rect 1386 152 1428 169)(font "Intel Clear" ))
(pt 1376 168)
(pt 1424 168)
)
(connector
(text "EXEC1" (rect 1138 -136 1169 -119)(font "Intel Clear" ))
(pt 1128 -120)
(pt 1168 -120)
)
(connector
(text "EXEC2" (rect 1138 -120 1169 -103)(font "Intel Clear" ))
(pt 1128 -104)
(pt 1168 -104)
)
(connector
(text "COND" (rect 1138 -104 1167 -87)(font "Intel Clear" ))
(pt 1128 -88)
(pt 1168 -88)
)
(connector
(text "FETCH" (rect 1138 -152 1169 -135)(font "Intel Clear" ))
(pt 1168 -136)
(pt 1128 -136)
)
(connector
(text "instr[15..0]" (rect 882 -168 931 -151)(font "Intel Clear" ))
(pt 872 -152)
(pt 1168 -152)
(bus)
)
(connector
(pt 1160 192)
(pt 1160 304)
(bus)
)
(connector (connector
(text "RAMd_out[15..0]" (rect 1178 288 1258 305)(font "Intel Clear" )) (text "RAMd_out[15..0]" (rect 1178 288 1258 305)(font "Intel Clear" ))
(pt 1256 304) (pt 1256 304)
(pt 1160 304) (pt 1160 304)
(bus) (bus)
) )
(connector
(text "s4" (rect 1386 24 1396 41)(font "Intel Clear" ))
(pt 1376 40)
(pt 1424 40)
)
(connector
(pt 872 -152)
(pt 872 24)
(bus)
)
(connector
(pt 872 24)
(pt 872 56)
(bus)
)
(connector
(text "RAMd_wren" (rect 1386 40 1445 57)(font "Intel Clear" ))
(pt 1376 56)
(pt 1440 56)
)
(connector
(text "ALU_en" (rect 1386 88 1423 105)(font "Intel Clear" ))
(pt 1376 104)
(pt 1424 104)
)
(connector (connector
(text "Rs1[15..0]" (rect 850 600 897 617)(font "Intel Clear" )) (text "Rs1[15..0]" (rect 850 600 897 617)(font "Intel Clear" ))
(pt 840 616) (pt 840 616)
@ -3054,9 +2911,208 @@ refer to the applicable agreement for further details.
(pt 1440 440) (pt 1440 440)
) )
(connector (connector
(text "s5" (rect 1386 168 1396 185)(font "Intel Clear" )) (pt 1512 296)
(pt 1376 184) (pt 1416 296)
(pt 1424 184) (bus)
)
(connector
(pt 1416 296)
(pt 1416 256)
(bus)
)
(connector
(pt 1416 256)
(pt 1160 256)
(bus)
)
(connector
(pt 1160 192)
(pt 1160 256)
(bus)
)
(connector
(pt 1160 256)
(pt 1160 304)
(bus)
)
(connector
(pt 872 -152)
(pt 872 24)
(bus)
)
(connector
(pt 872 24)
(pt 872 56)
(bus)
)
(connector
(text "instr[15..0]" (rect 890 -168 939 -151)(font "Intel Clear" ))
(pt 872 -152)
(pt 1176 -152)
(bus)
)
(connector
(text "FETCH" (rect 1146 -152 1177 -135)(font "Intel Clear" ))
(pt 1136 -136)
(pt 1176 -136)
)
(connector
(text "EXEC1" (rect 1146 -136 1177 -119)(font "Intel Clear" ))
(pt 1136 -120)
(pt 1176 -120)
)
(connector
(text "EXEC2" (rect 1146 -120 1177 -103)(font "Intel Clear" ))
(pt 1136 -104)
(pt 1176 -104)
)
(connector
(text "COND" (rect 1146 -104 1175 -87)(font "Intel Clear" ))
(pt 1136 -88)
(pt 1176 -88)
)
(connector
(text "R1_en" (rect 1394 -136 1424 -119)(font "Intel Clear" ))
(pt 1384 -120)
(pt 1432 -120)
)
(connector
(text "R0_en" (rect 1394 -152 1424 -135)(font "Intel Clear" ))
(pt 1384 -136)
(pt 1432 -136)
)
(connector
(text "R0_count" (rect 1394 -168 1438 -151)(font "Intel Clear" ))
(pt 1384 -152)
(pt 1432 -152)
)
(connector
(text "R2_en" (rect 1394 -120 1424 -103)(font "Intel Clear" ))
(pt 1384 -104)
(pt 1432 -104)
)
(connector
(text "R3_en" (rect 1394 -104 1424 -87)(font "Intel Clear" ))
(pt 1384 -88)
(pt 1432 -88)
)
(connector
(text "R4_en" (rect 1394 -88 1424 -71)(font "Intel Clear" ))
(pt 1384 -72)
(pt 1432 -72)
)
(connector
(text "R5_en" (rect 1394 -72 1424 -55)(font "Intel Clear" ))
(pt 1384 -56)
(pt 1432 -56)
)
(connector
(text "R6_en" (rect 1394 -56 1424 -39)(font "Intel Clear" ))
(pt 1384 -40)
(pt 1432 -40)
)
(connector
(text "R7_en" (rect 1394 -40 1424 -23)(font "Intel Clear" ))
(pt 1384 -24)
(pt 1432 -24)
)
(connector
(text "s1[2..0]" (rect 1394 -24 1428 -7)(font "Intel Clear" ))
(pt 1384 -8)
(pt 1432 -8)
(bus)
)
(connector
(text "s2[2..0]" (rect 1394 -8 1428 9)(font "Intel Clear" ))
(pt 1384 8)
(pt 1432 8)
(bus)
)
(connector
(text "s3[2..0]" (rect 1394 8 1428 25)(font "Intel Clear" ))
(pt 1384 24)
(pt 1432 24)
(bus)
)
(connector
(text "RAMd_wren" (rect 1394 40 1453 57)(font "Intel Clear" ))
(pt 1384 56)
(pt 1448 56)
)
(connector
(text "RAMd_en" (rect 1394 56 1441 73)(font "Intel Clear" ))
(pt 1384 72)
(pt 1432 72)
)
(connector
(text "RAMi_en" (rect 1394 72 1437 89)(font "Intel Clear" ))
(pt 1384 88)
(pt 1432 88)
)
(connector
(text "ALU_en" (rect 1394 88 1431 105)(font "Intel Clear" ))
(pt 1384 104)
(pt 1432 104)
)
(connector
(text "E2" (rect 1394 104 1405 121)(font "Intel Clear" ))
(pt 1384 120)
(pt 1432 120)
)
(connector
(text "stack_en" (rect 1394 120 1436 137)(font "Intel Clear" ))
(pt 1384 136)
(pt 1432 136)
)
(connector
(text "stack_rst" (rect 1394 136 1436 153)(font "Intel Clear" ))
(pt 1384 152)
(pt 1432 152)
)
(connector
(text "stack_rw" (rect 1394 152 1436 169)(font "Intel Clear" ))
(pt 1384 168)
(pt 1432 168)
)
(connector
(text "s4" (rect 1394 24 1404 41)(font "Intel Clear" ))
(pt 1384 40)
(pt 1432 40)
)
(connector
(text "s5" (rect 1394 168 1404 185)(font "Intel Clear" ))
(pt 1384 184)
(pt 1432 184)
)
(connector
(pt 1168 152)
(pt 1168 248)
(bus)
)
(connector
(pt 872 152)
(pt 1088 152)
(bus)
)
(connector
(pt 1088 152)
(pt 1168 152)
(bus)
)
(connector
(pt 1168 248)
(pt 1440 248)
(bus)
)
(connector
(pt 1440 248)
(pt 1440 264)
(bus)
)
(connector
(pt 1440 264)
(pt 1512 264)
(bus)
) )
(junction (pt 856 192)) (junction (pt 856 192))
(junction (pt 136 320)) (junction (pt 136 320))
@ -3085,3 +3141,5 @@ refer to the applicable agreement for further details.
(junction (pt 1416 496)) (junction (pt 1416 496))
(junction (pt 536 192)) (junction (pt 536 192))
(junction (pt 872 24)) (junction (pt 872 24))
(junction (pt 1160 256))
(junction (pt 1088 152))

2
CPUProject.qsf
View file

@ -41,7 +41,7 @@ set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY CPUProject set_global_assignment -name TOP_LEVEL_ENTITY CPUProject
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020" set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition" set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL

BIN
CPUProject.qws
View file

Binary file not shown.

7
DECODE.bsf
View file

@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 2018 Intel Corporation. All rights reserved. Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic and other software and tools, and any partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
(including device programming or simulation files), and any (including device programming or simulation files), and any
associated documentation or information are expressly subject associated documentation or information are expressly subject
@ -16,7 +16,8 @@ the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details. refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/ */
(header "symbol" (version "1.1")) (header "symbol" (version "1.1"))
(symbol (symbol

26
DECODE.v
View file

@ -54,33 +54,33 @@ module DECODE
wire STP = ~msb & op[5] & op[4] & op[3] & op[2] & op[1] & op[0]; wire STP = ~msb & op[5] & op[4] & op[3] & op[2] & op[1] & op[0];
assign R0_count = EXEC1 & (~(JMP | (JCX & COND_result) | STP)); assign R0_count = EXEC1 & (~(JMP | (JCX & COND_result) | STP));
assign R0_en = (EXEC1 & (~(STA | NOP | STP | LDA | PSH) & ~Rd[2] & ~Rd[1] & ~Rd[0] | JMP | JCX & COND_result)) | (EXEC2 & LDA & ~Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR) & ~Rd[2] & ~Rd[1] & ~Rd[0]); assign R0_en = (EXEC1 & (~(STA | NOP | STP | LDA | PSH | LDR) & ~Rd[2] & ~Rd[1] & ~Rd[0] | JMP | JCX & COND_result)) | (EXEC2 & LDA & ~Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & ~Rd[1] & ~Rd[0]);
assign R1_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH) & ~Rd[2] & ~Rd[1] & Rd[0]) | (EXEC2 & LDA & ~Rls[2] & ~Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR) & ~Rd[2] & ~Rd[1] & Rd[0]); assign R1_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & ~Rd[2] & ~Rd[1] & Rd[0]) | (EXEC2 & LDA & ~Rls[2] & ~Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & ~Rd[1] & Rd[0]);
assign R2_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH) & ~Rd[2] & Rd[1] & ~Rd[0]) | (EXEC2 & LDA & ~Rls[2] & Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR) & ~Rd[2] & Rd[1] & ~Rd[0]); assign R2_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & ~Rd[2] & Rd[1] & ~Rd[0]) | (EXEC2 & LDA & ~Rls[2] & Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & Rd[1] & ~Rd[0]);
assign R3_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH) & ~Rd[2] & Rd[1] & Rd[0]) | (EXEC2 & LDA & ~Rls[2] & Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR) & ~Rd[2] & Rd[1] & Rd[0]); assign R3_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & ~Rd[2] & Rd[1] & Rd[0]) | (EXEC2 & LDA & ~Rls[2] & Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & Rd[1] & Rd[0]);
assign R4_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH) & Rd[2] & ~Rd[1] & ~Rd[0]) | (EXEC2 & LDA & Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR) & Rd[2] & ~Rd[1] & ~Rd[0]); assign R4_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & Rd[2] & ~Rd[1] & ~Rd[0]) | (EXEC2 & LDA & Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & Rd[2] & ~Rd[1] & ~Rd[0]);
assign R5_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH) & Rd[2] & ~Rd[1] & Rd[0]) | (EXEC2 & LDA & Rls[2] & ~Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR) & Rd[2] & ~Rd[1] & Rd[0]); assign R5_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & Rd[2] & ~Rd[1] & Rd[0]) | (EXEC2 & LDA & Rls[2] & ~Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & Rd[2] & ~Rd[1] & Rd[0]);
assign R6_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH) & Rd[2] & Rd[1] & ~Rd[0]) | (EXEC2 & LDA & Rls[2] & Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR) & Rd[2] & Rd[1] & ~Rd[0]); assign R6_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & Rd[2] & Rd[1] & ~Rd[0]) | (EXEC2 & LDA & Rls[2] & Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & Rd[2] & Rd[1] & ~Rd[0]);
assign R7_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH) & Rd[2] & Rd[1] & Rd[0]) | (EXEC2 & LDA & Rls[2] & Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR) & Rd[2] & Rd[1] & Rd[0]); assign R7_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & Rd[2] & Rd[1] & Rd[0]) | (EXEC2 & LDA & Rls[2] & Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & Rd[2] & Rd[1] & Rd[0]);
assign s1[2] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[2]) | (STA & Rls[2]); assign s1[2] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[2]) | (STA & Rls[2]);
assign s1[1] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[1]) | (STA & Rls[1]); assign s1[1] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[1]) | (STA & Rls[1]);
assign s1[0] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[0]) | (STA & Rls[0]); assign s1[0] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[0]) | (STA & Rls[0]);
assign s2[2] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[2]); assign s2[2] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[2]);
assign s2[1] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[1]); assign s2[1] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[1]);
assign s2[0] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[0]); assign s2[0] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[0]);
assign s3[2] = (~(STA | LDA | NOP | STP | PSH | POP | LDR) & Rd[2]); assign s3[2] = (~(STA | LDA | NOP | STP | PSH | POP) & Rd[2]);
assign s3[1] = (~(STA | LDA | NOP | STP | PSH | POP | LDR) & Rd[1]); assign s3[1] = (~(STA | LDA | NOP | STP | PSH | POP) & Rd[1]);
assign s3[0] = (~(STA | LDA | NOP | STP | PSH | POP | LDR) & Rd[0]); assign s3[0] = (~(STA | LDA | NOP | STP | PSH | POP) & Rd[0]);
assign s4 = ~(LDA | LDR); assign s4 = ~(LDA | LDR);
assign RAMd_wren = EXEC1 & (STA | STR); assign RAMd_wren = EXEC1 & (STA | STR);
assign RAMd_en = EXEC1 & (STA | LDA | STR | LDR); assign RAMd_en = EXEC1 & (STA | LDA | STR | LDR);
assign RAMi_en = FETCH; assign RAMi_en = FETCH;
assign ALU_en = LDA | STA; assign ALU_en = LDA | STA;
assign E2 = EXEC1 & (LDA | MUL | MLA | MLS | POP); assign E2 = EXEC1 & (LDA | MUL | MLA | MLS | POP | LDR);
assign stack_en = (EXEC1 & PSH) | ((EXEC1 | EXEC2) & POP); assign stack_en = (EXEC1 & PSH) | ((EXEC1 | EXEC2) & POP);
assign stack_rst = STP; assign stack_rst = STP;
assign stack_rw = EXEC1 & PSH; assign stack_rw = EXEC1 & PSH;
assign s5 = (EXEC1 & STR) | (EXEC2 & LDR); assign s5 = EXEC1 & (STR | LDR);
endmodule endmodule

8
instr.mif
View file

@ -85,6 +85,10 @@ CONTENT BEGIN
60 : A810; 60 : A810;
61 : 226D; 61 : 226D;
62 : 246D; 62 : 246D;
63 : 7E00; 63 : 8805;
[64..2047] : 0000; 64 : 5488;
65 : 5698;
66 : A028;
67 : 7E00;
[68..2047] : 0000;
END; END;